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authorRichard Sandiford <richard.sandiford@arm.com>2023-03-30 11:09:02 +0100
committerRichard Sandiford <richard.sandiford@arm.com>2023-03-30 11:09:02 +0100
commita5791d5814226054215b7aab9f87dec6b8e41664 (patch)
tree6c3d02b8085caa28f0053d1eeee02fe7b2ade17b /opcodes/aarch64-dis.c
parenteee2ecccdaa37d6c5d283d6346f70897ba27166b (diff)
downloadbinutils-gdb-a5791d5814226054215b7aab9f87dec6b8e41664.tar.gz
aarch64: Make SME instructions use F_STRICT
This patch makes all SME instructions use F_STRICT, so that qualifiers have to be provided explicitly rather than being inferred from other operands. The main change is to move the qualifier setting from the operand-level decoders to the opcode level. This is one step towards consolidating the ZA parsing code and extending it to handle SME2.
Diffstat (limited to 'opcodes/aarch64-dis.c')
-rw-r--r--opcodes/aarch64-dis.c93
1 files changed, 46 insertions, 47 deletions
diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c
index 02ce8345979..01881ea377d 100644
--- a/opcodes/aarch64-dis.c
+++ b/opcodes/aarch64-dis.c
@@ -1785,44 +1785,35 @@ aarch64_ext_sme_za_hv_tiles (const aarch64_operand *self,
/* Deduce qualifier encoded in size and Q fields. */
if (fld_size == 0)
- info->qualifier = AARCH64_OPND_QLF_S_B;
- else if (fld_size == 1)
- info->qualifier = AARCH64_OPND_QLF_S_H;
- else if (fld_size == 2)
- info->qualifier = AARCH64_OPND_QLF_S_S;
- else if (fld_size == 3 && fld_q == 0)
- info->qualifier = AARCH64_OPND_QLF_S_D;
- else if (fld_size == 3 && fld_q == 1)
- info->qualifier = AARCH64_OPND_QLF_S_Q;
-
- info->za_tile_vector.index.regno = fld_rv + 12;
- info->za_tile_vector.v = fld_v;
-
- switch (info->qualifier)
{
- case AARCH64_OPND_QLF_S_B:
info->za_tile_vector.regno = 0;
info->za_tile_vector.index.imm = fld_zan_imm;
- break;
- case AARCH64_OPND_QLF_S_H:
+ }
+ else if (fld_size == 1)
+ {
info->za_tile_vector.regno = fld_zan_imm >> 3;
info->za_tile_vector.index.imm = fld_zan_imm & 0x07;
- break;
- case AARCH64_OPND_QLF_S_S:
+ }
+ else if (fld_size == 2)
+ {
info->za_tile_vector.regno = fld_zan_imm >> 2;
info->za_tile_vector.index.imm = fld_zan_imm & 0x03;
- break;
- case AARCH64_OPND_QLF_S_D:
+ }
+ else if (fld_size == 3 && fld_q == 0)
+ {
info->za_tile_vector.regno = fld_zan_imm >> 1;
info->za_tile_vector.index.imm = fld_zan_imm & 0x01;
- break;
- case AARCH64_OPND_QLF_S_Q:
+ }
+ else if (fld_size == 3 && fld_q == 1)
+ {
info->za_tile_vector.regno = fld_zan_imm;
info->za_tile_vector.index.imm = 0;
- break;
- default:
- return false;
}
+ else
+ return false;
+
+ info->za_tile_vector.index.regno = fld_rv + 12;
+ info->za_tile_vector.v = fld_v;
return true;
}
@@ -1914,26 +1905,14 @@ aarch64_ext_sme_pred_reg_with_index (const aarch64_operand *self,
info->za_tile_vector.regno = fld_pn;
info->za_tile_vector.index.regno = fld_rm + 12;
- if (fld_tszh == 0x1 && fld_tszl == 0x0)
- {
- info->qualifier = AARCH64_OPND_QLF_S_D;
- imm = fld_i1;
- }
- else if (fld_tszl == 0x4)
- {
- info->qualifier = AARCH64_OPND_QLF_S_S;
- imm = (fld_i1 << 1) | fld_tszh;
- }
- else if ((fld_tszl & 0x3) == 0x2)
- {
- info->qualifier = AARCH64_OPND_QLF_S_H;
- imm = (fld_i1 << 2) | (fld_tszh << 1) | (fld_tszl >> 2);
- }
- else if (fld_tszl & 0x1)
- {
- info->qualifier = AARCH64_OPND_QLF_S_B;
- imm = (fld_i1 << 3) | (fld_tszh << 2) | (fld_tszl >> 1);
- }
+ if (fld_tszl & 0x1)
+ imm = (fld_i1 << 3) | (fld_tszh << 2) | (fld_tszl >> 1);
+ else if (fld_tszl & 0x2)
+ imm = (fld_i1 << 2) | (fld_tszh << 1) | (fld_tszl >> 2);
+ else if (fld_tszl & 0x4)
+ imm = (fld_i1 << 1) | fld_tszh;
+ else if (fld_tszh)
+ imm = fld_i1;
else
return false;
@@ -2975,6 +2954,25 @@ aarch64_decode_variant_using_iclass (aarch64_inst *inst)
variant = 0;
switch (inst->opcode->iclass)
{
+ case sme_mov:
+ variant = extract_fields (inst->value, 0, 2, FLD_SME_Q, FLD_SME_size_10);
+ if (variant >= 4 && variant < 7)
+ return false;
+ if (variant == 7)
+ variant = 4;
+ break;
+
+ case sme_psel:
+ i = extract_fields (inst->value, 0, 2, FLD_SME_tszh, FLD_SME_tszl);
+ if (i == 0)
+ return false;
+ while ((i & 1) == 0)
+ {
+ i >>= 1;
+ variant += 1;
+ }
+ break;
+
case sve_cpy:
variant = extract_fields (inst->value, 0, 2, FLD_size, FLD_SVE_M_14);
break;
@@ -3002,8 +3000,9 @@ aarch64_decode_variant_using_iclass (aarch64_inst *inst)
variant = 3;
break;
+ case sme_misc:
case sve_misc:
- /* sve_misc instructions have only a single variant. */
+ /* These instructions have only a single variant. */
break;
case sve_movprfx: