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| author | Richard Sandiford <richard.sandiford@arm.com> | 2023-03-30 11:09:12 +0100 |
|---|---|---|
| committer | Richard Sandiford <richard.sandiford@arm.com> | 2023-03-30 11:09:12 +0100 |
| commit | cbd11b8818335007cf960e0cecc4dec445f80327 (patch) | |
| tree | 0c93cdb222610d90df1b5d74fd31c55b3c6db96f /opcodes/aarch64-asm.c | |
| parent | 99e01a66b4c619fb8c7d6f978038eb7a3661c160 (diff) | |
| download | binutils-gdb-cbd11b8818335007cf960e0cecc4dec445f80327.tar.gz | |
aarch64: Add the SME2 ZT0 instructions
SME2 adds lookup table instructions for quantisation. They use
a new lookup table register called ZT0.
LUTI2 takes an unsuffixed SVE vector index of the form Zn[<imm>],
which is the first time that this syntax has been used.
Diffstat (limited to 'opcodes/aarch64-asm.c')
| -rw-r--r-- | opcodes/aarch64-asm.c | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/opcodes/aarch64-asm.c b/opcodes/aarch64-asm.c index acfec3773dc..bd03f4116cc 100644 --- a/opcodes/aarch64-asm.c +++ b/opcodes/aarch64-asm.c @@ -404,6 +404,8 @@ aarch64_ins_imm (const aarch64_operand *self, const aarch64_opnd_info *info, imm = info->imm.value; if (operand_need_shift_by_two (self)) imm >>= 2; + if (operand_need_shift_by_three (self)) + imm >>= 3; if (operand_need_shift_by_four (self)) imm >>= 4; insert_all_fields (self, code, imm); @@ -1946,11 +1948,21 @@ aarch64_encode_variant_using_iclass (struct aarch64_inst *inst) /* The variant is encoded as part of the immediate. */ break; + case sme_size_12_bhs: + insert_field (FLD_SME_size_12, &inst->value, + aarch64_get_variant (inst), 0); + break; + case sme_size_22: insert_field (FLD_SME_size_22, &inst->value, aarch64_get_variant (inst), 0); break; + case sme_size_12_hs: + insert_field (FLD_SME_size_12, &inst->value, + aarch64_get_variant (inst) + 1, 0); + break; + case sve_cpy: insert_fields (&inst->value, aarch64_get_variant (inst), 0, 2, FLD_SVE_M_14, FLD_size); |