ChangeLog rotatation and copyright year update

1 files changed, 897 insertions, 0 deletions

diff --git a/opcodes/ChangeLog-2014 b/opcodes/ChangeLog-2014
new file mode 100644
index 00000000000..dd302b2d3fa
--- /dev/null
+++ b/opcodes/ChangeLog-2014
@@ -0,0 +1,897 @@
+2014-12-27  Anthony Green  <green@moxielofic.com
+
+	* moxie-opc.c (moxie_form1_opc_info): sto/ldo are now encoded with
+	16-bit immediat values instead of 32.
+	* moxie-dis.c (print_insn_moxie): Ditto.
+
+2014-12-24  Anthony Green  <green@moxielogic.com>
+
+	* moxie-opc: Define mul.x and umul.x instructions.  Remove
+	trailing .l from add, sub, mul, div and udiv instructions.
+
+2014-12-16  Matthew Fortune  <matthew.fortune@imgtec.com>
+
+	* mips-opc.c (mips_builtin_opcodes): Add JALRC alias for
+	JIALC.  Remove the operand from NAL.
+
+2014-12-12  Anthony Green  <green@moxielogic.com>
+
+	* moxie-opc.c: Define zex instructions.
+
+2014-12-06  Eric Botcazou  <ebotcazou@adacore.com>
+
+	* configure.ac: Add Visium support.
+	* configure: Regenerate.
+	* Makefile.am (TARGET_LIBOPCODES_CFILES): Add visium-dis.c and
+	visium-opc.c.
+	* Makefile.in: Regenerate.
+	* disassemble.c (ARCH_visium): Define if ARCH_all.
+	(disassembler): Deal with bfd_arch_visium if ARCH_visium.
+	* visium-dis.c: New file.
+	* visium-opc.c: Likewise.
+	* po/POTFILES.in: Regenerate.
+
+2014-11-30  Alan Modra  <amodra@gmail.com>
+
+	* ppc-opc.c (powerpc_opcodes): Make mftb* generate mfspr for
+	power4 and later.
+
+2014-11-28  Sandra Loosemore  <sandra@codesourcery.com>
+
+	* nios2-opc.c (nios2_r1_opcodes): Remove deleted attributes
+	from descriptors.
+
+2014-11-28  Alan Modra  <amodra@gmail.com>
+
+	* ppc-opc.c (powerpc_opcodes <mftb>): Don't deprecate for power7.
+	(TB): Delete.
+	(insert_tbr, extract_tbr): Validate tbr number.
+
+2014-11-24  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* configure: Regenerated.
+
+2014-11-17  Ilya Tocar  <ilya.tocar@intel.com>
+
+	* i386-dis-evex.c (evex_table): Add vpermi2b, vpermt2b, vpermb,
+	vpmultishiftqb.
+	* i386-dis.c (PREFIX enum): Add PREFIX_EVEX_0F3883, EVEX_W_0F3883_P_2.
+	* i386-gen.c (cpu_flag_init): Add CPU_AVX512VBMI_FLAGS.
+	(cpu_flags): Add CpuAVX512VBMI.
+	* i386-opc.h (enum): Add CpuAVX512VBMI.
+	(i386_cpu_flags): Add cpuavx512vbmi.
+	* i386-opc.tbl: Add vpmadd52luq, vpmultishiftqb, vpermb, vpermi2b,
+	vpermt2b.
+	* i386-init.h: Regenerated.
+	* i386-tbl.h: Likewise.
+
+2014-11-17  Ilya Tocar  <ilya.tocar@intel.com>
+
+	* i386-dis-evex.c (evex_table): Add vpmadd52luq, vpmadd52huq.
+	* i386-dis.c (PREFIX enum): Add PREFIX_EVEX_0F38B4,
+	PREFIX_EVEX_0F38B5.
+	* i386-gen.c (cpu_flag_init): Add CPU_AVX512IFMA_FLAGS.
+	(cpu_flags): Add CpuAVX512IFMA.
+	* i386-opc.h (enum): Add CpuAVX512IFMA.
+	(i386_cpu_flags): Add cpuavx512ifma.
+	* i386-opc.tbl: Add vpmadd52huq, vpmadd52luq.
+	* i386-init.h: Regenerated.
+	* i386-tbl.h: Likewise.
+
+2014-11-17  Ilya Tocar  <ilya.tocar@intel.com>
+
+	* i386-dis.c (PREFIX enum): Add PREFIX_RM_0_0FAE_REG_7.
+	(prefix_table): Add pcommit.
+	* i386-gen.c (cpu_flag_init): Add CPU_PCOMMIT_FLAGS.
+	(cpu_flags): Add CpuPCOMMIT.
+	* i386-opc.h (enum): Add CpuPCOMMIT.
+	(i386_cpu_flags): Add cpupcommit.
+	* i386-opc.tbl: Add pcommit.
+	* i386-init.h: Regenerated.
+	* i386-tbl.h: Likewise.
+
+2014-11-17  Ilya Tocar  <ilya.tocar@intel.com>
+
+	* i386-dis.c (PREFIX enum): Add PREFIX_0FAE_REG_6.
+	(prefix_table): Add clwb.
+	* i386-gen.c (cpu_flag_init): Add CPU_CLWB_FLAGS.
+	(cpu_flags): Add CpuCLWB.
+	* i386-opc.h (enum): Add CpuCLWB.
+	(i386_cpu_flags): Add cpuclwb.
+	* i386-opc.tbl: Add clwb.
+	* i386-init.h: Regenerated.
+	* i386-tbl.h: Likewise.
+
+2014-11-06  Sandra Loosemore  <sandra@codesourcery.com>
+
+	* nios2-dis.c (nios2_find_opcode_hash): Add mach parameter.
+	(nios2_disassemble): Adjust call to nios2_find_opcode_hash.
+
+2014-11-03  Nick Clifton  <nickc@redhat.com>
+
+	* po/fi.po: Updated Finnish translation.
+
+2014-10-31  Andrew Pinski  <apinski@cavium.com>
+            Naveen H.S  <Naveen.Hurugalawadi@caviumnetworks.com>
+
+	* mips-dis.c (mips_arch_choices): Add octeon3.
+	* mips-opc.c (IOCT): Include INSN_OCTEON3.
+	(IOCT2): Likewise.
+	(IOCT3): New define.
+	(IVIRT): New define.
+	(mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
+	tlbinv, tlbinvf, tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp, tlti
+	IVIRT instructions.
+	Extend mtm0, mtm1, mtm2, mtp0, mtp1, mtp2 instructions to take another
+	operand for IOCT3.
+
+2014-10-29  Nick Clifton  <nickc@redhat.com>
+
+	* po/de.po: Updated German translation.
+
+2014-10-23  Sandra Loosemore  <sandra@codesourcery.com>
+
+	* nios2-opc.c (nios2_builtin_regs): Add regtype field initializers.
+	(nios2_builtin_opcodes): Rename to nios2_r1_opcodes.  Use new
+	MATCH_R1_<insn> and MASK_R1_<insn> macros in initializers.  Add
+	size and format initializers.  Merge 'b' arguments into 'j'.
+	(NIOS2_NUM_OPCODES): Adjust definition.
+	(bfd_nios2_num_builtin_opcodes): Rename to nios2_num_r1_opcodes.
+	(nios2_opcodes): Adjust.
+	(bfd_nios2_num_opcodes): Rename to nios2_num_opcodes.
+	* nios2-dis.c (INSNLEN): Update comment.
+	(nios2_hash_init, nios2_hash): Delete.
+	(OPCODE_HASH_SIZE): New.
+	(nios2_r1_extract_opcode): New.
+	(nios2_disassembler_state): New.
+	(nios2_r1_disassembler_state): New.
+	(nios2_init_opcode_hash): Add state parameter.  Adjust to use it.
+	(nios2_find_opcode_hash): Use state object.
+	(bad_opcode): New.
+	(nios2_print_insn_arg): Add op parameter.  Use it to access
+	format.  Remove 'b' case.
+	(nios2_disassemble): Remove special case for nop.  Remove
+	hard-coded instruction size.
+
+2014-10-21  Jan Beulich  <jbeulich@suse.com>
+
+	* ppc-opc.c (powerpc_opcodes): Enable msgclr and msgsnd on Power8.
+
+2014-10-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
+
+	* sparc-opc.c (sparc-opcodes): Fix several misplaced hwcap
+	entries.
+	Annotate several instructions with the HWCAP2_VIS3B hwcap.
+
+2014-10-15  Tristan Gingold  <gingold@adacore.com>
+
+	* configure: Regenerate.
+
+2014-10-09  Jose E. Marchesi  &lt;jose.marchesi@oracle.com&gt;
+
+	* sparc-opc.c (sparc-opcodes): Remove instructions `chkpt',
+	`commit', `random', `wr r,r,%cps', `wr r,i,%cps' and `rd %cps,r'.
+	Annotate table with HWCAP2 bits.
+	Add instructions xmontmul, xmontsqr, xmpmul.
+	(sparc-opcodes): Add the `mwait',  `wr r,r,%mwait', `wr
+	r,i,%mwait' and `rd %mwait,r' instructions.
+	Add rd/wr instructions for accessing the %mcdper ancillary state
+	register.
+	(sparc-opcodes): Add sparc5/vis4.0 instructions:
+	subxc, subxccc, fpadd8, fpadds8, fpaddus8, fpaddus16, fpcmple8,
+	fpcmpgt8, fpcmpule16, fpcmpugt16, fpcmpule32, fpcmpugt32, fpmax8,
+	fpmax16, fpmax32, fpmaxu8, fpmaxu16, fpmaxu32, fpmin8, fpmin16,
+	fpmin32, fpminu8, fpminu16, fpminu32, fpsub8, fpsubs8, fpsubus8,
+	fpsubus16, and faligndatai.
+	* sparc-dis.c (v9a_asr_reg_names): Add the %mwait (%asr28)
+	ancillary state register to the table.
+	(print_insn_sparc): Handle the %mcdper ancillary state register.
+	(print_insn_sparc): Handle new operand type '}'.
+
+2014-09-22  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* i386-dis.c (MOD_0F20): Removed.
+	(MOD_0F21): Likewise.
+	(MOD_0F22): Likewise.
+	(MOD_0F23): Likewise.
+	(dis386_twobyte): Replace MOD_0F20, MOD_0F21, MOD_0F22 and
+	MOD_0F23 with "movZ".
+	(mod_table): Remove MOD_0F20, MOD_0F21, MOD_0F22 and MOD_0F23.
+	(OP_R): Check mod/rm byte and call OP_E_register.
+
+2014-09-16 Kuan-Lin Chen <kuanlinchentw@gmail.com>
+
+	* nds32-asm.c (nds32_opcodes, operand_fields, keyword_im5_i,
+	keyword_im5_m, keyword_accumulator, keyword_aridx, keyword_aridx2,
+	keyword_aridxi): Add audio ISA extension.
+	(keyword_gpr, keyword_usr, keyword_sr, keyword_cp, keyword_cpr,
+	keyword_fsr, keyword_fdr, keyword_abdim, keyword_abm, keyword_dpref_st,
+	keyword_cctl_lv, keyword_standby_st, keyword_msync_st): Adjust scrope
+	for nds32-dis.c using.
+	(build_opcode_syntax): Remove dead code.
+	(parse_re, parse_a30b20, parse_rt21, parse_rte_start, parse_rte_end,
+	parse_rte69_start, parse_rte69_end, parse_im5_ip, parse_im5_mr,
+	parse_im6_ip, parse_im6_iq, parse_im6_mr, parse_im6_ms): Add audio ISA
+	operand parser.
+	* nds32-asm.h: Declare.
+	* nds32-dis.c: Use array nds32_opcodes to disassemble instead of
+	decoding by switch.
+
+2014-09-15  Andrew Bennett  <andrew.bennett@imgtec.com>
+	    Matthew Fortune  <matthew.fortune@imgtec.com>
+
+	* mips-dis.c (mips_arch_choices): Add entries for mips32r6 and
+	mips64r6.
+	(parse_mips_dis_option): Allow MSA and virtualization support for
+	mips64r6.
+	(mips_print_arg_state): Add fields dest_regno and seen_dest.
+	(mips_seen_register): New function.
+	(print_insn_arg): Refactored code to use mips_seen_register
+	function.  Add support for OP_SAME_RS_RT, OP_CHECK_PREV and
+	OP_NON_ZERO_REG.  Changed OP_REPEAT_DEST_REG case to print out
+	the register rather than aborting.
+	(print_insn_args): Add length argument.  Add code to correctly
+	calculate the instruction address for pc relative instructions.
+	(validate_insn_args): New static function.
+	(print_insn_mips): Prevent jalx disassembling for r6.  Use
+	validate_insn_args.
+	(print_insn_micromips): Use validate_insn_args.
+	all the arguments are valid.
+	* mips-formats.h (PREV_CHECK): New define.
+	* mips-opc.c (decode_mips_operand): Add support for -a, -b, -d, -s,
+	-t, -u, -v, -w, -x, -y, -A, -B, +I, +O, +R, +:, +\, +", +;
+	(RD_pc): New define.
+	(FS): New define.
+	(I37): New define.
+	(I69): New define.
+	(mips_builtin_opcodes): Add MIPS R6 instructions.  Exclude recoded
+	MIPS R6 instructions from MIPS R2 instructions.
+
+2014-09-10  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* i386-dis.c (dis386): Replace "P" with "%LP" for iret and sysret.
+	(putop): Handle "%LP".
+
+2014-09-03  Jiong Wang  <jiong.wang@arm.com>
+
+	* aarch64-tbl.h (aarch64_opcode_table): Update encoding for mrs/msr.
+	* aarch64-dis-2.c: Update auto-generated file.
+
+2014-09-03  Jiong Wang  <jiong.wang@arm.com>
+
+	* aarch64-tbl.h (QL_R4NIL): New qualifiers.
+	(aarch64_feature_lse): New feature added.
+	(LSE): New Added.
+	(aarch64_opcode_table): New LSE instructions added.  Improve
+	descriptions for ldarb/ldarh/ldar.
+	(aarch64_opcode_table): Describe PAIRREG.
+	* aarch64-opc.h (aarch64_field_kind): Add FLD_lse_sz.
+	* aarch64-opc.c (fields): Add entry for F_LSE_SZ.
+	(aarch64_print_operand): Recognize PAIRREG.
+	(operand_general_constraint_met_p): Check reg pair constraints for CASP
+	instructions.
+	* aarch64-dis.c (aarch64_ext_regno_pair): New extractor for paired reg.
+	(do_special_decoding): Recognize F_LSE_SZ.
+	* aarch64-asm.c (do_special_encoding): Recognize F_LSE_SZ.
+
+2014-08-26  Maciej W. Rozycki  <macro@codesourcery.com>
+
+	* micromips-opc.c (decode_micromips_operand): Rename `B' to `+J'.
+	(micromips_opcodes): Use "+J" in place of "B" for "hypcall",
+	"sdbbp", "syscall" and "wait".
+
+2014-08-21  Nathan Sidwell  <nathan@codesourcery.com>
+	    Maciej W. Rozycki  <macro@codesourcery.com>
+
+	* arm-dis.c (print_arm_address): Negate the GPR-relative offset
+	returned if the U bit is set.
+
+2014-08-21  Maciej W. Rozycki  <macro@codesourcery.com>
+
+	* micromips-opc.c (micromips_opcodes): Remove #ifdef-ed out
+	48-bit "li" encoding.
+
+2014-08-19  Andreas Arnez  <arnez@linux.vnet.ibm.com>
+
+	* s390-dis.c (s390_insn_length, s390_insn_matches_opcode)
+	(s390_print_insn_with_opcode, opcode_mask_more_specific): New
+	static functions, code was moved from...
+	(print_insn_s390): ...here.
+	(s390_extract_operand): Adjust comment.  Change type of first
+	parameter from 'unsigned char *' to 'const bfd_byte *'.
+	(union operand_value): New.
+	(s390_extract_operand): Change return type to union operand_value.
+	Also avoid integer overflow in sign-extension.
+	(s390_print_insn_with_opcode): Adjust to changed return value from
+	s390_extract_operand().  Change "%i" printf format to "%u" for
+	unsigned values.
+	(init_disasm): Simplify initialization of opc_index[].  This also
+	fixes an access after the last element of s390_opcodes[].
+	(print_insn_s390): Simplify the opcode search loop.
+	Check architecture mask against all searched opcodes, not just the
+	first matching one.
+	(s390_print_insn_with_opcode): Drop function pointer dereferences
+	without effect.
+	(print_insn_s390): Likewise.
+	(s390_insn_length): Simplify formula for return value.
+	(s390_print_insn_with_opcode): Avoid special handling for the
+	separator before the first operand.  Use new local variable
+	'flags' in place of 'operand->flags'.
+
+2014-08-14  Mike Frysinger  <vapier@gentoo.org>
+
+	* bfin-dis.c (struct private): Change int's to bfd_boolean's.
+	(decode_LOGI2op_0, decode_COMPI2opD_0, decode_COMPI2opP_0,
+	decode_dagMODik_0, decode_LDIMMhalf_0, decode_linkage_0):
+	Change assignment of 1 to priv->comment to TRUE.
+	(print_insn_bfin): Change legal to a bfd_boolean.  Change
+	assignment of 0/1 with priv comment and parallel and legal
+	to FALSE/TRUE.
+
+2014-08-14  Mike Frysinger  <vapier@gentoo.org>
+
+	* bfin-dis.c (OUT): Define.
+	(decode_CC2stat_0): Declare new op_names array.
+	Replace multiple if statements with a single one.
+
+2014-08-14  Mike Frysinger  <vapier@gentoo.org>
+
+	* bfin-dis.c (struct private): Add iw0.
+	(_print_insn_bfin): Assign iw0 to priv.iw0.
+	(print_insn_bfin): Drop ifetch and use priv.iw0.
+
+2014-08-13  Mike Frysinger  <vapier@gentoo.org>
+
+	* bfin-dis.c (comment, parallel): Move from global scope ...
+	(struct private): ... to this new struct.
+	(decode_ProgCtrl_0, decode_CaCTRL_0, decode_PushPopReg_0,
+	decode_PushPopMultiple_0, decode_ccMV_0, decode_CCflag_0,
+	decode_CC2dreg_0, decode_CC2stat_0, decode_BRCC_0, decode_UJUMP_0,
+	decode_LOGI2op_0, decode_COMPI2opD_0, decode_COMPI2opP_0,
+	decode_dagMODik_0, decode_LoopSetup_0, decode_LDIMMhalf_0,
+	decode_CALLa_0, decode_linkage_0, decode_pseudoDEBUG_0,
+	decode_pseudoOChar_0, decode_pseudodbg_assert_0, _print_insn_bfin,
+	print_insn_bfin): Declare private struct.  Use priv's comment and
+	parallel members.
+
+2014-08-13  Mike Frysinger  <vapier@gentoo.org>
+
+	* bfin-dis.c (ifetch): Do not align pc to 2 bytes.
+	(_print_insn_bfin): Add check for unaligned pc.
+
+2014-08-13  Mike Frysinger  <vapier@gentoo.org>
+
+	* bfin-dis.c (ifetch): New function.
+	(_print_insn_bfin, print_insn_bfin): Call new ifetch and return
+	-1 when it errors.
+
+2014-07-29  Matthew Fortune  <matthew.fortune@imgtec.com>
+
+	* micromips-opc.c (COD): Rename throughout to...
+	(CM): New define, update to use INSN_COPROC_MOVE.
+	(LCD): Rename throughout to...
+	(LC): New define, update to use INSN_LOAD_COPROC.
+	* mips-opc.c: Likewise.
+
+2014-07-29  Matthew Fortune  <matthew.fortune@imgtec.com>
+
+	* micromips-opc.c (COD, LCD) New macros.
+	(cfc1, ctc1): Remove FP_S attribute.
+	(dmfc1, mfc1, mfhc1): Add LCD attribute.
+	(dmtc1, mtc1, mthc1): Add COD attribute.
+	* mips-opc.c (cfc1, cftc1, ctc, cttc1): Remove FP_S attribute.
+
+2014-07-22  Sergey Guriev  <sergey.s.guriev@intel.com>
+	    Alexander Ivchenko  <alexander.ivchenko@intel.com>
+	    Maxim Kuznetsov  <maxim.kuznetsov@intel.com>
+	    Sergey Lega  <sergey.s.lega@intel.com>
+	    Anna Tikhonova  <anna.tikhonova@intel.com>
+	    Ilya Tocar  <ilya.tocar@intel.com>
+	    Andrey Turetskiy  <andrey.turetskiy@intel.com>
+	    Ilya Verbin  <ilya.verbin@intel.com>
+	    Kirill Yukhin  <kirill.yukhin@intel.com>
+	    Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
+
+	* i386-dis-evex.h: Updated.
+	* i386-dis.c (PREFIX enum): Add PREFIX_EVEX_0F54, PREFIX_EVEX_0F55,
+	PREFIX_EVEX_0F56, PREFIX_EVEX_0F57, PREFIX_EVEX_0F3A16,
+	PREFIX_EVEX_0F3A22, PREFIX_EVEX_0F3A50, PREFIX_EVEX_0F3A51,
+	PREFIX_EVEX_0F3A56, PREFIX_EVEX_0F3A57, PREFIX_EVEX_0F3A66,
+	PREFIX_EVEX_0F3A67.
+	(VEX_LEN enum): Add VEX_LEN_0F92_P_2, VEX_LEN_0F93_P_2,
+	VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_2_LEN_0.
+	(VEX_W enum): Add EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, EVEX_W_0F55_P_0,
+	EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, EVEX_W_0F56_P_2, EVEX_W_0F57_P_0,
+	EVEX_W_0F57_P_2, EVEX_W_0F78_P_2, EVEX_W_0F79_P_2, EVEX_W_0F7A_P_2,
+	EVEX_W_0F7B_P_2, EVEX_W_0F3838_P_1, EVEX_W_0F3839_P_1,
+	EVEX_W_0F3A16_P_2, EVEX_W_0F3A22_P_2, EVEX_W_0F3A50_P_2,
+	EVEX_W_0F3A51_P_2, EVEX_W_0F3A56_P_2, EVEX_W_0F3A57_P_2,
+	EVEX_W_0F3A66_P_2, EVEX_W_0F3A67_P_2.
+	(prefix_table): Add entries for new instructions.
+	(vex_len_table): Ditto.
+	(vex_w_table): Ditto.
+	(OP_E_memory): Update xmmq_mode handling.
+	* i386-gen.c (cpu_flag_init): Add CPU_AVX512DQ_FLAGS.
+	(cpu_flags): Add CpuAVX512DQ.
+	* i386-init.h: Regenerared.
+	* i386-opc.h (CpuAVX512DQ): New.
+	(i386_cpu_flags): Add cpuavx512dq.
+	* i386-opc.tbl: Add AVX512DQ instructions.
+	* i386-tbl.h: Regenerate.
+
+2014-07-22  Sergey Guriev  <sergey.s.guriev@intel.com>
+	    Alexander Ivchenko  <alexander.ivchenko@intel.com>
+	    Maxim Kuznetsov  <maxim.kuznetsov@intel.com>
+	    Sergey Lega  <sergey.s.lega@intel.com>
+	    Anna Tikhonova  <anna.tikhonova@intel.com>
+	    Ilya Tocar  <ilya.tocar@intel.com>
+	    Andrey Turetskiy  <andrey.turetskiy@intel.com>
+	    Ilya Verbin  <ilya.verbin@intel.com>
+	    Kirill Yukhin  <kirill.yukhin@intel.com>
+	    Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
+
+	* i386-dis-evex.h: Add new instructions (prefixes bellow).
+	* i386-dis.c (fetch_data): Add EdqwS, Edb, Edw, MaskBDE.
+	(enum): Add dqw_swap_mode, db_mode, dw_mode, mask_bd_mode, REG_EVEX_0F71.
+	(PREFIX enum): Add PREFIX_VEX_0F4A, PREFIX_VEX_0F99, PREFIX_VEX_0F3A31,
+	PREFIX_VEX_0F3A33, PREFIX_EVEX_0F60, PREFIX_EVEX_0F61, PREFIX_EVEX_0F63,
+	PREFIX_EVEX_0F64, PREFIX_EVEX_0F65, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
+	PREFIX_EVEX_0F69, PREFIX_EVEX_0F6B, PREFIX_EVEX_0F71_REG_2, PREFIX_EVEX_0F71_REG_4,
+	PREFIX_EVEX_0F71_REG_6, PREFIX_EVEX_0F73_REG_3, PREFIX_EVEX_0F73_REG_7,
+	PREFIX_EVEX_0F74, PREFIX_EVEX_0F75, PREFIX_EVEX_0FC4, PREFIX_EVEX_0FC5,
+	PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5, PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9,
+	PREFIX_EVEX_0FDA, PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
+	PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3, PREFIX_EVEX_0FE4,
+	PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8, PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA,
+	PREFIX_EVEX_0FEC, PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
+	PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8, PREFIX_EVEX_0FF9,
+	PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD, PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804,
+	PREFIX_EVEX_0F380B, PREFIX_EVEX_0F3810, PREFIX_EVEX_0F381C, PREFIX_EVEX_0F381D,
+	PREFIX_EVEX_0F3820, PREFIX_EVEX_0F3826, PREFIX_EVEX_0F382B, PREFIX_EVEX_0F3830,
+	PREFIX_EVEX_0F3838, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E, PREFIX_EVEX_0F3866,
+	PREFIX_EVEX_0F3875, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879, PREFIX_EVEX_0F387A,
+	PREFIX_EVEX_0F387B, PREFIX_EVEX_0F387D, PREFIX_EVEX_0F388D, PREFIX_EVEX_0F3A0F,
+	PREFIX_EVEX_0F3A14, PREFIX_EVEX_0F3A15, PREFIX_EVEX_0F3A20, PREFIX_EVEX_0F3A3E,
+	PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A42.
+	(VEX_LEN enum): Add VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_2, VEX_LEN_0F44_P_2,
+	VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_2, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
+	VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_2,
+	VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_2, VEX_LEN_0F99_P_0,
+	VEX_LEN_0F99_P_2, VEX_LEN_0F3A31_P_2, VEX_LEN_0F3A33_P_2, VEX_W_0F41_P_2_LEN_1,
+	VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_2_LEN_1,
+	VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
+	VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1, VEX_W_0F90_P_2_LEN_0,
+	VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_3_LEN_0, VEX_W_0F93_P_3_LEN_0,
+	VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0, VEX_W_0F99_P_2_LEN_0,
+	VEX_W_0F3A31_P_2_LEN_0, VEX_W_0F3A33_P_2_LEN_0.
+	(VEX_W enum): Add EVEX_W_0F6B_P_2, EVEX_W_0F6F_P_3, EVEX_W_0F7F_P_3,
+	EVEX_W_0F3810_P_1, EVEX_W_0F3810_P_2, EVEX_W_0F3811_P_2, EVEX_W_0F3812_P_2,
+	EVEX_W_0F3820_P_1, EVEX_W_0F3826_P_1, EVEX_W_0F3826_P_2, EVEX_W_0F3828_P_1,
+	EVEX_W_0F3829_P_1, EVEX_W_0F382B_P_2, EVEX_W_0F3830_P_1, EVEX_W_0F3866_P_2,
+	EVEX_W_0F3875_P_2, EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2, EVEX_W_0F387A_P_2,
+	EVEX_W_0F387B_P_2, EVEX_W_0F387D_P_2, EVEX_W_0F388D_P_2, EVEX_W_0F3A3E_P_2,
+	EVEX_W_0F3A3F_P_2, EVEX_W_0F3A42_P_2.
+	(prefix_table): Add entries for new instructions.
+	(vex_table) : Ditto.
+	(vex_len_table): Ditto.
+	(vex_w_table): Ditto.
+	(intel_operand_size): Add db_mode, dw_mode, dqw_swap_mode,
+	mask_bd_mode handling.
+	(OP_E_register): Add dqw_swap_mode, dw_mode, db_mode, mask_bd_mode
+	handling.
+	(OP_E_memory): Add dqw_mode, dw_mode, dqw_swap_mode, dqb_mode, db_mode
+	handling.
+	(OP_G): Add db_mode, dw_mode, dqw_swap_mode, mask_bd_mode handling.
+	(OP_EX): Add dqw_swap_mode handling.
+	(OP_VEX): Add mask_bd_mode handling.
+	(OP_Mask): Add mask_bd_mode handling.
+	* i386-gen.c (cpu_flag_init): Add CPU_AVX512BW_FLAGS.
+	(cpu_flags): Add CpuAVX512BW.
+	* i386-init.h: Regenerated.
+	* i386-opc.h (CpuAVX512BW): New.
+	(i386_cpu_flags): Add cpuavx512bw.
+	* i386-opc.tbl: Add AVX512BW instructions.
+	* i386-tbl.h: Regenerate.
+
+2014-07-22  Sergey Guriev  <sergey.s.guriev@intel.com>
+	    Alexander Ivchenko  <alexander.ivchenko@intel.com>
+	    Maxim Kuznetsov  <maxim.kuznetsov@intel.com>
+	    Sergey Lega  <sergey.s.lega@intel.com>
+	    Anna Tikhonova  <anna.tikhonova@intel.com>
+	    Ilya Tocar  <ilya.tocar@intel.com>
+	    Andrey Turetskiy  <andrey.turetskiy@intel.com>
+	    Ilya Verbin  <ilya.verbin@intel.com>
+	    Kirill Yukhin  <kirill.yukhin@intel.com>
+	    Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
+
+	* i386-opc.tbl: Add AVX512VL and AVX512CD instructions.
+	* i386-tbl.h: Regenerate.
+
+2014-07-22  Sergey Guriev  <sergey.s.guriev@intel.com>
+	    Alexander Ivchenko  <alexander.ivchenko@intel.com>
+	    Maxim Kuznetsov  <maxim.kuznetsov@intel.com>
+	    Sergey Lega  <sergey.s.lega@intel.com>
+	    Anna Tikhonova  <anna.tikhonova@intel.com>
+	    Ilya Tocar  <ilya.tocar@intel.com>
+	    Andrey Turetskiy  <andrey.turetskiy@intel.com>
+	    Ilya Verbin  <ilya.verbin@intel.com>
+	    Kirill Yukhin  <kirill.yukhin@intel.com>
+	    Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
+
+	* i386-dis.c (intel_operand_size): Support 128/256 length in
+	vex_vsib_q_w_dq_mode.
+	(OP_E_memory): Add ymmq_mode handling, handle new broadcast.
+	* i386-gen.c (cpu_flag_init): Add CPU_AVX512VL_FLAGS.
+	(cpu_flags): Add CpuAVX512VL.
+	* i386-init.h: Regenerated.
+	* i386-opc.h (CpuAVX512VL): New.
+	(i386_cpu_flags): Add cpuavx512vl.
+	(BROADCAST_1TO4, BROADCAST_1TO2): Define.
+	* i386-opc.tbl: Add AVX512VL instructions.
+	* i386-tbl.h: Regenerate.
+
+2014-07-20  Stefan Kristiansson  <stefan.kristiansson@saunalahti.fi>
+
+	* or1k-desc.c, * or1k-desc.h, * or1k-opc.c, * or1k-opc.h,
+	* or1k-opinst.c: Regenerate.
+
+2014-07-08  Ilya Tocar  <ilya.tocar@intel.com>
+
+	* i386-dis-evex.h (EVEX_W_0F10_P_1_M_1): Fix vmovss.
+	(EVEX_W_0F10_P_3_M_1): Fix vmovsd.
+
+2014-07-04  Alan Modra  <amodra@gmail.com>
+
+	* configure.ac: Rename from configure.in.
+	* Makefile.in: Regenerate.
+	* config.in: Regenerate.
+
+2014-07-04  Alan Modra  <amodra@gmail.com>
+
+	* configure.in: Include bfd/version.m4.
+	(AC_INIT, AM_INIT_AUTOMAKE): Use modern form.
+	(BFD_VERSION): Delete.
+	* Makefile.am (CONFIG_STATUS_DEPENDENCIES): Remove bfd/configure.in.
+	* configure: Regenerate.
+	* Makefile.in: Regenerate.
+
+2014-07-01  Barney Stratford   <barney_stratford@fastmail.fm>
+            Senthil Kumar Selvaraj  <senthil_kumar.selvaraj@atmel.com>
+            Pitchumani Sivanupandi  <pitchumani.s@atmel.com>
+            Soundararajan  <Sounderarajan.D@atmel.com>
+
+	* avr-dis.c (avr_operand): Handle constraint j for 16 bit lds/sts.
+	(print_insn_avr): Do not select opcode if insn ISA is avrtiny and
+	machine is not avrtiny.
+
+2014-06-26  Philippe De Muyter <phdm@macqel.be>
+
+	* or1k-desc.h (spr_field_masks): Add U suffix to the end of long
+	constants.
+
+2014-06-12  Alan Modra  <amodra@gmail.com>
+
+	* or1k-asm.c, * or1k-desc.c, * or1k-desc.h, * or1k-dis.c,
+	* or1k-ibld.c, * or1k-opc.c, * or1k-opc.h, * or1k-opinst.c: Regenerate.
+
+2014-06-10  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* i386-dis.c (fwait_prefix): New.
+	(ckprefix): Set fwait_prefix.
+	(print_insn): Properly print prefixes before fwait.
+
+2014-06-07  Alan Modra  <amodra@gmail.com>
+
+	* ppc-opc.c (UISIGNOPT): Define and use with cmpli.
+
+2014-06-05  Joel Brobecker  <brobecker@adacore.com>
+
+	* Makefile.am (CONFIG_STATUS_DEPENDENCIES): Add dependency on
+	bfd's development.sh.
+	* Makefile.in, configure: Regenerate.
+
+2014-06-03  Nick Clifton  <nickc@redhat.com>
+
+	* msp430-dis.c (msp430_doubleoperand): Use extension_word to
+	decide when extended addressing is being used.
+
+2014-06-02  Eric Botcazou  <ebotcazou@adacore.com>
+
+	* sparc-opc.c (cas): Disable for LEON.
+	(casl): Likewise.
+
+2014-05-20  Alan Modra  <amodra@gmail.com>
+
+	* m68k-dis.c: Don't include setjmp.h.
+
+2014-05-09  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* i386-dis.c (ADDR16_PREFIX): Removed.
+	(ADDR32_PREFIX): Likewise.
+	(DATA16_PREFIX): Likewise.
+	(DATA32_PREFIX): Likewise.
+	(prefix_name): Updated.
+	(print_insn): Simplify data and address size prefixes processing.
+
+2014-05-08  Stefan Kristiansson  <stefan.kristiansson@saunalahti.fi>
+
+	* or1k-desc.c: Regenerated.
+	* or1k-desc.h: Likewise.
+	* or1k-opc.c: Likewise.
+	* or1k-opc.h: Likewise.
+	* or1k-opinst.c: Likewise.
+
+2014-05-07  Andrew Bennett  <andrew.bennett@imgtec.com>
+
+	* mips-opc.c (mips_builtin_opcodes): Add MIPS32r5 eretnc instruction.
+	(I34): New define.
+	(I36): New define.
+	(I66): New define.
+	(I68): New define.
+	* mips-dis.c (mips_arch_choices): Add mips32r3, mips32r5, mips64r3 and
+	mips64r5.
+	(parse_mips_dis_option): Update MSA and virtualization support to
+	allow mips64r3 and mips64r5.
+
+2014-05-07  Andrew Bennett  <andrew.bennett@imgtec.com>
+
+	* mips-opc.c (G3): Remove I4.
+
+2014-05-05  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR binutils/16893
+	* i386-dis.c (twobyte_has_mandatory_prefix): New variable.
+	(end_codep): Likewise.
+	(mandatory_prefix): Likewise.
+	(active_seg_prefix): Likewise.
+	(ckprefix): Set active_seg_prefix to the active segment register
+	prefix.
+	(seg_prefix): Removed.
+	(get_valid_dis386): Use the last of PREFIX_REPNZ and PREFIX_REPZ
+	for prefix index.  Ignore the index if it is invalid and the
+	mandatory prefix isn't required.
+	(print_insn): Set mandatory_prefix if the PREFIX_XXX prefix is
+	mandatory.  Don't set PREFIX_REPZ/PREFIX_REPNZ/PREFIX_LOCK bits
+	in used_prefixes here.  Don't print unused prefixes.  Check
+	active_seg_prefix for the active segment register prefix.
+	Restore the DFLAG bit in sizeflag if the data size prefix is
+	unused.  Check the unused mandatory PREFIX_XXX prefixes
+	(append_seg): Only print the segment register which gets used.
+	(OP_E_memory): Check active_seg_prefix for the segment register
+	prefix.
+	(OP_OFF): Likewise.
+	(OP_OFF64): Likewise.
+	(OP_DSreg): Set active_seg_prefix to PREFIX_DS if it is unset.
+
+2014-05-02  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR binutils/16886
+	* config.in: Regenerated.
+	* configure: Likewise.
+	* configure.in: Check if sigsetjmp is available.
+	* h8500-dis.c (private): Replace jmp_buf with OPCODES_SIGJMP_BUF.
+	(fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
+	(print_insn_h8500): Replace setjmp with OPCODES_SIGSETJMP.
+	* i386-dis.c (dis_private): Replace jmp_buf with OPCODES_SIGJMP_BUF.
+	(fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
+	(print_insn): Replace setjmp with OPCODES_SIGSETJMP.
+	* ns32k-dis.c (private): Replace jmp_buf with OPCODES_SIGJMP_BUF.
+	(fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
+	(print_insn_ns32k): Replace setjmp with OPCODES_SIGSETJMP.
+	* sysdep.h (OPCODES_SIGJMP_BUF): New macro.
+	(OPCODES_SIGSETJMP): Likewise.
+	(OPCODES_SIGLONGJMP): Likewise.
+	* vax-dis.c (private): Replace jmp_buf with OPCODES_SIGJMP_BUF.
+	(fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
+	(print_insn_vax): Replace setjmp with OPCODES_SIGSETJMP.
+	* xtensa-dis.c (dis_private): Replace jmp_buf with
+	OPCODES_SIGJMP_BUF.
+	(fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
+	(print_insn_xtensa): Replace setjmp with OPCODES_SIGSETJMP.
+	* z8k-dis.c(instr_data_s): Replace jmp_buf with OPCODES_SIGJMP_BUF.
+	(fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
+	(print_insn_z8k): Replace setjmp with OPCODES_SIGSETJMP.
+
+2014-05-01  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR binutils/16891
+	* i386-dis.c (print_insn): Handle prefixes before fwait.
+
+2014-04-26  Alan Modra  <amodra@gmail.com>
+
+	* po/POTFILES.in: Regenerate.
+
+2014-04-23  Andrew Bennett  <andrew.bennett@imgtec.com>
+
+	* mips-dis.c (mips_arch_choices): Update mips32r2 and mips64r2
+	to allow the MIPS XPA ASE.
+	(parse_mips_dis_option): Process the -Mxpa option.
+	* mips-opc.c (XPA): New define.
+	(mips_builtin_opcodes): Add MIPS XPA instructions and move the
+	locations of the ctc0 and cfc0 instructions.
+
+2014-04-22  Christian Svensson  <blue@cmd.nu>
+
+	* Makefile.am: Remove openrisc and or32 support.  Add support for or1k.
+	* configure.in: Likewise.
+	* disassemble.c: Likewise.
+	* or1k-asm.c: New file.
+	* or1k-desc.c: New file.
+	* or1k-desc.h: New file.
+	* or1k-dis.c: New file.
+	* or1k-ibld.c: New file.
+	* or1k-opc.c: New file.
+	* or1k-opc.h: New file.
+	* or1k-opinst.c: New file.
+	* Makefile.in: Regenerate.
+	* configure: Regenerate.
+	* openrisc-asm.c: Delete.
+	* openrisc-desc.c: Delete.
+	* openrisc-desc.h: Delete.
+	* openrisc-dis.c: Delete.
+	* openrisc-ibld.c: Delete.
+	* openrisc-opc.c: Delete.
+	* openrisc-opc.h: Delete.
+	* or32-dis.c: Delete.
+	* or32-opc.c: Delete.
+
+2014-04-04  Ilya Tocar  <ilya.tocar@intel.com>
+
+	* i386-dis.c (rm_table): Add encls, enclu.
+	* i386-gen.c (cpu_flag_init): Add CPU_SE1_FLAGS,
+	(cpu_flags): Add CpuSE1.
+	* i386-opc.h (enum): Add CpuSE1.
+	(i386_cpu_flags): Add cpuse1.
+	* i386-opc.tbl: Add encls, enclu.
+	* i386-init.h: Regenerated.
+	* i386-tbl.h: Likewise.
+
+2014-04-02  Anthony Green  <green@moxielogic.com>
+
+	* moxie-opc.c (moxie_form1_opc_info): Add sign-extension
+	instructions, sex.b and sex.s.
+
+2014-03-26  Jiong Wang  <jiong.wang@arm.com>
+
+	* aarch64-dis.c (aarch64_ext_ldst_elemlist): Check H/S undefined
+	instructions.
+
+2014-03-20  Ilya Tocar  <ilya.tocar@intel.com>
+
+	* i386-opc.tbl: Change memory size for vgatherpf0qps, vgatherpf1qps,
+	vscatterpf0qps, vscatterpf1qps, vgatherqps, vpgatherqd, vpscatterqd,
+	vscatterqps.
+	* i386-tbl.h: Regenerate.
+
+2014-03-19  Jose E. Marchesi  <jose.marchesi@oracle.com>
+
+	* sparc-dis.c (v9_hpriv_reg_names): Names for %hstick_offset and
+	%hstick_enable added.
+
+2014-03-19  Nick Clifton  <nickc@redhat.com>
+
+	* rx-decode.opc (bwl): Allow for bogus instructions with a size
+	field of 3.
+	(sbwl, ubwl, SCALE): Likewise.
+	* rx-decode.c: Regenerate.
+
+2014-03-12  Alan Modra  <amodra@gmail.com>
+
+	* Makefile.in: Regenerate.
+
+2014-03-05  Alan Modra  <amodra@gmail.com>
+
+	Update copyright years.
+
+2014-03-04  Heiher  <r@hev.cc>
+
+	* mips-dis.c (mips_arch_choices): Usee ISA_MIPS64R2 for Loongson-3A.
+
+2014-03-04  Richard Sandiford  <rdsandiford@googlemail.com>
+
+	* mips-opc.c (mips_builtin_opcodes): Move the udi* instructions
+	so that they come after the Loongson extensions.
+
+2014-03-03  Alan Modra  <amodra@gmail.com>
+
+	* i386-gen.c (process_copyright): Emit copyright notice on one line.
+
+2014-02-28  Alan Modra  <amodra@gmail.com>
+
+	* msp430-decode.c: Regenerate.
+
+2014-02-27  Jiong Wang  <jiong.wang@arm.com>
+
+	* aarch64-tbl.h (aarch64_opcode_table): Replace IMM0 with
+	FPIMM0 for fcmeq, fcmgt, fcmge, fcmlt and fcmle.
+
+2014-02-27  Yufeng Zhang  <yufeng.zhang@arm.com>
+
+	* aarch64-opc.c (print_register_offset_address): Call
+	get_int_reg_name to prepare the register name.
+
+2014-02-25  Ilya Tocar  <ilya.tocar@intel.com>
+
+	* i386-opc.tbl: Remove wrong variant of vcvtps2ph
+	* i386-tbl.h: Regenerate.
+
+2014-02-20  Ilya Tocar  <ilya.tocar@intel.com>
+
+	* i386-gen.c (cpu_flag_init): Add CPU_PREFETCHWT1_FLAGS/
+	(cpu_flags): Add CpuPREFETCHWT1.
+	* i386-init.h: Regenerate.
+	* i386-opc.h (CpuPREFETCHWT1): New.
+	(i386_cpu_flags): Add cpuprefetchwt1.
+	* i386-opc.tbl: Cahnge CPU of prefetchwt1 from CpuAVX512PF to CpuPREFETCHWT1.
+	* i386-tbl.h: Regenerate.
+
+2014-02-20  Ilya Tocar  <ilya.tocar@intel.com>
+
+	* i386-opc.tbl: Change CPU of vptestnmq, vptestnmd from CpuAVX512CD,
+	to CpuAVX512F.
+	* i386-tbl.h: Regenerate.
+
+2014-02-19  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* i386-gen.c (output_cpu_flags): Don't output trailing space.
+	(output_opcode_modifier): Likewise.
+	(output_operand_type): Likewise.
+	* i386-init.h: Regenerated.
+	* i386-tbl.h: Likewise.
+
+2014-02-12  Ilya Tocar  <ilya.tocar@intel.com>
+
+	* i386-dis.c (MOD enum): Add MOD_0FC7_REG_3, MOD_0FC7_REG_4,
+	MOD_0FC7_REG_5.
+	(PREFIX enum): Add PREFIX_0FAE_REG_7.
+	(reg_table): Add MOD_0FC7_REG_3, MOD_0FC7_REG_4 MOD_0FC7_REG_5.
+	(prefix_table): Add clflusopt.
+	(mod_table): Add xrstors, xsavec, xsaves.
+	* i386-gen.c (cpu_flag_init): Add CPU_CLFLUSHOPT_FLAGS,
+	CPU_XSAVES_FLAGS, CPU_XSAVEC_FLAGS.
+	(cpu_flags): Add CpuClflushOpt, CpuXSAVES, CpuXSAVEC.
+	* i386-init.h: Regenerate.
+	* i386-opc.tbl: Add clflushopt, xrstors, xrstors64, xsaves,
+	xsaves64, xsavec, xsavec64.
+	* i386-tbl.h: Regenerate.
+
+2014-02-10  Alan Modra  <amodra@gmail.com>
+
+	* po/POTFILES.in: Regenerate.
+	* po/opcodes.pot: Regenerate.
+
+2014-01-30  Michael Zolotukhin  <michael.v.zolotukhin@gmail.com>
+	    Jan Beulich  <jbeulich@suse.com>
+
+	PR binutils/16490
+	* i386-dis.c (OP_E_memory): Fix shift computation for
+	vex_vsib_q_w_dq_mode.
+
+2014-01-09  Bradley Nelson  <bradnelson@google.com>
+	    Roland McGrath  <mcgrathr@google.com>
+
+	* i386-dis.c (print_insn): Do not touch all_prefixes[-1] when
+	last_rex_prefix is -1.
+
+2014-01-08  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* i386-gen.c (process_copyright): Update copyright year to 2014.
+
+2014-01-03  Maciej W. Rozycki  <macro@codesourcery.com>
+
+	* nds32-asm.c (parse_operand): Fix out-of-range integer constant.
+
+For older changes see ChangeLog-2013
+
+Copyright (C) 2014 Free Software Foundation, Inc.
+
+Copying and distribution of this file, with or without modification,
+are permitted in any medium without royalty provided the copyright
+notice and this notice are preserved.
+
+Local Variables:
+mode: change-log
+left-margin: 8
+fill-column: 74
+version-control: never
+End: