diff options
| author | mengqinggang <mengqinggang@loongson.cn> | 2023-04-23 09:55:46 +0800 |
|---|---|---|
| committer | liuzhensong <liuzhensong@loongson.cn> | 2023-04-23 10:04:07 +0800 |
| commit | fda507e61c40b25c339c2dbd7ace70498779f70a (patch) | |
| tree | 7d4b2c3b2bf5246d3be8b6f03a39fbf181a67555 /ld | |
| parent | 630e5a235eb7be043ab2fe9ed3d030d0ebd5aa92 (diff) | |
| download | binutils-gdb-fda507e61c40b25c339c2dbd7ace70498779f70a.tar.gz | |
LoongArch: Fix loongarch32 test fails
Regenerated macro_op_32.d and add skip loongarch64-*-*.
gas/ChangeLog:
* testsuite/gas/loongarch/macro_op_32.d: Regenerated.
ld/ChangeLog:
* testsuite/ld-loongarch-elf/macro_op_32.d: Regenerated.
Diffstat (limited to 'ld')
| -rw-r--r-- | ld/testsuite/ld-loongarch-elf/macro_op_32.d | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/ld/testsuite/ld-loongarch-elf/macro_op_32.d b/ld/testsuite/ld-loongarch-elf/macro_op_32.d index 145d852b2be..a78c4579ee9 100644 --- a/ld/testsuite/ld-loongarch-elf/macro_op_32.d +++ b/ld/testsuite/ld-loongarch-elf/macro_op_32.d @@ -7,19 +7,19 @@ Disassembly of section .text: -00000000.* <.text>: +00000000.* <.L1>: [ ]+0:[ ]+00150004[ ]+move[ ]+\$a0,[ ]+\$zero [ ]+4:[ ]+02bffc04[ ]+addi.w[ ]+\$a0,[ ]+\$zero,[ ]+-1\(0xfff\) [ ]+8:[ ]+00150004[ ]+move[ ]+\$a0,[ ]+\$zero [ ]+c:[ ]+02bffc04[ ]+addi.w[ ]+\$a0,[ ]+\$zero,[ ]+-1\(0xfff\) [ ]+10:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0 -[ ]+10:[ ]+R_LARCH_GOT_PC_HI20[ ]+.text +[ ]+10:[ ]+R_LARCH_GOT_PC_HI20[ ]+.L1 [ ]+14:[ ]+28800084[ ]+ld.w[ ]+\$a0,[ ]+\$a0,[ ]+0 -[ ]+14:[ ]+R_LARCH_GOT_PC_LO12[ ]+.text +[ ]+14:[ ]+R_LARCH_GOT_PC_LO12[ ]+.L1 [ ]+18:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0 -[ ]+18:[ ]+R_LARCH_GOT_PC_HI20[ ]+.text +[ ]+18:[ ]+R_LARCH_GOT_PC_HI20[ ]+.L1 [ ]+1c:[ ]+28800084[ ]+ld.w[ ]+\$a0,[ ]+\$a0,[ ]+0 -[ ]+1c:[ ]+R_LARCH_GOT_PC_LO12[ ]+.text +[ ]+1c:[ ]+R_LARCH_GOT_PC_LO12[ ]+.L1 [ ]+20:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0 [ ]+20:[ ]+R_LARCH_PCALA_HI20[ ]+.text [ ]+24:[ ]+02800084[ ]+addi.w[ ]+\$a0,[ ]+\$a0,[ ]+0 @@ -34,9 +34,9 @@ Disassembly of section .text: [ ]+34:[ ]+02800084[ ]+addi.w[ ]+\$a0,[ ]+\$a0,[ ]+0 [ ]+34:[ ]+R_LARCH_PCALA_LO12[ ]+.text [ ]+38:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0 -[ ]+38:[ ]+R_LARCH_GOT_PC_HI20[ ]+.text +[ ]+38:[ ]+R_LARCH_GOT_PC_HI20[ ]+.L1 [ ]+3c:[ ]+28800084[ ]+ld.w[ ]+\$a0,[ ]+\$a0,[ ]+0 -[ ]+3c:[ ]+R_LARCH_GOT_PC_LO12[ ]+.text +[ ]+3c:[ ]+R_LARCH_GOT_PC_LO12[ ]+.L1 [ ]+40:[ ]+14000004[ ]+lu12i.w[ ]+\$a0,[ ]+0 [ ]+40:[ ]+R_LARCH_TLS_LE_HI20[ ]+TLS1 [ ]+44:[ ]+03800084[ ]+ori[ ]+\$a0,[ ]+\$a0,[ ]+0x0 |