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| author | Tamar Christina <tamar.christina@arm.com> | 2020-04-01 10:40:07 +0100 |
|---|---|---|
| committer | Tamar Christina <tamar.christina@arm.com> | 2020-04-01 10:52:32 +0100 |
| commit | 15ccbdd717530f81f545a716f0df1de62aee1157 (patch) | |
| tree | b54513be2b1a192572032eb32a8c3a52aecaef51 /ld/testsuite | |
| parent | 40bd13ced9c03c74af9d55a98d6e06ddcf11429c (diff) | |
| download | binutils-gdb-15ccbdd717530f81f545a716f0df1de62aee1157.tar.gz | |
Arm: Fix thumb2 PLT branch offsets.
When I previously changed these offsets I had incorrectly used an offset of -2
for this Thumb2 PLT. Unfortunately because we had no tests for this PLT I had
missed that the result was incorrect.
This patch fixes the offset to PC .-4 so that it correctly addresses the
previous instruction and adds a test for this PLT stub.
bfd/ChangeLog:
* elf32-arm.c (elf32_thumb2_plt_entry): Fix PC-rel offset.
ld/ChangeLog:
* testsuite/ld-arm/arm-elf.exp (thumb-plt): New.
* testsuite/ld-arm/thumb-plt.d: New test.
* testsuite/ld-arm/thumb-plt.s: New test.
Diffstat (limited to 'ld/testsuite')
| -rw-r--r-- | ld/testsuite/ld-arm/arm-elf.exp | 2 | ||||
| -rw-r--r-- | ld/testsuite/ld-arm/thumb-plt.d | 34 | ||||
| -rw-r--r-- | ld/testsuite/ld-arm/thumb-plt.s | 18 |
3 files changed, 54 insertions, 0 deletions
diff --git a/ld/testsuite/ld-arm/arm-elf.exp b/ld/testsuite/ld-arm/arm-elf.exp index 18177d19224..99a313999e7 100644 --- a/ld/testsuite/ld-arm/arm-elf.exp +++ b/ld/testsuite/ld-arm/arm-elf.exp @@ -1268,3 +1268,5 @@ run_dump_test "non-contiguous-arm3" run_dump_test "non-contiguous-arm4" run_dump_test "non-contiguous-arm5" run_dump_test "non-contiguous-arm6" + +run_dump_test "thumb-plt" diff --git a/ld/testsuite/ld-arm/thumb-plt.d b/ld/testsuite/ld-arm/thumb-plt.d new file mode 100644 index 00000000000..441325b21db --- /dev/null +++ b/ld/testsuite/ld-arm/thumb-plt.d @@ -0,0 +1,34 @@ +#source: thumb-plt.s +#name: Thumb only PLT and GOT +#ld: -shared -e0 +#objdump: -dr +#skip: *-*-pe *-*-wince *-*-vxworks armeb-*-* *-*-gnueabihf + +.*: +file format .*arm.* + + +Disassembly of section \.plt: + +00000110 <\.plt>: + 110: b500 push {lr} + 112: f8df e008 ldr.w lr, \[pc, #8\] ; 11c <\.plt\+0xc> + 116: 44fe add lr, pc + 118: f85e ff08 ldr.w pc, \[lr, #8\]! + 11c: 0001009c \.word 0x0001009c + +00000120 <foo@plt>: + 120: f240 0c98 movw ip, #152 ; 0x98 + 124: f2c0 0c01 movt ip, #1 + 128: 44fc add ip, pc + 12a: f8dc f000 ldr.w pc, \[ip\] + 12e: e7fc b.n 12a <foo@plt\+0xa> + +Disassembly of section .text: + +00000130 <bar>: + 130: b580 push {r7, lr} + 132: af00 add r7, sp, #0 + 134: f7ff fff4 bl 120 <foo@plt> + 138: 4603 mov r3, r0 + 13a: 4618 mov r0, r3 + 13c: bd80 pop {r7, pc} diff --git a/ld/testsuite/ld-arm/thumb-plt.s b/ld/testsuite/ld-arm/thumb-plt.s new file mode 100644 index 00000000000..e3fd80f0f1d --- /dev/null +++ b/ld/testsuite/ld-arm/thumb-plt.s @@ -0,0 +1,18 @@ + .cpu cortex-m3 + .text + .align 1 + .global bar + .arch armv7-m + .syntax unified + .thumb + .thumb_func + .fpu softvfp + .type bar, %function +bar: + push {r7, lr} + add r7, sp, #0 + bl foo(PLT) + mov r3, r0 + mov r0, r3 + pop {r7, pc} + .size bar, .-bar |