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| author | Alan Modra <amodra@gmail.com> | 2015-07-28 11:03:57 +0930 |
|---|---|---|
| committer | Alan Modra <amodra@gmail.com> | 2015-07-28 18:42:43 +0930 |
| commit | e5654c0f8492e65b3e3ac5e1a2276856049eb1b1 (patch) | |
| tree | 365260c36ca9ad4abda3550eec856dcce63beba8 /ld/testsuite/ld-powerpc | |
| parent | d6f1bafa2c05241b89c0303a9f6a2af89f51c39c (diff) | |
| download | binutils-gdb-e5654c0f8492e65b3e3ac5e1a2276856049eb1b1.tar.gz | |
Fallout from "Reorder more powerpc64 sections for -z relro"
Commit 23283c1b changed the layout of some bss style sections on
powerpc64, but neglected to add a page gap before the third PT_LOAD
segment created by this reording. Without a page gap we get two
PT_LOAD headers that overlap by one page in memory. That shouldn't be
allowed because the dynamic loader will load garbage from the first
page of the last segment over the last page of the previous segment.
bfd/
* elf.c (_bfd_elf_map_sections_to_segments): Do not make a new
segment for loaded sections after nonloaded sections if the
sections are on the same page.
ld/testsuite/
* ld-powerpc/elfv2so.d: Update
Diffstat (limited to 'ld/testsuite/ld-powerpc')
| -rw-r--r-- | ld/testsuite/ld-powerpc/elfv2so.d | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/ld/testsuite/ld-powerpc/elfv2so.d b/ld/testsuite/ld-powerpc/elfv2so.d index 906b375adff..d6f0b7da5b6 100644 --- a/ld/testsuite/ld-powerpc/elfv2so.d +++ b/ld/testsuite/ld-powerpc/elfv2so.d @@ -7,33 +7,33 @@ Disassembly of section \.text: -0+320 <.*\.plt_call\.f4>: +0+300 <.*\.plt_call\.f4>: .*: (f8 41 00 18|18 00 41 f8) std r2,24\(r1\) .*: (e9 82 80 38|38 80 82 e9) ld r12,-32712\(r2\) .*: (7d 89 03 a6|a6 03 89 7d) mtctr r12 .*: (4e 80 04 20|20 04 80 4e) bctr -0+330 <.*\.plt_call\.f3>: +0+310 <.*\.plt_call\.f3>: .*: (f8 41 00 18|18 00 41 f8) std r2,24\(r1\) .*: (e9 82 80 28|28 80 82 e9) ld r12,-32728\(r2\) .*: (7d 89 03 a6|a6 03 89 7d) mtctr r12 .*: (4e 80 04 20|20 04 80 4e) bctr -0+340 <.*\.plt_call\.f2>: +0+320 <.*\.plt_call\.f2>: .*: (f8 41 00 18|18 00 41 f8) std r2,24\(r1\) .*: (e9 82 80 30|30 80 82 e9) ld r12,-32720\(r2\) .*: (7d 89 03 a6|a6 03 89 7d) mtctr r12 .*: (4e 80 04 20|20 04 80 4e) bctr -0+350 <.*\.plt_call\.f1>: +0+330 <.*\.plt_call\.f1>: .*: (f8 41 00 18|18 00 41 f8) std r2,24\(r1\) .*: (e9 82 80 40|40 80 82 e9) ld r12,-32704\(r2\) .*: (7d 89 03 a6|a6 03 89 7d) mtctr r12 .*: (4e 80 04 20|20 04 80 4e) bctr -0+360 <f1>: +0+340 <f1>: .*: (3c 4c 00 02|02 00 4c 3c) addis r2,r12,2 -.*: (38 42 82 a0|a0 82 42 38) addi r2,r2,-32096 +.*: (38 42 82 c0|c0 82 42 38) addi r2,r2,-32064 .*: (7c 08 02 a6|a6 02 08 7c) mflr r0 .*: (f8 21 ff e1|e1 ff 21 f8) stdu r1,-32\(r1\) .*: (f8 01 00 30|30 00 01 f8) std r0,48\(r1\) @@ -50,10 +50,10 @@ Disassembly of section \.text: .*: (38 21 00 20|20 00 21 38) addi r1,r1,32 .*: (7c 08 03 a6|a6 03 08 7c) mtlr r0 .*: (4e 80 00 20|20 00 80 4e) blr -.*: (00 00 00 00|60 02 01 00) .* -.*: (00 01 02 60|00 00 00 00) .* +.*: (00 00 00 00|80 02 01 00) .* +.*: (00 01 02 80|00 00 00 00) .* -0+3b0 <__glink_PLTresolve>: +0+390 <__glink_PLTresolve>: .*: (7c 08 02 a6|a6 02 08 7c) mflr r0 .*: (42 9f 00 05|05 00 9f 42) bcl .* .*: (7d 68 02 a6|a6 02 68 7d) mflr r11 |