PowerPC PLT stub tidy

This is in preparation for the next patch adding Spectre variant 2
mitigation for PowerPC and PowerPC64.  Besides tidying code involved
in stub output (to reduce the number of places where bctr is output),
the patch adds some user visible features:

1) PowerPC64 ELFv2 global entry stubs now are aligned under the
   control of --plt-align, with a default alignment of 32 bytes.
2) PowerPC64 __glink_PLTresolve is no longer padded out with nops.
3) PowerPC32 PLT stubs are aligned under the control of --plt-align,
   with the default alignment being 16 bytes as before.
4) The PowerPC32 branch/nop table emitted before __glink_PLTresolve
   is now smaller in many cases.  It was sized incorrectly when the
   __tls_get_addr_opt stub was used, and unnecessarily included space
   for local ifuncs.

bfd/
	* elf32-ppc.c (GLINK_ENTRY_SIZE): Add parameters, handle
	__tls_get_addr_opt, and alignment sizing.
	(TLS_GET_ADDR_GLINK_SIZE): Delete.
	(is_nonpic_glink_stub): Don't use GLINK_ENTRY_SIZE.
	(ppc_elf_get_synthetic_symtab): Recognize stubs spaced at 4, 6,
	or 8 insns.
	(ppc_elf_link_hash_table_create): Init new ppc_elf_params field.
	(allocate_dynrelocs): Use new GLINK_ENTRY_SIZE.
	(ppc_elf_size_dynamic_sections): Likewise.  Size branch table
	by PLT reloc count.
	(write_glink_stub): Handle __tls_get_addr_opt stub.
	Pad out to size given by GLINK_ENTRY_SIZE.
	(ppc_elf_relocate_section): Adjust write_glink_stub call.
	(ppc_elf_finish_dynamic_symbol): Likewise.
	(ppc_elf_finish_dynamic_sections): Write PLTresolve without using
	insn array since so many need rewriting.
	* elf32-ppc.h (struct ppc_elf_params): Add plt_stub_align.
	* elf64-ppc.c (GLINK_PLTRESOLVE_SIZE): Rename from
	GLINK_CALL_STUB_SIZE.  Add htab param and evaluate to size without
	nops.  Adjust all uses.
	(ppc64_elf_get_synthetic_symtab): Don't use GLINK_CALL_STUB_SIZE
	in glink_vma calculation.
	(struct ppc_link_hash_table): Add global_entry section pointer.
	(create_linkage_sections): Create separate section for global
	entry stubs.
	(PPC_LO, PPC_HI, PPC_HA): Move earlier.
	(size_global_entry_stubs): Handle sizing for aligned stubs.
	(ppc64_elf_size_dynamic_sections): Handle global_entry alloc,
	and don't stash end of glink branch table in rawsize.
	(ppc_build_one_stub): Rewrite stub size calculations.
	(build_global_entry_stubs): Use new section.
	(ppc64_elf_build_stubs): Don't pad __glink_PLTresolve with nops.
	Build lazy link stubs out to end of section.  Build global entry
	stubs in new section.
gold/
	* options.h (plt_align): Support for PowerPC32 too.
	* powerpc.cc (Stub_table::stub_align): Heed --plt-align for 32-bit.
	(Stub_table::plt_call_size, branch_stub_size): Tidy.
	(Stub_table::plt_call_align): Implement using stub_align.
	(Output_data_glink::global_entry_align): New function.
	(Output_data_glink::global_entry_off): New function.
	(Output_data_glink::global_entry_address): Use global_entry_off.
	(Output_data_glink::pltresolve_size): New function, replacing
	pltresolve_size_ constant.  Update all uses.
	(Output_data_glink::add_global_entry): Align offset.
	(Output_data_glink::set_final_data_size): Use global_entry_align.
	(Stub_table::do_write): Don't pad __glink_PLTrelsolve with nops.
	Tidy stub output.  Use global_entry_off.
ld/
	* emultempl/ppc32elf.em (params): Init new field.
	(enum ppc32_opt): New enum to define OPTION_* values.  Add
	OPTION_PLT_ALIGN and OPTION_NO_PLT_ALIGN.
	(PARSE_AND_LIST_LONGOPTS): Handle new options.
	(PARSE_AND_LIST_ARGS_CASES): Likewise.
	(PARSE_AND_LIST_OPTIONS): Likewise.  Break up help output.
	* emultempl/ppc64elf.em (ppc_add_stub_section): Init alignment
	correctly for negative --plt-stub-align.
	* testsuite/ld-powerpc/elfv2exe.d,
	* testsuite/ld-powerpc/elfv2so.d,
	* testsuite/ld-powerpc/relbrlt.d,
	* testsuite/ld-powerpc/relbrlt.s,
	* testsuite/ld-powerpc/tlsexe.d,
	* testsuite/ld-powerpc/tlsexe.r,
	* testsuite/ld-powerpc/tlsexe32.d,
	* testsuite/ld-powerpc/tlsexe32.g,
	* testsuite/ld-powerpc/tlsexe32.r,
	* testsuite/ld-powerpc/tlsexetoc.d,
	* testsuite/ld-powerpc/tlsexetoc.r,
	* testsuite/ld-powerpc/tlsopt5_32.d,
	* testsuite/ld-powerpc/tlsso.d,
	* testsuite/ld-powerpc/tlstocso.d: Update for changed stub order.

14 files changed, 50 insertions, 74 deletions

diff --git a/ld/testsuite/ld-powerpc/elfv2exe.d b/ld/testsuite/ld-powerpc/elfv2exe.d
index 4c3c632247f..77bf6e25688 100644
--- a/ld/testsuite/ld-powerpc/elfv2exe.d
+++ b/ld/testsuite/ld-powerpc/elfv2exe.d
@@ -7,13 +7,13 @@
 
 Disassembly of section \.text:
 
-0+100000c0 <.*\.plt_branch\.f2>:
+0+100000c0 <.*\.plt_branch\.f4>:
 .*:	(3d 82 ff ff|ff ff 82 3d) 	addis   r12,r2,-1
 .*:	(e9 8c 7f 28|28 7f 8c e9) 	ld      r12,32552\(r12\)
 .*:	(7d 89 03 a6|a6 03 89 7d) 	mtctr   r12
 .*:	(4e 80 04 20|20 04 80 4e) 	bctr
 
-0+100000d0 <.*\.plt_branch\.f4>:
+0+100000d0 <.*\.plt_branch\.f2>:
 .*:	(3d 82 ff ff|ff ff 82 3d) 	addis   r12,r2,-1
 .*:	(e9 8c 7f 30|30 7f 8c e9) 	ld      r12,32560\(r12\)
 .*:	(7d 89 03 a6|a6 03 89 7d) 	mtctr   r12
@@ -27,12 +27,12 @@ Disassembly of section \.text:
 .*:	(f8 01 00 30|30 00 01 f8) 	std     r0,48\(r1\)
 .*:	(4b ff ff f5|f5 ff ff 4b) 	bl      .* <(f1|_start)\+0x8>
 .*:	(e8 62 80 08|08 80 62 e8) 	ld      r3,-32760\(r2\)
-.*:	(4b ff ff c5|c5 ff ff 4b) 	bl      .*\.plt_branch\.f2>
+.*:	(4b ff ff d5|d5 ff ff 4b) 	bl      .*\.plt_branch\.f2>
 .*:	(60 00 00 00|00 00 00 60) 	nop
 .*:	(e8 62 80 10|10 80 62 e8) 	ld      r3,-32752\(r2\)
 .*:	(48 00 87 81|81 87 00 48) 	bl      10008888 <f3>
 .*:	(60 00 00 00|00 00 00 60) 	nop
-.*:	(4b ff ff c1|c1 ff ff 4b) 	bl      .*\.plt_branch\.f4>
+.*:	(4b ff ff b1|b1 ff ff 4b) 	bl      .*\.plt_branch\.f4>
 .*:	(60 00 00 00|00 00 00 60) 	nop
 .*:	(e8 01 00 30|30 00 01 e8) 	ld      r0,48\(r1\)
 .*:	(38 21 00 20|20 00 21 38) 	addi    r1,r1,32
diff --git a/ld/testsuite/ld-powerpc/elfv2so.d b/ld/testsuite/ld-powerpc/elfv2so.d
index a577b2a7ea8..e7cd45c9c21 100644
--- a/ld/testsuite/ld-powerpc/elfv2so.d
+++ b/ld/testsuite/ld-powerpc/elfv2so.d
@@ -14,23 +14,23 @@ Disassembly of section \.text:
 .*:	(4e 80 04 20|20 04 80 4e) 	bctr
 	\.\.\.
 
-.* <.*\.plt_call\.f3>:
+.* <.*\.plt_call\.f1>:
 .*:	(f8 41 00 18|18 00 41 f8) 	std     r2,24\(r1\)
-.*:	(e9 82 80 28|28 80 82 e9) 	ld      r12,-32728\(r2\)
+.*:	(e9 82 80 40|40 80 82 e9) 	ld      r12,-32704\(r2\)
 .*:	(7d 89 03 a6|a6 03 89 7d) 	mtctr   r12
 .*:	(4e 80 04 20|20 04 80 4e) 	bctr
 	\.\.\.
 
-.* <.*\.plt_call\.f2>:
+.* <.*\.plt_call\.f3>:
 .*:	(f8 41 00 18|18 00 41 f8) 	std     r2,24\(r1\)
-.*:	(e9 82 80 30|30 80 82 e9) 	ld      r12,-32720\(r2\)
+.*:	(e9 82 80 28|28 80 82 e9) 	ld      r12,-32728\(r2\)
 .*:	(7d 89 03 a6|a6 03 89 7d) 	mtctr   r12
 .*:	(4e 80 04 20|20 04 80 4e) 	bctr
 	\.\.\.
 
-.* <.*\.plt_call\.f1>:
+.* <.*\.plt_call\.f2>:
 .*:	(f8 41 00 18|18 00 41 f8) 	std     r2,24\(r1\)
-.*:	(e9 82 80 40|40 80 82 e9) 	ld      r12,-32704\(r2\)
+.*:	(e9 82 80 30|30 80 82 e9) 	ld      r12,-32720\(r2\)
 .*:	(7d 89 03 a6|a6 03 89 7d) 	mtctr   r12
 .*:	(4e 80 04 20|20 04 80 4e) 	bctr
 	\.\.\.
@@ -41,12 +41,12 @@ Disassembly of section \.text:
 .*:	(7c 08 02 a6|a6 02 08 7c) 	mflr    r0
 .*:	(f8 21 ff e1|e1 ff 21 f8) 	stdu    r1,-32\(r1\)
 .*:	(f8 01 00 30|30 00 01 f8) 	std     r0,48\(r1\)
-.*:	(4b ff ff cd|cd ff ff 4b) 	bl      .*\.plt_call\.f1>
+.*:	(4b ff ff 8d|8d ff ff 4b) 	bl      .*\.plt_call\.f1>
 .*:	(e8 62 80 08|08 80 62 e8) 	ld      r3,-32760\(r2\)
-.*:	(4b ff ff a5|a5 ff ff 4b) 	bl      .*\.plt_call\.f2>
+.*:	(4b ff ff c5|c5 ff ff 4b) 	bl      .*\.plt_call\.f2>
 .*:	(e8 41 00 18|18 00 41 e8) 	ld      r2,24\(r1\)
 .*:	(e8 62 80 10|10 80 62 e8) 	ld      r3,-32752\(r2\)
-.*:	(4b ff ff 79|79 ff ff 4b) 	bl      .*\.plt_call\.f3>
+.*:	(4b ff ff 99|99 ff ff 4b) 	bl      .*\.plt_call\.f3>
 .*:	(e8 41 00 18|18 00 41 e8) 	ld      r2,24\(r1\)
 .*:	(4b ff ff 51|51 ff ff 4b) 	bl      .*\.plt_call\.f4>
 .*:	(e8 41 00 18|18 00 41 e8) 	ld      r2,24\(r1\)
diff --git a/ld/testsuite/ld-powerpc/relbrlt.d b/ld/testsuite/ld-powerpc/relbrlt.d
index a00b1ffd0c5..6f3db7d0146 100644
--- a/ld/testsuite/ld-powerpc/relbrlt.d
+++ b/ld/testsuite/ld-powerpc/relbrlt.d
@@ -8,32 +8,32 @@
 Disassembly of section \.text:
 
 0*100000c0 <_start>:
-[0-9a-f	 ]*:	(49 bf 00 2d|2d 00 bf 49) 	bl      .*
+[0-9a-f	 ]*:	(49 bf 00 21|21 00 bf 49) 	bl      .*
 [0-9a-f	 ]*: R_PPC64_REL24	\.text\+0x37e003c
 [0-9a-f	 ]*:	(60 00 00 00|00 00 00 60) 	nop
-[0-9a-f	 ]*:	(49 bf 00 19|19 00 bf 49) 	bl      .*
-[0-9a-f	 ]*: R_PPC64_REL24	\.text\+0x3bf0020
+[0-9a-f	 ]*:	(49 bf 00 1d|1d 00 bf 49) 	bl      .*
+[0-9a-f	 ]*: R_PPC64_REL24	\.text\+0x3bf002c
 [0-9a-f	 ]*:	(60 00 00 00|00 00 00 60) 	nop
 [0-9a-f	 ]*:	(49 bf 00 21|21 00 bf 49) 	bl      .*
-[0-9a-f	 ]*: R_PPC64_REL24	\.text\+0x57e0024
+[0-9a-f	 ]*: R_PPC64_REL24	\.text\+0x57e0030
 [0-9a-f	 ]*:	(60 00 00 00|00 00 00 60) 	nop
 [0-9a-f	 ]*:	00 00 00 00 	\.long 0x0
 [0-9a-f	 ]*:	(4b ff ff e4|e4 ff ff 4b) 	b       .* <_start>
 	\.\.\.
 
+[0-9a-f	 ]*<.*long_branch.*>:
+[0-9a-f	 ]*:	(49 bf 00 1c|1c 00 bf 49) 	b       .* <far>
+[0-9a-f	 ]*: R_PPC64_REL24	\*ABS\*\+0x137e00fc
+
 [0-9a-f	 ]*<.*plt_branch.*>:
-[0-9a-f	 ]*:	(e9 82 80 e8|e8 80 82 e9) 	ld      r12,-32536\(r2\)
-[0-9a-f	 ]*: R_PPC64_TOC16_DS	\*ABS\*\+0x157f00e8
+[0-9a-f	 ]*:	(e9 82 80 f8|f8 80 82 e9) 	ld      r12,-32520\(r2\)
+[0-9a-f	 ]*: R_PPC64_TOC16_DS	\*ABS\*\+0x157f00f8
 [0-9a-f	 ]*:	(7d 89 03 a6|a6 03 89 7d) 	mtctr   r12
 [0-9a-f	 ]*:	(4e 80 04 20|20 04 80 4e) 	bctr
 
-[0-9a-f	 ]*<.*long_branch.*>:
-[0-9a-f	 ]*:	(49 bf 00 10|10 00 bf 49) 	b       .* <far>
-[0-9a-f	 ]*: R_PPC64_REL24	\*ABS\*\+0x137e00fc
-
 [0-9a-f	 ]*<.*plt_branch.*>:
-[0-9a-f	 ]*:	(e9 82 80 f0|f0 80 82 e9) 	ld      r12,-32528\(r2\)
-[0-9a-f	 ]*: R_PPC64_TOC16_DS	\*ABS\*\+0x157f00f0
+[0-9a-f	 ]*:	(e9 82 81 00|00 81 82 e9) 	ld      r12,-32512\(r2\)
+[0-9a-f	 ]*: R_PPC64_TOC16_DS	\*ABS\*\+0x157f0100
 [0-9a-f	 ]*:	(7d 89 03 a6|a6 03 89 7d) 	mtctr   r12
 [0-9a-f	 ]*:	(4e 80 04 20|20 04 80 4e) 	bctr
 	\.\.\.
@@ -42,19 +42,19 @@ Disassembly of section \.text:
 [0-9a-f	 ]*:	(4e 80 00 20|20 00 80 4e) 	blr
 	\.\.\.
 
-0*13bf00e0 <far2far>:
+0*13bf00ec <far2far>:
 [0-9a-f	 ]*:	(4e 80 00 20|20 00 80 4e) 	blr
 	\.\.\.
 
-0*157e00e4 <huge>:
+0*157e00f0 <huge>:
 [0-9a-f	 ]*:	(4e 80 00 20|20 00 80 4e) 	blr
 
 Disassembly of section \.branch_lt:
 
-0*157f00e8 .*:
-[0-9a-f	 ]*:	(00 00 00 00|e0 00 bf 13) .*
-[0-9a-f	 ]*: R_PPC64_RELATIVE	\*ABS\*\+0x13bf00e0
-[0-9a-f	 ]*:	(13 bf 00 e0|00 00 00 00) .*
-[0-9a-f	 ]*:	(00 00 00 00|e4 00 7e 15) .*
-[0-9a-f	 ]*: R_PPC64_RELATIVE	\*ABS\*\+0x157e00e4
-[0-9a-f	 ]*:	(15 7e 00 e4|00 00 00 00) .*
+0*157f00f8 .*:
+[0-9a-f	 ]*:	(00 00 00 00|ec 00 bf 13) .*
+[0-9a-f	 ]*: R_PPC64_RELATIVE	\*ABS\*\+0x13bf00ec
+[0-9a-f	 ]*:	(13 bf 00 ec|00 00 00 00) .*
+[0-9a-f	 ]*:	(00 00 00 00|f0 00 7e 15) .*
+[0-9a-f	 ]*: R_PPC64_RELATIVE	\*ABS\*\+0x157e00f0
+[0-9a-f	 ]*:	(15 7e 00 f0|00 00 00 00) .*
diff --git a/ld/testsuite/ld-powerpc/relbrlt.s b/ld/testsuite/ld-powerpc/relbrlt.s
index cee0cddfda0..fade6a281ea 100644
--- a/ld/testsuite/ld-powerpc/relbrlt.s
+++ b/ld/testsuite/ld-powerpc/relbrlt.s
@@ -20,7 +20,7 @@ far:
  blr
 
  .section .text.pad2,"ax"
- .space 0x40ffe0
+ .space 0x40ffec
 
  .section .text.far2far,"ax"
 far2far:
diff --git a/ld/testsuite/ld-powerpc/tlsexe.d b/ld/testsuite/ld-powerpc/tlsexe.d
index 542b435847e..396f45559f0 100644
--- a/ld/testsuite/ld-powerpc/tlsexe.d
+++ b/ld/testsuite/ld-powerpc/tlsexe.d
@@ -81,9 +81,6 @@ Disassembly of section \.text:
 .*	(7d 89 03 a6|a6 03 89 7d) 	mtctr   r12
 .*	(e9 6b 00 10|10 00 6b e9) 	ld      r11,16\(r11\)
 .*	(4e 80 04 20|20 04 80 4e) 	bctr
-.*	(60 00 00 00|00 00 00 60) 	nop
-.*	(60 00 00 00|00 00 00 60) 	nop
-.*	(60 00 00 00|00 00 00 60) 	nop
 .* <__tls_get_addr_opt@plt>:
 .*	(38 00 00 00|00 00 00 38) 	li      r0,0
-.*	(4b ff ff c4|c4 ff ff 4b) 	b       .*
+.*	(4b ff ff d0|d0 ff ff 4b) 	b       .*
diff --git a/ld/testsuite/ld-powerpc/tlsexe.r b/ld/testsuite/ld-powerpc/tlsexe.r
index f28ae9c474d..8c8b3318f6a 100644
--- a/ld/testsuite/ld-powerpc/tlsexe.r
+++ b/ld/testsuite/ld-powerpc/tlsexe.r
@@ -16,7 +16,7 @@ Section Headers:
  +\[[ 0-9]+\] \.dynstr +.*
  +\[[ 0-9]+\] \.rela\.dyn +.*
  +\[[ 0-9]+\] \.rela\.plt +.*
- +\[[ 0-9]+\] \.text +PROGBITS .* 0+128 0+ +AX +0 +0 +32
+ +\[[ 0-9]+\] \.text +PROGBITS .* 0+11c 0+ +AX +0 +0 +32
  +\[[ 0-9]+\] \.tdata +PROGBITS .* 0+38 0+ WAT +0 +0 +8
  +\[[ 0-9]+\] \.tbss +NOBITS .* 0+38 0+ WAT +0 +0 +8
  +\[[ 0-9]+\] \.dynamic +DYNAMIC .* 0+160 10 +WA +4 +0 +8
diff --git a/ld/testsuite/ld-powerpc/tlsexe32.d b/ld/testsuite/ld-powerpc/tlsexe32.d
index e7bc0d69651..79029468395 100644
--- a/ld/testsuite/ld-powerpc/tlsexe32.d
+++ b/ld/testsuite/ld-powerpc/tlsexe32.d
@@ -12,7 +12,7 @@ Disassembly of section \.text:
 .*:	(42 9f 00 05|05 00 9f 42) 	bcl     20,4\*cr7\+so,.* <_start\+0x4>
 .*:	(7f c8 02 a6|a6 02 c8 7f) 	mflr    r30
 .*:	(3f de 00 02|02 00 de 3f) 	addis   r30,r30,2
-.*:	(3b de 81 18|18 81 de 3b) 	addi    r30,r30,-32488
+.*:	(3b de 81 08|08 81 de 3b) 	addi    r30,r30,-32504
 .*:	(80 7f ff f4|f4 ff 7f 80) 	lwz     r3,-12\(r31\)
 .*:	(7c 63 12 14|14 12 63 7c) 	add     r3,r3,r2
 .*:	(38 7f ff f8|f8 ff 7f 38) 	addi    r3,r31,-8
@@ -52,24 +52,18 @@ Disassembly of section \.text:
 .*:	(7c 03 03 78|78 03 03 7c) 	mr      r3,r0
 .*:	(60 00 00 00|00 00 00 60) 	nop
 .*:	(3d 60 01 81|81 01 60 3d) 	lis     r11,385
-.*:	(81 6b 04 14|14 04 6b 81) 	lwz     r11,1044\(r11\)
+.*:	(81 6b 04 04|04 04 6b 81) 	lwz     r11,1028\(r11\)
 .*:	(7d 69 03 a6|a6 03 69 7d) 	mtctr   r11
 .*:	(4e 80 04 20|20 04 80 4e) 	bctr
 
-.* <__glink>:
-.*:	(60 00 00 00|00 00 00 60) 	nop
-.*:	(60 00 00 00|00 00 00 60) 	nop
-.*:	(60 00 00 00|00 00 00 60) 	nop
-.*:	(60 00 00 00|00 00 00 60) 	nop
-
-.* <__glink_PLTresolve>:
+.* <__glink(_PLTresolve)?>:
 .*:	(3d 80 01 81|81 01 80 3d) 	lis     r12,385
 .*:	(3d 6b fe 80|80 fe 6b 3d) 	addis   r11,r11,-384
-.*:	(80 0c 04 0c|0c 04 0c 80) 	lwz     r0,1036\(r12\)
+.*:	(80 0c 03 fc|fc 03 0c 80) 	lwz     r0,1020\(r12\)
 .*:	(39 6b fd 20|20 fd 6b 39) 	addi    r11,r11,-736
 .*:	(7c 09 03 a6|a6 03 09 7c) 	mtctr   r0
 .*:	(7c 0b 5a 14|14 5a 0b 7c) 	add     r0,r11,r11
-.*:	(81 8c 04 10|10 04 8c 81) 	lwz     r12,1040\(r12\)
+.*:	(81 8c 04 00|00 04 8c 81) 	lwz     r12,1024\(r12\)
 .*:	(7d 60 5a 14|14 5a 60 7d) 	add     r11,r0,r11
 .*:	(4e 80 04 20|20 04 80 4e) 	bctr
 .*:	(60 00 00 00|00 00 00 60) 	nop
diff --git a/ld/testsuite/ld-powerpc/tlsexe32.g b/ld/testsuite/ld-powerpc/tlsexe32.g
index e402f6b867d..b6afc9c44cc 100644
--- a/ld/testsuite/ld-powerpc/tlsexe32.g
+++ b/ld/testsuite/ld-powerpc/tlsexe32.g
@@ -7,5 +7,5 @@
 .*
 
 Contents of section \.got:
-.* 00000000 00000000 00000000 (0181034c|4c038101)  .*
+.* 00000000 00000000 00000000 (0181033c|3c038101)  .*
 .* 00000000 00000000  .*
diff --git a/ld/testsuite/ld-powerpc/tlsexe32.r b/ld/testsuite/ld-powerpc/tlsexe32.r
index 6061835f29c..a7387e42800 100644
--- a/ld/testsuite/ld-powerpc/tlsexe32.r
+++ b/ld/testsuite/ld-powerpc/tlsexe32.r
@@ -16,7 +16,7 @@ Section Headers:
  +\[[ 0-9]+\] \.dynstr +.*
  +\[[ 0-9]+\] \.rela\.dyn +.*
  +\[[ 0-9]+\] \.rela\.plt +.*
- +\[[ 0-9]+\] \.text +PROGBITS +[0-9a-f]+ [0-9a-f]+ 000100 00 +AX +0 +0 +16
+ +\[[ 0-9]+\] \.text +PROGBITS +[0-9a-f]+ [0-9a-f]+ 0000f0 00 +AX +0 +0 +16
  +\[[ 0-9]+\] \.tdata +PROGBITS +[0-9a-f]+ [0-9a-f]+ 00001c 00 WAT +0 +0 +4
  +\[[ 0-9]+\] \.tbss +NOBITS +[0-9a-f]+ [0-9a-f]+ 00001c 00 WAT +0 +0 +4
  +\[[ 0-9]+\] \.dynamic +DYNAMIC +[0-9a-f]+ [0-9a-f]+ [0-9a-f]+ 08 +WA +4 +0 +4
diff --git a/ld/testsuite/ld-powerpc/tlsexetoc.d b/ld/testsuite/ld-powerpc/tlsexetoc.d
index d216a2a3f94..4bab567054b 100644
--- a/ld/testsuite/ld-powerpc/tlsexetoc.d
+++ b/ld/testsuite/ld-powerpc/tlsexetoc.d
@@ -65,9 +65,6 @@ Disassembly of section \.text:
 .*	(7d 89 03 a6|a6 03 89 7d) 	mtctr   r12
 .*	(e9 6b 00 10|10 00 6b e9) 	ld      r11,16\(r11\)
 .*	(4e 80 04 20|20 04 80 4e) 	bctr
-.*	(60 00 00 00|00 00 00 60) 	nop
-.*	(60 00 00 00|00 00 00 60) 	nop
-.*	(60 00 00 00|00 00 00 60) 	nop
 .* <__tls_get_addr_opt@plt>:
 .*	(38 00 00 00|00 00 00 38) 	li      r0,0
-.*	(4b ff ff c4|c4 ff ff 4b) 	b       .*
+.*	(4b ff ff d0|d0 ff ff 4b) 	b       .*
diff --git a/ld/testsuite/ld-powerpc/tlsexetoc.r b/ld/testsuite/ld-powerpc/tlsexetoc.r
index ce746d9dce0..14096ac3eae 100644
--- a/ld/testsuite/ld-powerpc/tlsexetoc.r
+++ b/ld/testsuite/ld-powerpc/tlsexetoc.r
@@ -16,7 +16,7 @@ Section Headers:
  +\[[ 0-9]+\] \.dynstr +.*
  +\[[ 0-9]+\] \.rela\.dyn +.*
  +\[[ 0-9]+\] \.rela\.plt +.*
- +\[[ 0-9]+\] \.text +PROGBITS .* 0+e8 0+ +AX +0 +0 +32
+ +\[[ 0-9]+\] \.text +PROGBITS .* 0+dc 0+ +AX +0 +0 +32
  +\[[ 0-9]+\] \.tdata +PROGBITS .* 0+38 0+ WAT +0 +0 +8
  +\[[ 0-9]+\] \.tbss +NOBITS .* 0+38 0+ WAT +0 +0 +8
  +\[[ 0-9]+\] \.dynamic +DYNAMIC .* 0+160 10 +WA +4 +0 +8
diff --git a/ld/testsuite/ld-powerpc/tlsopt5_32.d b/ld/testsuite/ld-powerpc/tlsopt5_32.d
index 4f1bf06dd3d..822c93cf496 100644
--- a/ld/testsuite/ld-powerpc/tlsopt5_32.d
+++ b/ld/testsuite/ld-powerpc/tlsopt5_32.d
@@ -40,17 +40,11 @@ Disassembly of section \.text:
 .*:	(20 04 80 4e|4e 80 04 20) 	bctr
 .*:	(00 00 00 60|60 00 00 00) 	nop
 
-.* <__glink>:
-.*:	(00 00 00 60|60 00 00 00) 	nop
-.*:	(00 00 00 60|60 00 00 00) 	nop
-.*:	(00 00 00 60|60 00 00 00) 	nop
-.*:	(00 00 00 60|60 00 00 00) 	nop
-
-.* <__glink_PLTresolve>:
+.* <__glink(_PLTresolve)?>:
 .*:	(00 00 6b 3d|3d 6b 00 00) 	addis   r11,r11,0
 .*:	(a6 02 08 7c|7c 08 02 a6) 	mflr    r0
 .*:	(05 00 9f 42|42 9f 00 05) 	bcl     .*
-.*:	(1c 00 6b 39|39 6b 00 1c) 	addi    r11,r11,28
+.*:	(0c 00 6b 39|39 6b 00 0c) 	addi    r11,r11,12
 .*:	(a6 02 88 7d|7d 88 02 a6) 	mflr    r12
 .*:	(a6 03 08 7c|7c 08 03 a6) 	mtlr    r0
 .*:	(50 58 6c 7d|7d 6c 58 50) 	subf    r11,r12,r11
diff --git a/ld/testsuite/ld-powerpc/tlsso.d b/ld/testsuite/ld-powerpc/tlsso.d
index 8ac25e67059..58c9dee6cc6 100644
--- a/ld/testsuite/ld-powerpc/tlsso.d
+++ b/ld/testsuite/ld-powerpc/tlsso.d
@@ -71,9 +71,6 @@ Disassembly of section \.text:
 .*	(7d 89 03 a6|a6 03 89 7d) 	mtctr   r12
 .*	(e9 6b 00 10|10 00 6b e9) 	ld      r11,16\(r11\)
 .*	(4e 80 04 20|20 04 80 4e) 	bctr
-.*	(60 00 00 00|00 00 00 60) 	nop
-.*	(60 00 00 00|00 00 00 60) 	nop
-.*	(60 00 00 00|00 00 00 60) 	nop
 .* <__tls_get_addr@plt>:
 .*	(38 00 00 00|00 00 00 38) 	li      r0,0
-.*	(4b ff ff c4|c4 ff ff 4b) 	b       .*
+.*	(4b ff ff d0|d0 ff ff 4b) 	b       .*
diff --git a/ld/testsuite/ld-powerpc/tlstocso.d b/ld/testsuite/ld-powerpc/tlstocso.d
index ad9481aa887..8d55feedcfa 100644
--- a/ld/testsuite/ld-powerpc/tlstocso.d
+++ b/ld/testsuite/ld-powerpc/tlstocso.d
@@ -55,9 +55,6 @@ Disassembly of section \.text:
 .*	(7d 89 03 a6|a6 03 89 7d) 	mtctr   r12
 .*	(e9 6b 00 10|10 00 6b e9) 	ld      r11,16\(r11\)
 .*	(4e 80 04 20|20 04 80 4e) 	bctr
-.*	(60 00 00 00|00 00 00 60) 	nop
-.*	(60 00 00 00|00 00 00 60) 	nop
-.*	(60 00 00 00|00 00 00 60) 	nop
 .* <__tls_get_addr@plt>:
 .*	(38 00 00 00|00 00 00 38) 	li      r0,0
-.*	(4b ff ff c4|c4 ff ff 4b) 	b       .*
+.*	(4b ff ff d0|d0 ff ff 4b) 	b       .*