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| author | Richard Sandiford <richard.sandiford@arm.com> | 2023-03-30 11:09:13 +0100 |
|---|---|---|
| committer | Richard Sandiford <richard.sandiford@arm.com> | 2023-03-30 11:09:13 +0100 |
| commit | ed429b33c1ee8d6d8f8e640e58f04ec800bc7b2a (patch) | |
| tree | 9dec9ddf10c70e8d8c16f5f0820eb23eefe4a733 /include | |
| parent | 80752eb0989b85e88af7f1f4627dbed8a42dfe6d (diff) | |
| download | binutils-gdb-ed429b33c1ee8d6d8f8e640e58f04ec800bc7b2a.tar.gz | |
aarch64: Add the SME2 MLAL and MLSL instructions
The {BF,F,S,U}MLAL and {BF,F,S,U}MLSL instructions share the same
encoding. They are the first instance of a ZA (as opposed to ZA tile)
operand having a range of offsets. As with ZA tiles, the expected
range size is encoded in the operand-specific data field.
Diffstat (limited to 'include')
| -rw-r--r-- | include/opcode/aarch64.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index 8c7646a0ce3..3b58bfaf146 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -510,14 +510,18 @@ enum aarch64_opnd AARCH64_OPND_SME_PNn3_INDEX2, /* Indexed pred-as-counter reg, bits [9:5]. */ AARCH64_OPND_SME_list_of_64bit_tiles, /* SME list of ZA tiles. */ AARCH64_OPND_SME_ZA_HV_idx_ldstr, /* SME destination ZA tile vector. */ + AARCH64_OPND_SME_ZA_array_off2x2, /* SME ZA[<Wv>, #<imm2>*2:<imm2>*2+1]. */ AARCH64_OPND_SME_ZA_array_off3_0, /* SME ZA[<Wv>{, #<imm3>}]. */ AARCH64_OPND_SME_ZA_array_off3_5, /* SME ZA[<Wv>{, #<imm3>}]. */ + AARCH64_OPND_SME_ZA_array_off3x2, /* SME ZA[<Wv>, #<imm3>*2:<imm3>*2+1]. */ AARCH64_OPND_SME_ZA_array_off4, /* SME ZA[<Wv>{, #<imm>}]. */ AARCH64_OPND_SME_ADDR_RI_U4xVL, /* SME [<Xn|SP>{, #<imm>, MUL VL}]. */ AARCH64_OPND_SME_SM_ZA, /* SME {SM | ZA}. */ AARCH64_OPND_SME_PnT_Wm_imm, /* SME <Pn>.<T>[<Wm>, #<imm>]. */ AARCH64_OPND_SME_Zm_INDEX1, /* Zn.T[index], bits [19:16,10]. */ AARCH64_OPND_SME_Zm_INDEX2, /* Zn.T[index], bits [19:16,11:10]. */ + AARCH64_OPND_SME_Zm_INDEX3_2, /* Zn.T[index], bits [19:16,11:10,2]. */ + AARCH64_OPND_SME_Zm_INDEX3_10, /* Zn.T[index], bits [19:16,15,11:10]. */ AARCH64_OPND_SME_Zn_INDEX1_16, /* Zn[index], bits [9:5] and [16:16]. */ AARCH64_OPND_SME_Zn_INDEX2_15, /* Zn[index], bits [9:5] and [16:15]. */ AARCH64_OPND_SME_Zn_INDEX2_16, /* Zn[index], bits [9:5] and [17:16]. */ |