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| author | Kuan-Lin Chen <kuanlinchentw@gmail.com> | 2014-09-10 09:46:32 +0800 |
|---|---|---|
| committer | Kuan-Lin Chen <kuanlinchentw@gmail.com> | 2014-09-16 12:28:11 +0800 |
| commit | 40c7a7cb74ee4a9ec0830d734198fcd0e99c3a37 (patch) | |
| tree | b28e7367173b15a3be3b1dd05dafa6e811f02f5a /include/opcode/nds32.h | |
| parent | 5b636fed3a28c9237c187999490f8e58d54b2d83 (diff) | |
| download | binutils-gdb-40c7a7cb74ee4a9ec0830d734198fcd0e99c3a37.tar.gz | |
NDS32/opcodes: Add audio ISA extension and modify the disassemble implemnt.
First, add nds32 audio ISA extension including opcodes and registers.
Second, redesign the disassemble implement.
The original disassemble decode instruction opcode using switch-case.
It is hard to synchronize when adding new instructions.
Therefore, the new implement reuses nds32_opcodes to dump the instructions.
Diffstat (limited to 'include/opcode/nds32.h')
| -rw-r--r-- | include/opcode/nds32.h | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/include/opcode/nds32.h b/include/opcode/nds32.h index 47b1c49fd57..9592be668f4 100644 --- a/include/opcode/nds32.h +++ b/include/opcode/nds32.h @@ -29,6 +29,7 @@ #define REG_R16 16 #define REG_R20 20 #define REG_TA 15 +#define REG_TP 27 #define REG_FP 28 #define REG_GP 29 #define REG_LP 30 @@ -358,12 +359,13 @@ enum n32_opcodes N32_ALU2_SUB_SC, N32_ALU2_ADD_WC, N32_ALU2_SUB_WC, - N32_ALU2_0x14, + N32_ALU2_KMxy, N32_ALU2_0x15, N32_ALU2_0x16, N32_ALU2_FFZMISM, - N32_ALU2_QADD = 0x18, - N32_ALU2_QSUB, + N32_ALU2_KADD = 0x18, + N32_ALU2_KSUB, + N32_ALU2_KSLRA, N32_ALU2_MFUSR = 0x20, N32_ALU2_MTUSR, N32_ALU2_0x22, @@ -459,7 +461,7 @@ enum n32_opcodes N32_MISC_TLBOP, N32_MISC_0xf, - /* bit[0;4] */ + /* bit[0:4] */ N32_SIMD_PBSAD = 0, N32_SIMD_PBSADA = 1, |