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| author | Richard Sandiford <richard.sandiford@arm.com> | 2023-03-30 11:09:08 +0100 |
|---|---|---|
| committer | Richard Sandiford <richard.sandiford@arm.com> | 2023-03-30 11:09:08 +0100 |
| commit | 8c2216b2773ee9e5a233fa29e12b61d1646af18e (patch) | |
| tree | 21869638e2bb5d716e114297cd07cc21432153f7 /gold/tilegx.cc | |
| parent | 38c5aa5e88406193fe184a129cd397bc09c304e2 (diff) | |
| download | binutils-gdb-8c2216b2773ee9e5a233fa29e12b61d1646af18e.tar.gz | |
aarch64: Tweak register list errors
The error for invalid register lists had the form:
invalid number of registers in the list; N registers are expected at operand M -- `insn'
This seems a bit verbose. Also, the "bracketing" is really:
(invalid number of registers in the list; N registers are expected) at operand M
but the semicolon works against that.
This patch goes for slightly shorter messages, setting a template
that later patches can use for more complex cases.
Diffstat (limited to 'gold/tilegx.cc')
0 files changed, 0 insertions, 0 deletions