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author | Jan Beulich <jbeulich@suse.com> | 2020-01-03 10:12:49 +0100 |
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committer | Jan Beulich <jbeulich@suse.com> | 2020-01-03 10:12:49 +0100 |
commit | f4950f76fa56bd60314f05620c39fb31e96bb088 (patch) | |
tree | cbf63ab1f340a2528f40b48b590b3a38f92ab264 /gas | |
parent | 4bb7a87e74e66a7d32cbd39e6fc8e54f25a5ad0d (diff) | |
download | binutils-gdb-f4950f76fa56bd60314f05620c39fb31e96bb088.tar.gz |
Arm64: correct 64-bit element fmmla encoding
There's just one bit of difference to the 32-bit element form, as
per the documentation.
Diffstat (limited to 'gas')
-rw-r--r-- | gas/ChangeLog | 5 | ||||
-rw-r--r-- | gas/testsuite/gas/aarch64/f64mm.d | 4 | ||||
-rw-r--r-- | gas/testsuite/gas/aarch64/sve-movprfx-mm.d | 2 |
3 files changed, 8 insertions, 3 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog index 86134cb5b66..933c17e6036 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,8 @@ +2020-01-03 Jan Beulich <jbeulich@suse.com> + + * testsuite/gas/aarch64/f64mm.d, + testsuite/gas/aarch64/sve-movprfx-mm.d: Adjust expectations. + 2020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com> * config/tc-z80.c: Add new architectures: Z180 and eZ80. Add diff --git a/gas/testsuite/gas/aarch64/f64mm.d b/gas/testsuite/gas/aarch64/f64mm.d index a09179a93be..b2aa86132ac 100644 --- a/gas/testsuite/gas/aarch64/f64mm.d +++ b/gas/testsuite/gas/aarch64/f64mm.d @@ -6,8 +6,8 @@ Disassembly of section \.text: 0+ <\.text>: - *[0-9a-f]+: 64dbe6b1 fmmla z17\.d, z21\.d, z27\.d - *[0-9a-f]+: 64c0e400 fmmla z0\.d, z0\.d, z0\.d + *[0-9a-f]+: 64fbe6b1 fmmla z17\.d, z21\.d, z27\.d + *[0-9a-f]+: 64e0e400 fmmla z0\.d, z0\.d, z0\.d *[0-9a-f]+: a43b17f1 ld1rob {z17\.b}, p5/z, \[sp, x27\] *[0-9a-f]+: a42003e0 ld1rob {z0\.b}, p0/z, \[sp, x0\] *[0-9a-f]+: a4bb17f1 ld1roh {z17\.h}, p5/z, \[sp, x27\] diff --git a/gas/testsuite/gas/aarch64/sve-movprfx-mm.d b/gas/testsuite/gas/aarch64/sve-movprfx-mm.d index 88415ef098f..f2b480dfe48 100644 --- a/gas/testsuite/gas/aarch64/sve-movprfx-mm.d +++ b/gas/testsuite/gas/aarch64/sve-movprfx-mm.d @@ -21,4 +21,4 @@ Disassembly of section \.text: *[0-9a-f]+: 0420bc11 movprfx z17, z0 *[0-9a-f]+: 64bbe6b1 fmmla z17\.s, z21\.s, z27\.s *[0-9a-f]+: 0420bc11 movprfx z17, z0 - *[0-9a-f]+: 64dbe6b1 fmmla z17\.d, z21\.d, z27\.d + *[0-9a-f]+: 64fbe6b1 fmmla z17\.d, z21\.d, z27\.d |