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authorPrzemyslaw Wirkus <przemyslaw.wirkus@arm.com>2020-11-16 20:37:39 +0000
committerPrzemyslaw Wirkus <przemyslaw.wirkus@arm.com>2020-11-16 21:07:17 +0000
commite64441b14c26a5361e030064cf62c419572fc392 (patch)
treedbdde421e2aed9b228cd3526b4c959858761dcd7 /gas
parent1bbda94fe0174714e296335e7cc744b5fb618525 (diff)
downloadbinutils-gdb-e64441b14c26a5361e030064cf62c419572fc392.tar.gz
aarch64: Extract Condition flag manipulation feature from Armv8.4-A
Extract FLAGM (Condition flag manipulation) feature from Armv8.4-A. Please note that FLAGM stays a Armv8.4-A feature but now can be assigned to other architectures or CPUs. New -march option +flagm is added to enable independently this feature.
Diffstat (limited to 'gas')
-rw-r--r--gas/ChangeLog8
-rw-r--r--gas/NEWS4
-rw-r--r--gas/config/tc-aarch64.c2
-rw-r--r--gas/doc/c-aarch64.texi6
-rw-r--r--gas/testsuite/gas/aarch64/flagm.d16
-rw-r--r--gas/testsuite/gas/aarch64/flagm.s16
6 files changed, 51 insertions, 1 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog
index 369377660b1..c289dd7ed36 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,5 +1,13 @@
2020-11-16 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
+ * NEWS: Update news.
+ * config/tc-aarch64.c: New feature flag +flagm.
+ * doc/c-aarch64.texi: Update docs.
+ * testsuite/gas/aarch64/flagm.d: New test.
+ * testsuite/gas/aarch64/flagm.s: New test.
+
+2020-11-16 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
+
* config/tc-arm.c (arm_cpus): Add Cortex-A78C.
* doc/c-arm.texi: Document -mcpu=cortex-a78c.
* testsuite/gas/arm/cpu-cortex-a78c.d: New test.
diff --git a/gas/NEWS b/gas/NEWS
index 88415076c18..1d4b4be9be1 100644
--- a/gas/NEWS
+++ b/gas/NEWS
@@ -25,7 +25,9 @@
AArch64.
* Add support for +csre feature for -march. Add CSR PDEC instruction for CSRE
- feature.
+ feature in AArch64.
+
+* Add support for +flagm feature for -march in Armv8.4 AArch64.
* Add support for +ls64 feature for -march in Armv8.7 AArch64. Add atomic
64-byte load/store instructions for this feature.
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 9ae07276989..ca29fdc1724 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -9225,6 +9225,8 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = {
AARCH64_ARCH_NONE},
{"ls64", AARCH64_FEATURE (AARCH64_FEATURE_LS64, 0),
AARCH64_ARCH_NONE},
+ {"flagm", AARCH64_FEATURE (AARCH64_FEATURE_FLAGM, 0),
+ AARCH64_ARCH_NONE},
{NULL, AARCH64_ARCH_NONE, AARCH64_ARCH_NONE},
};
diff --git a/gas/doc/c-aarch64.texi b/gas/doc/c-aarch64.texi
index 526e8089b76..c005286bc4a 100644
--- a/gas/doc/c-aarch64.texi
+++ b/gas/doc/c-aarch64.texi
@@ -226,6 +226,12 @@ automatically cause those extensions to be disabled.
@code{pmullt} and @code{pmullb} instructions.
@item @code{sve2-sha3} @tab ARMv8-A @tab No
@tab Enable SVE2 SHA3 Extension.
+@item @code{flagm} @tab ARMv8-A @tab ARMv8.4-A or later
+ @tab Enable Flag Manipulation instructions.
+@item @code{csre} @tab ARMv8-A @tab No
+ @tab Enable Call Stack Recorder Extension.
+@item @code{ls64} @tab ARMv8-6 @tab ARMv8.7-A or later
+ @tab Enable 64 Byte Loads/Stores.
@end multitable
@node AArch64 Syntax
diff --git a/gas/testsuite/gas/aarch64/flagm.d b/gas/testsuite/gas/aarch64/flagm.d
new file mode 100644
index 00000000000..2f993bbfd38
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/flagm.d
@@ -0,0 +1,16 @@
+#name: FLAGM (Condition flag manipulation) feature
+#objdump: -dr
+
+.*: file format .*
+
+Disassembly of section \.text:
+
+0+ <.*>:
+.*: d500401f cfinv
+.*: ba0407cf rmif x30, #8, #15
+.*: 3a00080d setf8 w0
+.*: 3a00480d setf16 w0
+.*: d500401f cfinv
+.*: ba0407cf rmif x30, #8, #15
+.*: 3a00080d setf8 w0
+.*: 3a00480d setf16 w0
diff --git a/gas/testsuite/gas/aarch64/flagm.s b/gas/testsuite/gas/aarch64/flagm.s
new file mode 100644
index 00000000000..0a54f14c19e
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/flagm.s
@@ -0,0 +1,16 @@
+/* FLAGM (Condition flag manipulation) feature from Armv8.4-A. */
+.arch armv8.4-a
+
+ cfinv
+ rmif x30, #8, #15
+ setf8 w0
+ setf16 w0
+
+
+/* FLAGM feature enabled with +flagm. */
+.arch armv8-a+flagm
+
+ cfinv
+ rmif x30, #8, #15
+ setf8 w0
+ setf16 w0