diff options
author | Richard Henderson <rth@redhat.com> | 1999-05-03 07:29:11 +0000 |
---|---|---|
committer | Richard Henderson <rth@redhat.com> | 1999-05-03 07:29:11 +0000 |
commit | 252b5132c753830d5fd56823373aed85f2a0db63 (patch) | |
tree | 1af963bfd8d3e55167b81def4207f175eaff3a56 /gas/testsuite/gas/arc | |
download | binutils-gdb-binu_ss_19990502.tar.gz |
19990502 sourceware importbinu_ss_19990502
Diffstat (limited to 'gas/testsuite/gas/arc')
-rw-r--r-- | gas/testsuite/gas/arc/alias.d | 68 | ||||
-rw-r--r-- | gas/testsuite/gas/arc/alias.s | 76 | ||||
-rw-r--r-- | gas/testsuite/gas/arc/arc.exp | 114 | ||||
-rw-r--r-- | gas/testsuite/gas/arc/branch.d | 45 | ||||
-rw-r--r-- | gas/testsuite/gas/arc/branch.s | 47 | ||||
-rw-r--r-- | gas/testsuite/gas/arc/flag.d | 29 | ||||
-rw-r--r-- | gas/testsuite/gas/arc/flag.s | 27 | ||||
-rw-r--r-- | gas/testsuite/gas/arc/insn3.d | 44 | ||||
-rw-r--r-- | gas/testsuite/gas/arc/insn3.s | 52 | ||||
-rw-r--r-- | gas/testsuite/gas/arc/j.d | 75 | ||||
-rw-r--r-- | gas/testsuite/gas/arc/j.s | 45 | ||||
-rw-r--r-- | gas/testsuite/gas/arc/ld.d | 30 | ||||
-rw-r--r-- | gas/testsuite/gas/arc/ld.s | 24 | ||||
-rw-r--r-- | gas/testsuite/gas/arc/math.d | 78 | ||||
-rw-r--r-- | gas/testsuite/gas/arc/math.s | 89 | ||||
-rw-r--r-- | gas/testsuite/gas/arc/sshift.d | 44 | ||||
-rw-r--r-- | gas/testsuite/gas/arc/sshift.s | 52 | ||||
-rw-r--r-- | gas/testsuite/gas/arc/st.d | 25 | ||||
-rw-r--r-- | gas/testsuite/gas/arc/st.s | 19 | ||||
-rw-r--r-- | gas/testsuite/gas/arc/warn.exp | 13 | ||||
-rw-r--r-- | gas/testsuite/gas/arc/warn.s | 14 |
21 files changed, 1010 insertions, 0 deletions
diff --git a/gas/testsuite/gas/arc/alias.d b/gas/testsuite/gas/arc/alias.d new file mode 100644 index 00000000000..b51acf63e9e --- /dev/null +++ b/gas/testsuite/gas/arc/alias.d @@ -0,0 +1,68 @@ +#objdump: -dr +#name: @OC@ + +# Test the @OC@ insn. + +.*: +file format elf32-.*arc + +Disassembly of section .text: +00000000 @IC+0@008200 @OC@ r0,r1 +00000004 @IC+3@6e3800 @OC@ fp,sp +00000008 @IC+0@1ffe00 @OC@ r0,0 +0000000c @IC+0@3fffff @OC@ r1,-1 +00000010 @IC+7@e10400 @OC@ 0,r2 +00000014 @IC+7@e187ff @OC@ -1,r3 +00000018 @IC+0@9ffeff @OC@ r4,255 +0000001c @IC+7@e28aff @OC@ 255,r5 +00000020 @IC+0@dfff00 @OC@ r6,-256 +00000024 @IC+7@e38f00 @OC@ -256,r7 +00000028 @IC+1@1f7c00 @OC@ r8,256 +00000030 @IC+1@3f7c00 @OC@ r9,-257 +00000038 @IC+7@c51400 @OC@ 511,r10 +00000040 @IC+1@7f7c00 @OC@ r11,1111638594 +00000048 @IC+7@c61800 @OC@ 305419896,r12 +00000050 @IC+7@ff7cff @OC@ 255,256 +00000058 @IC+7@dffeff @OC@ 256,255 +00000060 @IC+0@1f7c00 @OC@ r0,0 + RELOC: 00000064 R_ARC_32 foo +00000068 @IC+0@008200 @OC@ r0,r1 +0000006c @IC+0@620800 @OC@ r3,r4 +00000070 @IC+0@c38e01 @OC@.eq r6,r7 +00000074 @IC+1@251401 @OC@.eq r9,r10 +00000078 @IC+1@869a02 @OC@.ne r12,r13 +0000007c @IC+1@e82002 @OC@.ne r15,r16 +00000080 @IC+2@49a603 @OC@.p r18,r19 +00000084 @IC+2@ab2c03 @OC@.p r21,r22 +00000088 @IC+3@0cb204 @OC@.n r24,r25 +0000008c @IC+3@6e3804 @OC@.n fp,sp +00000090 @IC+3@cfbe05 @OC@.c ilink2,blink +00000094 @IC+4@314405 @OC@.c r33,r34 +00000098 @IC+4@92ca05 @OC@.c r36,r37 +0000009c @IC+4@f45006 @OC@.nc r39,r40 +000000a0 @IC+5@55d606 @OC@.nc r42,r43 +000000a4 @IC+5@b75c06 @OC@.nc r45,r46 +000000a8 @IC+6@18e207 @OC@.v r48,r49 +000000ac @IC+6@7a6807 @OC@.v r51,r52 +000000b0 @IC+6@dbee08 @OC@.nv r54,r55 +000000b4 @IC+7@3d7408 @OC@.nv r57,r58 +000000b8 @IC+7@9e7809 @OC@.gt lp_count,lp_count +000000bc @IC+0@1f7c0a @OC@.ge r0,0 +000000c4 @IC+7@c0820b @OC@.lt 1,r1 +000000cc @IC+7@df7c0c @OC@.le 2,2 +000000d4 @IC+0@61860d @OC@.hi r3,r3 +000000d8 @IC+0@82080e @OC@.ls r4,r4 +000000dc @IC+0@a28a0f @OC@.pnz r5,r5 +000000e0 @IC+0@008300 @OC@.f r0,r1 +000000e4 @IC+0@5efa01 @OC@.f r2,1 +000000e8 @IC+7@a18601 @OC@.f 1,r3 +000000ec @IC+7@a20800 @OC@.f 0,r4 +000000f0 @IC+0@bf7d00 @OC@.f r5,512 +000000f8 @IC+7@c30d00 @OC@.f 512,r6 +00000100 @IC+7@df7d00 @OC@.f 512,512 +00000108 @IC+0@008301 @OC@.eq.f r0,r1 +0000010c @IC+0@3f7d02 @OC@.ne.f r1,0 +00000114 @IC+7@c1050b @OC@.lt.f 0,r2 +0000011c @IC+7@c10509 @OC@.gt.f 1,r2 +00000124 @IC+0@1f7d0c @OC@.le.f r0,512 +0000012c @IC+7@c1050a @OC@.ge.f 512,r2 +00000134 @IC+7@df7d04 @OC@.n.f 512,512 diff --git a/gas/testsuite/gas/arc/alias.s b/gas/testsuite/gas/arc/alias.s new file mode 100644 index 00000000000..d524440f987 --- /dev/null +++ b/gas/testsuite/gas/arc/alias.s @@ -0,0 +1,76 @@ +# @OC@ test + +# reg,reg + @OC@ r0,r1 + @OC@ fp,sp + +# shimm values + @OC@ r0,0 + @OC@ r1,-1 + @OC@ 0,r2 + @OC@ -1,r3 + @OC@ r4,255 + @OC@ 255,r5 + @OC@ r6,-256 + @OC@ -256,r7 + +# limm values + @OC@ r8,256 + @OC@ r9,-257 + @OC@ 511,r10 + @OC@ r11,0x42424242 + @OC@ 0x12345678,r12 + +# shimm and limm + @OC@ 255,256 + @OC@ 256,255 + +# symbols + @OC@ r0,foo + +# conditional execution + @OC@.al r0,r1 + @OC@.ra r3,r4 + @OC@.eq r6,r7 + @OC@.z r9,r10 + @OC@.ne r12,r13 + @OC@.nz r15,r16 + @OC@.pl r18,r19 + @OC@.p r21,r22 + @OC@.mi r24,r25 + @OC@.n r27,r28 + @OC@.cs r30,r31 + @OC@.c r33,r34 + @OC@.lo r36,r37 + @OC@.cc r39,r40 + @OC@.nc r42,r43 + @OC@.hs r45,r46 + @OC@.vs r48,r49 + @OC@.v r51,r52 + @OC@.vc r54,r55 + @OC@.nv r57,r58 + @OC@.gt r60,r60 + @OC@.ge r0,0 + @OC@.lt 1,r1 + @OC@.le 2,2 + @OC@.hi r3,r3 + @OC@.ls r4,r4 + @OC@.pnz r5,r5 + +# flag setting + @OC@.f r0,r1 + @OC@.f r2,1 + @OC@.f 1,r3 + @OC@.f 0,r4 + @OC@.f r5,512 + @OC@.f 512,r6 + @OC@.f 512,512 + +# conditional execution + flag setting + @OC@.eq.f r0,r1 + @OC@.ne.f r1,0 + @OC@.lt.f 0,r2 + @OC@.gt.f 1,r2 + @OC@.le.f r0,512 + @OC@.ge.f 512,r2 + @OC@.n.f 512,512 diff --git a/gas/testsuite/gas/arc/arc.exp b/gas/testsuite/gas/arc/arc.exp new file mode 100644 index 00000000000..b0984535e2e --- /dev/null +++ b/gas/testsuite/gas/arc/arc.exp @@ -0,0 +1,114 @@ +# ARC gas testsuite + +# Test an insn from a template .s/.d. +# The best way to create the .d file is to run the tests without it, let +# dejagnu crash, run as.new on the just built .s file, run objdump -dr on +# the result of that, copy the result into the .d file, and edit in the +# necessary patterns (@OC@, etc.). Sounds complicated but it's easy. The +# catch is that we assume a working assembler is used to build it. That's +# obviously not entirely kosher, but once the .d file is created one can +# verify it's contents over time. +# +# Template patterns: +# @OC@ - placeholder for the opcode +# @IC+?@ - place holder for the insn code +# @I3+??@ - place holder for the operation code of code 3 insns. + +proc test_template_insn { cpu tmpl opcode icode } { + global srcdir subdir objdir + + # Change @OC@ in the template file to $opcode + + set in_fd [open $srcdir/$subdir/$tmpl.s r] + set out_fd [open $objdir/$opcode.s w] + # FIXME: check return codes + + puts $out_fd "\t.cpu $cpu\n" + while { [gets $in_fd line] >= 0 } { + regsub "@OC@" $line $opcode line + puts $out_fd $line + } + + close $in_fd + close $out_fd + + # Create output template. + + set in_fd [open $srcdir/$subdir/$tmpl.d r] + set out_fd [open $objdir/$opcode.d w] + # FIXME: check return codes + + while { [gets $in_fd line] >= 0 } { + regsub "@OC@" $line $opcode line + #send_user "$line\n" + if [string match "*@IC+?@*" $line] { + # Insert the opcode. It occupies the top 5 bits. + regexp "^(.*)@IC\\+(.)@(.*)$" $line junk leftpart n rightpart + set n [expr ($icode << 3) + $n] + set n [format "%02x" $n] + puts $out_fd "$leftpart$n$rightpart" + } elseif [string match "*@I3+??@*" $line] { + # Insert insn 3 code (register C field) + # b15=8/0, b8=1/0 (their respective hex values in the objdump) + regexp "^(.*)@I3\\+(.)(.)@(.*)$" $line junk leftpart b15 b8 rightpart + set n [expr ($icode << 1) + ($b15 << 4) + ($b8 << 0)] + set n [format "%02x" $n] + puts $out_fd "$leftpart$n$rightpart" + } else { + puts $out_fd $line + } + } + + close $in_fd + close $out_fd + + # Finally, run the test. + + run_dump_test $objdir/$opcode + + # "make clean" won't delete these, so for now we must. + catch "exec rm -f $objdir/$opcode.s $objdir/$opcode.d" +} + +# Run the tests. + +if [istarget arc*-*-*] then { + + test_template_insn base math adc 9 + test_template_insn base math add 8 + test_template_insn base math and 12 + test_template_insn base math bic 14 + test_template_insn base math or 13 + test_template_insn base math sbc 11 + test_template_insn base math sub 10 + test_template_insn base math xor 15 + + test_template_insn base alias mov 12 + test_template_insn base alias rlc 9 + test_template_insn base alias asl 8 +# `lsl' gets dumped as `asl' so this must be tested elsewhere. +# test_template_insn base alias lsl 8 + + test_template_insn base sshift asr 1 + test_template_insn base sshift lsr 2 + test_template_insn base sshift ror 3 + test_template_insn base sshift rrc 4 + + test_template_insn base branch b 4 + test_template_insn base branch bl 5 + test_template_insn base branch lp 6 + + run_dump_test "j" + + test_template_insn base insn3 sexb 5 + test_template_insn base insn3 sexw 6 + test_template_insn base insn3 extb 7 + test_template_insn base insn3 extw 8 + + run_dump_test "flag" +# run_dump_test "nop" + + run_dump_test "ld" + run_dump_test "st" + +} diff --git a/gas/testsuite/gas/arc/branch.d b/gas/testsuite/gas/arc/branch.d new file mode 100644 index 00000000000..4c9b014b1ba --- /dev/null +++ b/gas/testsuite/gas/arc/branch.d @@ -0,0 +1,45 @@ +#objdump: -dr +#name: @OC@ + +# Test the @OC@ insn. + +.*: +file format elf32-.*arc + +Disassembly of section .text: +00000000 <text_label> @IC+7@ffff80 @OC@ 00000000 <text_label> +00000004 <text_label\+4> @IC+7@ffff00 @OC@ 00000000 <text_label> +00000008 <text_label\+8> @IC+7@fffe80 @OC@ 00000000 <text_label> +0000000c <text_label\+c> @IC+7@fffe01 @OC@eq 00000000 <text_label> +00000010 <text_label\+10> @IC+7@fffd81 @OC@eq 00000000 <text_label> +00000014 <text_label\+14> @IC+7@fffd02 @OC@ne 00000000 <text_label> +00000018 <text_label\+18> @IC+7@fffc82 @OC@ne 00000000 <text_label> +0000001c <text_label\+1c> @IC+7@fffc03 @OC@p 00000000 <text_label> +00000020 <text_label\+20> @IC+7@fffb83 @OC@p 00000000 <text_label> +00000024 <text_label\+24> @IC+7@fffb04 @OC@n 00000000 <text_label> +00000028 <text_label\+28> @IC+7@fffa84 @OC@n 00000000 <text_label> +0000002c <text_label\+2c> @IC+7@fffa05 @OC@c 00000000 <text_label> +00000030 <text_label\+30> @IC+7@fff985 @OC@c 00000000 <text_label> +00000034 <text_label\+34> @IC+7@fff905 @OC@c 00000000 <text_label> +00000038 <text_label\+38> @IC+7@fff886 @OC@nc 00000000 <text_label> +0000003c <text_label\+3c> @IC+7@fff806 @OC@nc 00000000 <text_label> +00000040 <text_label\+40> @IC+7@fff786 @OC@nc 00000000 <text_label> +00000044 <text_label\+44> @IC+7@fff707 @OC@v 00000000 <text_label> +00000048 <text_label\+48> @IC+7@fff687 @OC@v 00000000 <text_label> +0000004c <text_label\+4c> @IC+7@fff608 @OC@nv 00000000 <text_label> +00000050 <text_label\+50> @IC+7@fff588 @OC@nv 00000000 <text_label> +00000054 <text_label\+54> @IC+7@fff509 @OC@gt 00000000 <text_label> +00000058 <text_label\+58> @IC+7@fff48a @OC@ge 00000000 <text_label> +0000005c <text_label\+5c> @IC+7@fff40b @OC@lt 00000000 <text_label> +00000060 <text_label\+60> @IC+7@fff38c @OC@le 00000000 <text_label> +00000064 <text_label\+64> @IC+7@fff30d @OC@hi 00000000 <text_label> +00000068 <text_label\+68> @IC+7@fff28e @OC@ls 00000000 <text_label> +0000006c <text_label\+6c> @IC+7@fff20f @OC@pnz 00000000 <text_label> +00000070 <text_label\+70> @IC+7@ffff80 @OC@ 00000070 <text_label\+70> + RELOC: 00000070 R_ARC_B22_PCREL external_text_label +00000074 <text_label\+74> @IC+0@000000 @OC@ 00000078 <text_label\+78> +00000078 <text_label\+78> @IC+7@fff0a0 @OC@.d 00000000 <text_label> +0000007c <text_label\+7c> @IC+7@fff000 @OC@ 00000000 <text_label> +00000080 <text_label\+80> @IC+7@ffefc0 @OC@.jd 00000000 <text_label> +00000084 <text_label\+84> @IC+7@ffef21 @OC@eq.d 00000000 <text_label> +00000088 <text_label\+88> @IC+7@ffee82 @OC@ne 00000000 <text_label> +0000008c <text_label\+8c> @IC+7@ffee46 @OC@nc.jd 00000000 <text_label> diff --git a/gas/testsuite/gas/arc/branch.s b/gas/testsuite/gas/arc/branch.s new file mode 100644 index 00000000000..8bf1618ffc4 --- /dev/null +++ b/gas/testsuite/gas/arc/branch.s @@ -0,0 +1,47 @@ +# @OC@ test + +text_label: + +# Condition tests + @OC@ text_label + @OC@al text_label + @OC@ra text_label + @OC@eq text_label + @OC@z text_label + @OC@ne text_label + @OC@nz text_label + @OC@pl text_label + @OC@p text_label + @OC@mi text_label + @OC@n text_label + @OC@cs text_label + @OC@c text_label + @OC@lo text_label + @OC@cc text_label + @OC@nc text_label + @OC@hs text_label + @OC@vs text_label + @OC@v text_label + @OC@vc text_label + @OC@nv text_label + @OC@gt text_label + @OC@ge text_label + @OC@lt text_label + @OC@le text_label + @OC@hi text_label + @OC@ls text_label + @OC@pnz text_label + + @OC@ external_text_label + + @OC@ 0 + +# Delay slots + @OC@.d text_label + @OC@.nd text_label + @OC@.jd text_label + +# Condition tests and delay slots + @OC@eq.d text_label + @OC@ne.nd text_label + @OC@cc.jd text_label diff --git a/gas/testsuite/gas/arc/flag.d b/gas/testsuite/gas/arc/flag.d new file mode 100644 index 00000000000..68f36d39f1e --- /dev/null +++ b/gas/testsuite/gas/arc/flag.d @@ -0,0 +1,29 @@ +#objdump: -dr +#name: flag + +# Test the flag macro. + +.*: +file format elf32-.*arc + +No symbols in "a.out". +Disassembly of section .text: +00000000 1fa00000 flag r0 +00000004 1fbf8001 flag 1 +00000008 1fbf8002 flag 2 +0000000c 1fbf8004 flag 4 +00000010 1fbf8008 flag 8 +00000014 1fbf8010 flag 16 +00000018 1fbf8020 flag 32 +0000001c 1fbf8040 flag 64 +00000020 1fbf8080 flag 128 +00000024 1fbf0000 flag -2147483647 +0000002c 1fa0000b flag.lt r0 +00000030 1fbf0009 flag.gt 1 +00000038 1fbf0009 flag.gt 2 +00000040 1fbf0009 flag.gt 4 +00000048 1fbf0009 flag.gt 8 +00000050 1fbf0009 flag.gt 16 +00000058 1fbf0009 flag.gt 32 +00000060 1fbf0009 flag.gt 64 +00000068 1fbf0009 flag.gt 128 +00000070 1fbf000a flag.ge -2147483647 diff --git a/gas/testsuite/gas/arc/flag.s b/gas/testsuite/gas/arc/flag.s new file mode 100644 index 00000000000..7067aa5465e --- /dev/null +++ b/gas/testsuite/gas/arc/flag.s @@ -0,0 +1,27 @@ +# flag test + + flag r0 + + flag 1 + flag 2 + flag 4 + flag 8 + flag 16 + flag 32 + flag 64 + flag 128 + + flag 0x80000001 + + flag.lt r0 + + flag.gt 1 + flag.gt 2 + flag.gt 4 + flag.gt 8 + flag.gt 16 + flag.gt 32 + flag.gt 64 + flag.gt 128 + + flag.ge 0x80000001 diff --git a/gas/testsuite/gas/arc/insn3.d b/gas/testsuite/gas/arc/insn3.d new file mode 100644 index 00000000000..c0207a77a4b --- /dev/null +++ b/gas/testsuite/gas/arc/insn3.d @@ -0,0 +1,44 @@ +#objdump: -dr +#name: @OC@ + +# Test the @OC@ insn. + +.*: +file format elf32-.*arc + +Disassembly of section .text: +00000000 1800@I3+80@00 @OC@ r0,r1 +00000004 1b6e@I3+00@00 @OC@ fp,sp +00000008 181f@I3+80@00 @OC@ r0,0 +0000000c 183f@I3+81@ff @OC@ r1,-1 +00000010 1fe1@I3+00@00 @OC@ 0,r2 +00000014 1fe1@I3+81@ff @OC@ -1,r3 +00000018 189f@I3+80@ff @OC@ r4,255 +0000001c 1fe2@I3+80@ff @OC@ 255,r5 +00000020 18df@I3+81@00 @OC@ r6,-256 +00000024 1fe3@I3+81@00 @OC@ -256,r7 +00000028 191f@I3+00@00 @OC@ r8,256 +00000030 193f@I3+00@00 @OC@ r9,-257 +00000038 1fc5@I3+00@00 @OC@ 511,r10 +00000040 197f@I3+00@00 @OC@ r11,1111638594 +00000048 1fc6@I3+00@00 @OC@ 305419896,r12 +00000050 1fff@I3+00@ff @OC@ 255,256 +00000058 1fdf@I3+80@ff @OC@ 256,255 +00000060 181f@I3+00@00 @OC@ r0,0 + RELOC: 00000064 R_ARC_32 foo +00000068 1945@I3+80@01 @OC@.eq r10,r11 +0000006c 1986@I3+80@02 @OC@.ne r12,r13 +00000070 19df@I3+00@0b @OC@.lt r14,0 +00000078 19ff@I3+00@09 @OC@.gt r15,512 +00000080 1800@I3+81@00 @OC@.f r0,r1 +00000084 185e@I3+80@01 @OC@.f r2,1 +00000088 1fa2@I3+00@00 @OC@.f 0,r4 +0000008c 18bf@I3+01@00 @OC@.f r5,512 +00000094 1fc3@I3+01@00 @OC@.f 512,r6 +0000009c 1fdf@I3+01@00 @OC@.f 512,512 +000000a4 1800@I3+81@01 @OC@.eq.f r0,r1 +000000a8 183f@I3+01@02 @OC@.ne.f r1,0 +000000b0 1fc1@I3+01@0b @OC@.lt.f 0,r2 +000000b8 1fc1@I3+01@09 @OC@.gt.f 1,r2 +000000c0 181f@I3+01@0c @OC@.le.f r0,512 +000000c8 1fc1@I3+01@0a @OC@.ge.f 512,r2 +000000d0 1fdf@I3+01@04 @OC@.n.f 512,512 diff --git a/gas/testsuite/gas/arc/insn3.s b/gas/testsuite/gas/arc/insn3.s new file mode 100644 index 00000000000..f12fb88355f --- /dev/null +++ b/gas/testsuite/gas/arc/insn3.s @@ -0,0 +1,52 @@ +# Insn 3 @OC@ test + +# reg,reg + @OC@ r0,r1 + @OC@ fp,sp + +# shimm values + @OC@ r0,0 + @OC@ r1,-1 + @OC@ 0,r2 + @OC@ -1,r3 + @OC@ r4,255 + @OC@ 255,r5 + @OC@ r6,-256 + @OC@ -256,r7 + +# limm values + @OC@ r8,256 + @OC@ r9,-257 + @OC@ 511,r10 + @OC@ r11,0x42424242 + @OC@ 0x12345678,r12 + +# shimm and limm + @OC@ 255,256 + @OC@ 256,255 + +# symbols + @OC@ r0,foo + +# conditional execution + @OC@.eq r10,r11 + @OC@.ne r12,r13 + @OC@.lt r14,0 + @OC@.gt r15,512 + +# flag setting + @OC@.f r0,r1 + @OC@.f r2,1 + @OC@.f 0,r4 + @OC@.f r5,512 + @OC@.f 512,r6 + @OC@.f 512,512 + +# conditional execution + flag setting + @OC@.eq.f r0,r1 + @OC@.ne.f r1,0 + @OC@.lt.f 0,r2 + @OC@.gt.f 1,r2 + @OC@.le.f r0,512 + @OC@.ge.f 512,r2 + @OC@.n.f 512,512 diff --git a/gas/testsuite/gas/arc/j.d b/gas/testsuite/gas/arc/j.d new file mode 100644 index 00000000000..af103f0d1a7 --- /dev/null +++ b/gas/testsuite/gas/arc/j.d @@ -0,0 +1,75 @@ +#objdump: -dr +#name: j + +# Test the j insn. + +.*: +file format elf32-.*arc + +Disassembly of section .text: +00000000 <text_label> 38000000 j r0 +00000004 <text_label\+4> 38000020 j.d r0 +00000008 <text_label\+8> 38000040 j.jd r0 +0000000c <text_label\+c> 38000000 j r0 +00000010 <text_label\+10> 38008000 j r1 +00000014 <text_label\+14> 38008020 j.d r1 +00000018 <text_label\+18> 38008040 j.jd r1 +0000001c <text_label\+1c> 38008000 j r1 +00000020 <text_label\+20> 381f0000 j 0 + RELOC: 00000024 R_ARC_32 .text +00000028 <text_label\+28> 381f0000 j 0 + RELOC: 0000002c R_ARC_32 .text +00000030 <text_label\+30> 381f0000 j 0 + RELOC: 00000034 R_ARC_32 .text +00000038 <text_label\+38> 381f0001 jeq 0 + RELOC: 0000003c R_ARC_32 .text +00000040 <text_label\+40> 381f0001 jeq 0 + RELOC: 00000044 R_ARC_32 .text +00000048 <text_label\+48> 381f0002 jne 0 + RELOC: 0000004c R_ARC_32 .text +00000050 <text_label\+50> 381f0002 jne 0 + RELOC: 00000054 R_ARC_32 .text +00000058 <text_label\+58> 381f0003 jp 0 + RELOC: 0000005c R_ARC_32 .text +00000060 <text_label\+60> 381f0003 jp 0 + RELOC: 00000064 R_ARC_32 .text +00000068 <text_label\+68> 381f0004 jn 0 + RELOC: 0000006c R_ARC_32 .text +00000070 <text_label\+70> 381f0004 jn 0 + RELOC: 00000074 R_ARC_32 .text +00000078 <text_label\+78> 381f0005 jc 0 + RELOC: 0000007c R_ARC_32 .text +00000080 <text_label\+80> 381f0005 jc 0 + RELOC: 00000084 R_ARC_32 .text +00000088 <text_label\+88> 381f0005 jc 0 + RELOC: 0000008c R_ARC_32 .text +00000090 <text_label\+90> 381f0006 jnc 0 + RELOC: 00000094 R_ARC_32 .text +00000098 <text_label\+98> 381f0006 jnc 0 + RELOC: 0000009c R_ARC_32 .text +000000a0 <text_label\+a0> 381f0006 jnc 0 + RELOC: 000000a4 R_ARC_32 .text +000000a8 <text_label\+a8> 381f0007 jv 0 + RELOC: 000000ac R_ARC_32 .text +000000b0 <text_label\+b0> 381f0007 jv 0 + RELOC: 000000b4 R_ARC_32 .text +000000b8 <text_label\+b8> 381f0008 jnv 0 + RELOC: 000000bc R_ARC_32 .text +000000c0 <text_label\+c0> 381f0008 jnv 0 + RELOC: 000000c4 R_ARC_32 .text +000000c8 <text_label\+c8> 381f0009 jgt 0 + RELOC: 000000cc R_ARC_32 .text +000000d0 <text_label\+d0> 381f000a jge 0 + RELOC: 000000d4 R_ARC_32 .text +000000d8 <text_label\+d8> 381f000b jlt 0 + RELOC: 000000dc R_ARC_32 .text +000000e0 <text_label\+e0> 381f000c jle 0 + RELOC: 000000e4 R_ARC_32 .text +000000e8 <text_label\+e8> 381f000d jhi 0 + RELOC: 000000ec R_ARC_32 .text +000000f0 <text_label\+f0> 381f000e jls 0 + RELOC: 000000f4 R_ARC_32 .text +000000f8 <text_label\+f8> 381f000f jpnz 0 + RELOC: 000000fc R_ARC_32 .text +00000100 <text_label\+100> 381f0000 j 0 + RELOC: 00000104 R_ARC_32 external_text_label +00000108 <text_label\+108> 381f0000 j 0 diff --git a/gas/testsuite/gas/arc/j.s b/gas/testsuite/gas/arc/j.s new file mode 100644 index 00000000000..0161af215fc --- /dev/null +++ b/gas/testsuite/gas/arc/j.s @@ -0,0 +1,45 @@ +# j test + +text_label: + j r0 + j.d r0 + j.jd r0 + j.nd r0 + + j.f [r1] + j.d.f [r1] + j.jd.f [r1] + j.nd.f [r1] + + j text_label + jal text_label + jra text_label + jeq text_label + jz text_label + jne text_label + jnz text_label + jpl text_label + jp text_label + jmi text_label + jn text_label + jcs text_label + jc text_label + jlo text_label + jcc text_label + jnc text_label + jhs text_label + jvs text_label + jv text_label + jvc text_label + jnv text_label + jgt text_label + jge text_label + jlt text_label + jle text_label + jhi text_label + jls text_label + jpnz text_label + + j external_text_label + + j 0 diff --git a/gas/testsuite/gas/arc/ld.d b/gas/testsuite/gas/arc/ld.d new file mode 100644 index 00000000000..d6dd0a1a5dd --- /dev/null +++ b/gas/testsuite/gas/arc/ld.d @@ -0,0 +1,30 @@ +#objdump: -dr +#name: ld/lr + +# Test the ld/lr insn. + +.*: +file format elf32-.*arc + +Disassembly of section .text: +00000000 08008000 ld r0,\[r1\] +00000004 00418800 ld r2,\[r3,r4\] +00000008 08a30001 ld r5,\[r6,1\] +0000000c 08e401ff ld r7,\[r8,-1\] +00000010 092500ff ld r9,\[r10,255\] +00000014 09660100 ld r11,\[r12,-256\] +00000018 01a77c00 ld r13,\[r14,256\] +00000020 01e87c00 ld r15,\[r16,-257\] +00000028 023f3800 ld r17,\[305419896,sp\] +00000030 0a7f0000 ld r19,\[0\] + RELOC: 00000034 R_ARC_32 foo +00000038 0a9f0000 ld r20,\[4\] + RELOC: 0000003c R_ARC_32 foo +00000040 081f8400 ldb r0,\[0\] +00000044 081f8800 ldw r0,\[0\] +00000048 081f8200 ld.x r0,\[0\] +0000004c 081f9000 ld.a r0,\[0\] +00000050 081fc000 ld.di r0,\[0\] +00000054 08005600 ldb.x.a.di r0,\[r0\] +00000058 0800a000 lr r0,\[r1\] +0000005c 085fa000 lr r2,\[status\] +00000060 087f2000 lr r3,\[305419896\] diff --git a/gas/testsuite/gas/arc/ld.s b/gas/testsuite/gas/arc/ld.s new file mode 100644 index 00000000000..aa26719df1b --- /dev/null +++ b/gas/testsuite/gas/arc/ld.s @@ -0,0 +1,24 @@ +# ld/lr test + + ld r0,[r1] + ld r2,[r3,r4] + ld r5,[r6,1] + ld r7,[r8,-1] + ld r9,[r10,255] + ld r11,[r12,-256] + ld r13,[r14,256] + ld r15,[r16,-257] + ld r17,[0x12345678,r28] + ld r19,[foo] + ld r20,[foo+4] + + ldb r0,[0] + ldw r0,[0] + ld.x r0,[0] + ld.a r0,[0] + ld.di r0,[0] + ldb.x.a.di r0,[r0] + + lr r0,[r1] + lr r2,[status] + lr r3,[0x12345678] diff --git a/gas/testsuite/gas/arc/math.d b/gas/testsuite/gas/arc/math.d new file mode 100644 index 00000000000..ccb79c5ca77 --- /dev/null +++ b/gas/testsuite/gas/arc/math.d @@ -0,0 +1,78 @@ +#objdump: -dr +#name: @OC@ + +# Test the @OC@ insn. + +.*: +file format elf32-.*arc + +Disassembly of section .text: +00000000 @IC+0@008400 @OC@ r0,r1,r2 +00000004 @IC+3@4db800 @OC@ r26,fp,sp +00000008 @IC+3@af3e00 @OC@ ilink1,ilink2,blink +0000000c @IC+7@5df800 @OC@ r58,r59,lp_count +00000010 @IC+0@00fe00 @OC@ r0,r1,0 +00000014 @IC+0@1f8400 @OC@ r0,0,r2 +00000018 @IC+7@e08400 @OC@ 0,r1,r2 +0000001c @IC+0@00ffff @OC@ r0,r1,-1 +00000020 @IC+0@1f85ff @OC@ r0,-1,r2 +00000024 @IC+7@e085ff @OC@ -1,r1,r2 +00000028 @IC+0@00feff @OC@ r0,r1,255 +0000002c @IC+0@1f84ff @OC@ r0,255,r2 +00000030 @IC+7@e084ff @OC@ 255,r1,r2 +00000034 @IC+0@00ff00 @OC@ r0,r1,-256 +00000038 @IC+0@1f8500 @OC@ r0,-256,r2 +0000003c @IC+7@e08500 @OC@ -256,r1,r2 +00000040 @IC+0@00fc00 @OC@ r0,r1,256 +00000048 @IC+0@1f0400 @OC@ r0,-257,r2 +00000050 @IC+7@c08400 @OC@ 511,r1,r2 +00000058 @IC+0@1f0400 @OC@ r0,1111638594,r2 +00000060 @IC+7@c0fc00 @OC@ 305419896,r1,305419896 +00000068 @IC+0@1ffcff @OC@ r0,255,256 +00000070 @IC+0@1f7eff @OC@ r0,256,255 +00000078 @IC+7@e0fcff @OC@ 255,r1,256 +00000080 @IC+7@ff04ff @OC@ 255,256,r2 +00000088 @IC+7@c0feff @OC@ 256,r1,255 +00000090 @IC+7@df84ff @OC@ 256,255,r2 +00000098 @IC+0@00fc00 @OC@ r0,r1,0 + RELOC: 0000009c R_ARC_32 foo +000000a0 @IC+0@008400 @OC@ r0,r1,r2 +000000a4 @IC+0@620a00 @OC@ r3,r4,r5 +000000a8 @IC+0@c39001 @OC@.eq r6,r7,r8 +000000ac @IC+1@251601 @OC@.eq r9,r10,r11 +000000b0 @IC+1@869c02 @OC@.ne r12,r13,r14 +000000b4 @IC+1@e82202 @OC@.ne r15,r16,r17 +000000b8 @IC+2@49a803 @OC@.p r18,r19,r20 +000000bc @IC+2@ab2e03 @OC@.p r21,r22,r23 +000000c0 @IC+3@0cb404 @OC@.n r24,r25,r26 +000000c4 @IC+3@6e3a04 @OC@.n fp,sp,ilink1 +000000c8 @IC+3@cfc005 @OC@.c ilink2,blink,r32 +000000cc @IC+4@314605 @OC@.c r33,r34,r35 +000000d0 @IC+4@92cc05 @OC@.c r36,r37,r38 +000000d4 @IC+4@f45206 @OC@.nc r39,r40,r41 +000000d8 @IC+5@55d806 @OC@.nc r42,r43,r44 +000000dc @IC+5@b75e06 @OC@.nc r45,r46,r47 +000000e0 @IC+6@18e407 @OC@.v r48,r49,r50 +000000e4 @IC+6@7a6a07 @OC@.v r51,r52,r53 +000000e8 @IC+6@dbf008 @OC@.nv r54,r55,r56 +000000ec @IC+7@3d7608 @OC@.nv r57,r58,r59 +000000f0 @IC+7@9e0009 @OC@.gt lp_count,lp_count,r0 +000000f4 @IC+0@007c0a @OC@.ge r0,r0,0 +000000fc @IC+0@3f020b @OC@.lt r1,1,r1 +00000104 @IC+7@c0840c @OC@.le 2,r1,r2 +0000010c @IC+0@7f060d @OC@.hi r3,3,r3 +00000114 @IC+7@df080e @OC@.ls 4,4,r4 +0000011c @IC+7@c2fc0f @OC@.pnz 5,r5,5 +00000124 @IC+0@008500 @OC@.f r0,r1,r2 +00000128 @IC+0@00fa01 @OC@.f r0,r1,1 +0000012c @IC+0@1e8401 @OC@.f r0,1,r2 +00000130 @IC+7@a08400 @OC@.f 0,r1,r2 +00000134 @IC+0@00fd00 @OC@.f r0,r1,512 +0000013c @IC+0@1f0500 @OC@.f r0,512,r2 +00000144 @IC+7@c08500 @OC@.f 512,r1,r2 +0000014c @IC+0@008501 @OC@.eq.f r0,r1,r2 +00000150 @IC+0@00fd02 @OC@.ne.f r0,r1,0 +00000158 @IC+0@1f050b @OC@.lt.f r0,0,r2 +00000160 @IC+7@c08509 @OC@.gt.f 0,r1,r2 +00000168 @IC+0@00fd0c @OC@.le.f r0,r1,512 +00000170 @IC+0@1f050a @OC@.ge.f r0,512,r2 +00000178 @IC+7@c08504 @OC@.n.f 512,r1,r2 diff --git a/gas/testsuite/gas/arc/math.s b/gas/testsuite/gas/arc/math.s new file mode 100644 index 00000000000..775169a8a50 --- /dev/null +++ b/gas/testsuite/gas/arc/math.s @@ -0,0 +1,89 @@ +# @OC@ test + +# Stay away from operands with duplicate arguments (eg: add r0,r1,r1). +# They will be disassembled as they're macro counterparts (eg: asl r0,r1). + +# reg,reg,reg + @OC@ r0,r1,r2 + @OC@ r26,fp,sp + @OC@ ilink1,ilink2,blink + @OC@ r58,r59,lp_count + +# shimm values + @OC@ r0,r1,0 + @OC@ r0,0,r2 + @OC@ 0,r1,r2 + @OC@ r0,r1,-1 + @OC@ r0,-1,r2 + @OC@ -1,r1,r2 + @OC@ r0,r1,255 + @OC@ r0,255,r2 + @OC@ 255,r1,r2 + @OC@ r0,r1,-256 + @OC@ r0,-256,r2 + @OC@ -256,r1,r2 + +# limm values + @OC@ r0,r1,256 + @OC@ r0,-257,r2 + @OC@ 511,r1,r2 + @OC@ r0,0x42424242,r2 + @OC@ 0x12345678,r1,0x12345678 + +# shimm and limm + @OC@ r0,255,256 + @OC@ r0,256,255 + @OC@ 255,r1,256 + @OC@ 255,256,r2 + @OC@ 256,r1,255 + @OC@ 256,255,r2 + +# symbols + @OC@ r0,r1,foo + +# conditional execution + @OC@.al r0,r1,r2 + @OC@.ra r3,r4,r5 + @OC@.eq r6,r7,r8 + @OC@.z r9,r10,r11 + @OC@.ne r12,r13,r14 + @OC@.nz r15,r16,r17 + @OC@.pl r18,r19,r20 + @OC@.p r21,r22,r23 + @OC@.mi r24,r25,r26 + @OC@.n r27,r28,r29 + @OC@.cs r30,r31,r32 + @OC@.c r33,r34,r35 + @OC@.lo r36,r37,r38 + @OC@.cc r39,r40,r41 + @OC@.nc r42,r43,r44 + @OC@.hs r45,r46,r47 + @OC@.vs r48,r49,r50 + @OC@.v r51,r52,r53 + @OC@.vc r54,r55,r56 + @OC@.nv r57,r58,r59 + @OC@.gt r60,r60,r0 + @OC@.ge r0,r0,0 + @OC@.lt r1,1,r1 + @OC@.le 2,r1,r2 + @OC@.hi r3,3,r3 + @OC@.ls 4,4,r4 + @OC@.pnz 5,r5,5 + +# flag setting + @OC@.f r0,r1,r2 + @OC@.f r0,r1,1 + @OC@.f r0,1,r2 + @OC@.f 0,r1,r2 + @OC@.f r0,r1,512 + @OC@.f r0,512,r2 + @OC@.f 512,r1,r2 + +# conditional execution + flag setting + @OC@.eq.f r0,r1,r2 + @OC@.ne.f r0,r1,0 + @OC@.lt.f r0,0,r2 + @OC@.gt.f 0,r1,r2 + @OC@.le.f r0,r1,512 + @OC@.ge.f r0,512,r2 + @OC@.n.f 512,r1,r2 diff --git a/gas/testsuite/gas/arc/sshift.d b/gas/testsuite/gas/arc/sshift.d new file mode 100644 index 00000000000..c0207a77a4b --- /dev/null +++ b/gas/testsuite/gas/arc/sshift.d @@ -0,0 +1,44 @@ +#objdump: -dr +#name: @OC@ + +# Test the @OC@ insn. + +.*: +file format elf32-.*arc + +Disassembly of section .text: +00000000 1800@I3+80@00 @OC@ r0,r1 +00000004 1b6e@I3+00@00 @OC@ fp,sp +00000008 181f@I3+80@00 @OC@ r0,0 +0000000c 183f@I3+81@ff @OC@ r1,-1 +00000010 1fe1@I3+00@00 @OC@ 0,r2 +00000014 1fe1@I3+81@ff @OC@ -1,r3 +00000018 189f@I3+80@ff @OC@ r4,255 +0000001c 1fe2@I3+80@ff @OC@ 255,r5 +00000020 18df@I3+81@00 @OC@ r6,-256 +00000024 1fe3@I3+81@00 @OC@ -256,r7 +00000028 191f@I3+00@00 @OC@ r8,256 +00000030 193f@I3+00@00 @OC@ r9,-257 +00000038 1fc5@I3+00@00 @OC@ 511,r10 +00000040 197f@I3+00@00 @OC@ r11,1111638594 +00000048 1fc6@I3+00@00 @OC@ 305419896,r12 +00000050 1fff@I3+00@ff @OC@ 255,256 +00000058 1fdf@I3+80@ff @OC@ 256,255 +00000060 181f@I3+00@00 @OC@ r0,0 + RELOC: 00000064 R_ARC_32 foo +00000068 1945@I3+80@01 @OC@.eq r10,r11 +0000006c 1986@I3+80@02 @OC@.ne r12,r13 +00000070 19df@I3+00@0b @OC@.lt r14,0 +00000078 19ff@I3+00@09 @OC@.gt r15,512 +00000080 1800@I3+81@00 @OC@.f r0,r1 +00000084 185e@I3+80@01 @OC@.f r2,1 +00000088 1fa2@I3+00@00 @OC@.f 0,r4 +0000008c 18bf@I3+01@00 @OC@.f r5,512 +00000094 1fc3@I3+01@00 @OC@.f 512,r6 +0000009c 1fdf@I3+01@00 @OC@.f 512,512 +000000a4 1800@I3+81@01 @OC@.eq.f r0,r1 +000000a8 183f@I3+01@02 @OC@.ne.f r1,0 +000000b0 1fc1@I3+01@0b @OC@.lt.f 0,r2 +000000b8 1fc1@I3+01@09 @OC@.gt.f 1,r2 +000000c0 181f@I3+01@0c @OC@.le.f r0,512 +000000c8 1fc1@I3+01@0a @OC@.ge.f 512,r2 +000000d0 1fdf@I3+01@04 @OC@.n.f 512,512 diff --git a/gas/testsuite/gas/arc/sshift.s b/gas/testsuite/gas/arc/sshift.s new file mode 100644 index 00000000000..e2fa661fa5c --- /dev/null +++ b/gas/testsuite/gas/arc/sshift.s @@ -0,0 +1,52 @@ +# Single shift @OC@ test + +# reg,reg + @OC@ r0,r1 + @OC@ fp,sp + +# shimm values + @OC@ r0,0 + @OC@ r1,-1 + @OC@ 0,r2 + @OC@ -1,r3 + @OC@ r4,255 + @OC@ 255,r5 + @OC@ r6,-256 + @OC@ -256,r7 + +# limm values + @OC@ r8,256 + @OC@ r9,-257 + @OC@ 511,r10 + @OC@ r11,0x42424242 + @OC@ 0x12345678,r12 + +# shimm and limm + @OC@ 255,256 + @OC@ 256,255 + +# symbols + @OC@ r0,foo + +# conditional execution + @OC@.eq r10,r11 + @OC@.ne r12,r13 + @OC@.lt r14,0 + @OC@.gt r15,512 + +# flag setting + @OC@.f r0,r1 + @OC@.f r2,1 + @OC@.f 0,r4 + @OC@.f r5,512 + @OC@.f 512,r6 + @OC@.f 512,512 + +# conditional execution + flag setting + @OC@.eq.f r0,r1 + @OC@.ne.f r1,0 + @OC@.lt.f 0,r2 + @OC@.gt.f 1,r2 + @OC@.le.f r0,512 + @OC@.ge.f 512,r2 + @OC@.n.f 512,512 diff --git a/gas/testsuite/gas/arc/st.d b/gas/testsuite/gas/arc/st.d new file mode 100644 index 00000000000..cca99a83394 --- /dev/null +++ b/gas/testsuite/gas/arc/st.d @@ -0,0 +1,25 @@ +#objdump: -dr +#name: st/sr + +# Test the st/sr insn. + +.*: +file format elf32-.*arc + +Disassembly of section .text: +00000000 10008000 st r0,\[r1\] +00000004 10030a01 st r5,\[r6,1\] +00000008 10040fff st r7,\[r8,-1\] +0000000c 100512ff st r9,\[r10,255\] +00000010 10061700 st r11,\[r12,-256\] +00000014 101f2600 st r19,\[0\] + RELOC: 00000018 R_ARC_32 foo +0000001c 101f2800 st r20,\[4\] + RELOC: 00000020 R_ARC_32 foo +00000024 105f0000 stb r0,\[0\] +0000002c 109f0000 stw r0,\[0\] +00000034 111f0000 st.a r0,\[0\] +0000003c 141f0000 st.di r0,\[0\] +00000044 15400000 stb.a.di r0,\[r0\] +00000048 12008000 sr r0,\[r1\] +0000004c 121f8400 sr r2,\[status\] +00000050 121f0600 sr r3,\[305419896\] diff --git a/gas/testsuite/gas/arc/st.s b/gas/testsuite/gas/arc/st.s new file mode 100644 index 00000000000..10af198a787 --- /dev/null +++ b/gas/testsuite/gas/arc/st.s @@ -0,0 +1,19 @@ +# st/sr test + + st r0,[r1] + st r5,[r6,1] + st r7,[r8,-1] + st r9,[r10,255] + st r11,[r12,-256] + st r19,[foo] + st r20,[foo+4] + + stb r0,[0] + stw r0,[0] + st.a r0,[0] + st.di r0,[0] + stb.a.di r0,[r0] + + sr r0,[r1] + sr r2,[status] + sr r3,[0x12345678] diff --git a/gas/testsuite/gas/arc/warn.exp b/gas/testsuite/gas/arc/warn.exp new file mode 100644 index 00000000000..79ff1263d5e --- /dev/null +++ b/gas/testsuite/gas/arc/warn.exp @@ -0,0 +1,13 @@ +# Test assembler warnings. + +if [istarget arc*-*-*] { + + load_lib gas-dg.exp + + dg-init + + dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/warn*.s]] "" "" + + dg-finish + +} diff --git a/gas/testsuite/gas/arc/warn.s b/gas/testsuite/gas/arc/warn.s new file mode 100644 index 00000000000..6fcb43725fa --- /dev/null +++ b/gas/testsuite/gas/arc/warn.s @@ -0,0 +1,14 @@ +; Test ARC specific assembler warnings +; +; { dg-do assemble { target arc-*-* } } + + b.d foo + mov r0,256 ; { dg-warning "8 byte instruction in delay slot" "8 byte insn in delay slot" } + + j.d foo ; { dg-warning "8 byte jump instruction with delay slot" "8 byte jump with delay slot" } + mov r0,r1 + + sub.f 0,r0,r2 + beq foo ; { dg-warning "conditional branch follows set of flags" "cc set/branch nop test" } + +foo: |