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| author | Richard Sandiford <richard.sandiford@arm.com> | 2023-03-30 11:09:18 +0100 |
|---|---|---|
| committer | Richard Sandiford <richard.sandiford@arm.com> | 2023-03-30 11:09:18 +0100 |
| commit | e4cf4736e979fe83920ae8283fbea43764ab11d8 (patch) | |
| tree | f5cafc7511ece7a7f464065a789180b3c7af09d0 /gas/testsuite/gas/aarch64/sme2-22-invalid.l | |
| parent | b368719a5abe41be68ecce97d9015f79326b37c0 (diff) | |
| download | binutils-gdb-e4cf4736e979fe83920ae8283fbea43764ab11d8.tar.gz | |
aarch64: Add the SVE FCLAMP instruction
Diffstat (limited to 'gas/testsuite/gas/aarch64/sme2-22-invalid.l')
| -rw-r--r-- | gas/testsuite/gas/aarch64/sme2-22-invalid.l | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/gas/testsuite/gas/aarch64/sme2-22-invalid.l b/gas/testsuite/gas/aarch64/sme2-22-invalid.l index 85251cd1fee..6f799c1c329 100644 --- a/gas/testsuite/gas/aarch64/sme2-22-invalid.l +++ b/gas/testsuite/gas/aarch64/sme2-22-invalid.l @@ -1,5 +1,5 @@ [^ :]+: Assembler messages: -[^ :]+:[0-9]+: Error: expected '{' at operand 1 -- `fclamp 0,z0\.h,z0\.h' +[^ :]+:[0-9]+: Error: expected a register or register list at operand 1 -- `fclamp 0,z0\.h,z0\.h' [^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `fclamp {z0\.h-z1\.h},0,z0\.h' [^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `fclamp {z0\.h-z1\.h},z0\.h,0' [^ :]+:[0-9]+: Error: operand mismatch -- `fclamp {z0\.b-z1\.b},z0\.b,z0\.b' |