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| author | Richard Sandiford <richard.sandiford@arm.com> | 2023-03-30 11:09:05 +0100 |
|---|---|---|
| committer | Richard Sandiford <richard.sandiford@arm.com> | 2023-03-30 11:09:05 +0100 |
| commit | 7da28504bf86cbdf93965c953979d276db3616d0 (patch) | |
| tree | 0df0f0e1b4635f6a850daf451e817337e43c9576 /gas/testsuite/gas/aarch64/sme-6-illegal.l | |
| parent | 61dac77e931e254a3caeb4d924999e11875308d0 (diff) | |
| download | binutils-gdb-7da28504bf86cbdf93965c953979d276db3616d0.tar.gz | |
aarch64: Move w12-w15 range check to libopcodes
In SME, the vector select register had to be in the range
w12-w15, so it made sense to enforce that during parsing.
However, SME2 adds instructions for which the range is
w8-w11 instead.
This patch therefore moves the range check from the parsing
stage to the constraint-checking stage.
Also, the previous error used a capitalised range W12-W15,
whereas other register range errors used lowercase ranges
like p0-p7. A quick internal poll showed a preference for
the lowercase form, so the patch uses that.
The patch uses "selection register" rather than "vector
select register" so that the terminology extends more
naturally to PSEL.
Diffstat (limited to 'gas/testsuite/gas/aarch64/sme-6-illegal.l')
| -rw-r--r-- | gas/testsuite/gas/aarch64/sme-6-illegal.l | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/gas/testsuite/gas/aarch64/sme-6-illegal.l b/gas/testsuite/gas/aarch64/sme-6-illegal.l index d2a3f3ca09e..b2527ead250 100644 --- a/gas/testsuite/gas/aarch64/sme-6-illegal.l +++ b/gas/testsuite/gas/aarch64/sme-6-illegal.l @@ -1,6 +1,6 @@ [^:]*: Assembler messages: -[^:]*:[0-9]+: Error: expected vector select register W12-W15 at operand 1 -- `st1b {za0h.b\[w11,0\]},p0,\[x0\]' -[^:]*:[0-9]+: Error: expected vector select register W12-W15 at operand 1 -- `st1h {za0h.h\[w16,0\]},p0,\[x0\]' +[^:]*:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 1 -- `st1b {za0h.b\[w11,0\]},p0,\[x0\]' +[^:]*:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 1 -- `st1h {za0h.h\[w16,0\]},p0,\[x0\]' [^:]*:[0-9]+: Error: invalid addressing mode at operand 3 -- `st1h {za0v.h\[w12,0\]},p0,\[x0,x0,lsl#3\]' [^:]*:[0-9]+: Error: '\]' expected at operand 3 -- `st1w {za3v.s\[w15,3\]},p7,\[sp,lsl#2\]' [^:]*:[0-9]+: Error: invalid addressing mode at operand 3 -- `st1d {za0h.d\[w12,0\]},p0,\[sp,x0,lsl#12\]' |