diff options
| author | Sudakshina Das <sudi.das@arm.com> | 2019-04-11 10:19:37 +0100 |
|---|---|---|
| committer | Sudakshina Das <sudi.das@arm.com> | 2019-04-11 10:19:37 +0100 |
| commit | bd7ceb8d26e011ff3fd23402ec2587d7c374f090 (patch) | |
| tree | c840dda3b050e9fdb75bdfd334eb121796c24f5d /gas/testsuite/gas/aarch64/armv8_5-a-memtag.s | |
| parent | e54010f1aeb050cb9d65862a0afe9095a7a85f27 (diff) | |
| download | binutils-gdb-bd7ceb8d26e011ff3fd23402ec2587d7c374f090.tar.gz | |
[BINUTILS, AArch64, 2/2] Update Store Allocation Tag instructions
This patch updates the Store allocation tags instructions in
Armv8.5-A Memory Tagging Extension. This is part of the changes
that have been introduced recently in the 00bet10 release
All of these instructions have an updated register operand (Xt -> <Xt|SP>)
- STG <Xt|SP>, [<Xn|SP>, #<simm>]
- STG <Xt|SP>, [<Xn|SP>, #<simm>]!
- STG <Xt|SP>, [<Xn|SP>], #<simm>
- STZG <Xt|SP>, [<Xn|SP>, #<simm>]
- STZG <Xt|SP>, [<Xn|SP>, #<simm>]!
- STZG <Xt|SP>, [<Xn|SP>], #<simm>
- ST2G <Xt|SP>, [<Xn|SP>, #<simm>]
- ST2G <Xt|SP>, [<Xn|SP>, #<simm>]!
- ST2G <Xt|SP>, [<Xn|SP>], #<simm>
- STZ2G <Xt|SP>, [<Xn|SP>, #<simm>]
- STZ2G <Xt|SP>, [<Xn|SP>, #<simm>]!
- STZ2G <Xt|SP>, [<Xn|SP>], #<simm>
In order to accept <Rt|SP> a new operand type Rt_SP is introduced which has
the same field as FLD_Rt but follows other semantics of Rn_SP.
*** gas/ChangeLog ***
2019-04-11 Sudakshina Das <sudi.das@arm.com>
* config/tc-aarch64.c (process_omitted_operand): Add case for
AARCH64_OPND_Rt_SP.
(parse_operands): Likewise.
* testsuite/gas/aarch64/armv8_5-a-memtag.d: Update tests.
* testsuite/gas/aarch64/armv8_5-a-memtag.s: Likewise.
* testsuite/gas/aarch64/illegal-memtag.l: Likewise.
* testsuite/gas/aarch64/illegal-memtag.s: Likewise.
*** include/ChangeLog ***
2019-04-11 Sudakshina Das <sudi.das@arm.com>
* opcode/aarch64.h (enum aarch64_opnd): Add AARCH64_OPND_Rt_SP.
*** opcodes/ChangeLog ***
2019-04-11 Sudakshina Das <sudi.das@arm.com>
* aarch64-opc.c (aarch64_print_operand): Add case for
AARCH64_OPND_Rt_SP.
(verify_constraints): Likewise.
* aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
(struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
to accept Rt|SP as first operand.
(AARCH64_OPERANDS): Add new Rt_SP.
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Regenerated.
* aarch64-opc-2.c: Regenerated.
Diffstat (limited to 'gas/testsuite/gas/aarch64/armv8_5-a-memtag.s')
| -rw-r--r-- | gas/testsuite/gas/aarch64/armv8_5-a-memtag.s | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/gas/testsuite/gas/aarch64/armv8_5-a-memtag.s b/gas/testsuite/gas/aarch64/armv8_5-a-memtag.s index 50c9962a40e..bd01d73b00a 100644 --- a/gas/testsuite/gas/aarch64/armv8_5-a-memtag.s +++ b/gas/testsuite/gas/aarch64/armv8_5-a-memtag.s @@ -19,19 +19,19 @@ func: .macro expand_stg op \op x0, [x0, #0] \op x0, [x27, #0] - \op xzr, [x0, #0] + \op sp, [x0, #0] \op x27, [x0, #-80] \op x0, [x0, #0]! - \op xzr, [x0, #0]! + \op sp, [x0, #0]! \op x27, [x0, #160]! \op x0, [x0], #0 - \op xzr, [x0], #0 + \op sp, [x0], #0 \op x27, [x0], #-1440 \op x0, [sp, #4080] - \op xzr, [sp, #4080] + \op sp, [sp, #4080] \op x27, [sp, #-4096] \op x0, [sp, #4080]! - \op xzr, [sp], #-4096 + \op sp, [sp], #-4096 .endm .macro expand_ldg_bulk op |