diff options
author | Kazu Hirata <kazu@codesourcery.com> | 2002-05-09 13:12:57 +0000 |
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committer | Kazu Hirata <kazu@codesourcery.com> | 2002-05-09 13:12:57 +0000 |
commit | cc8a6dd09b7219289b0ceac611fc095fcde68153 (patch) | |
tree | 76b90b3715a4615f3d7322fb6df8d94751134f33 /gas/config/tc-d10v.c | |
parent | 2b9c82010f2544589cbc2b0fc435cd308f4cf20a (diff) | |
download | binutils-gdb-cc8a6dd09b7219289b0ceac611fc095fcde68153.tar.gz |
* config/obj-coff.c: Fix formatting.
* config/obj-elf.c: Likewise.
* config/tc-alpha.c: Likewise.
* config/tc-arm.c: Likewise.
* config/tc-d10v.c: Likewise.
* config/tc-d30v.c: Likewise.
* config/tc-h8300.c: Likewise.
* config/tc-hppa.c: Likewise.
Diffstat (limited to 'gas/config/tc-d10v.c')
-rw-r--r-- | gas/config/tc-d10v.c | 90 |
1 files changed, 45 insertions, 45 deletions
diff --git a/gas/config/tc-d10v.c b/gas/config/tc-d10v.c index 73d8e43f1da..6b534095ef5 100644 --- a/gas/config/tc-d10v.c +++ b/gas/config/tc-d10v.c @@ -99,9 +99,9 @@ static int parallel_ok PARAMS ((struct d10v_opcode *opcode1, unsigned long insn1 struct d10v_opcode *opcode2, unsigned long insn2, packing_type exec_type)); -static void check_resource_conflict PARAMS ((struct d10v_opcode *opcode1, - unsigned long insn1, - struct d10v_opcode *opcode2, +static void check_resource_conflict PARAMS ((struct d10v_opcode *opcode1, + unsigned long insn1, + struct d10v_opcode *opcode2, unsigned long insn2)); static symbolS * find_symbol_matching_register PARAMS ((expressionS *)); @@ -670,8 +670,8 @@ build_insn (opcode, opers, insn) insn = insn | (number << shift); } - /* kludge: for DIVS, we need to put the operands in twice on the second - pass, format is changed to LONG_R to force the second set of operands + /* kludge: for DIVS, we need to put the operands in twice on the second + pass, format is changed to LONG_R to force the second set of operands to not be shifted over 15. */ if ((opcode->opcode == OPCODE_DIVS) && (format == LONG_L)) insn = build_insn (opcode, opers, insn); @@ -728,8 +728,8 @@ write_1_short (opcode, insn, fx) if (opcode->exec_type & PARONLY) as_fatal (_("Instruction must be executed in parallel with another instruction.")); - /* The other container needs to be NOP. - According to 4.3.1: for FM=00, sub-instructions performed only by IU + /* The other container needs to be NOP. + According to 4.3.1: for FM=00, sub-instructions performed only by IU cannot be encoded in L-container. */ if (opcode->unit == IU) insn |= FM00 | (NOP << 15); /* Right container. */ @@ -944,7 +944,7 @@ parallel_ok (op1, insn1, op2, insn2, exec_type) /* If this is auto parallization, and either instruction is a branch, don't parallel. */ if (exec_type == PACK_UNSPEC - && (op1->exec_type & (ALONE | BRANCH) + && (op1->exec_type & (ALONE | BRANCH) || op2->exec_type & (ALONE | BRANCH))) return 0; @@ -963,8 +963,8 @@ parallel_ok (op1, insn1, op2, insn2, exec_type) and the second reads the PSW (which includes C, F0, and F1), then they cannot operate safely in parallel. */ - /* The bitmasks (mod and used) look like this (bit 31 = MSB). - r0-r15 0-15 + /* The bitmasks (mod and used) look like this (bit 31 = MSB). + r0-r15 0-15 a0-a1 16-17 cr (not psw) 18 psw 19 @@ -1051,7 +1051,7 @@ parallel_ok (op1, insn1, op2, insn2, exec_type) /* Determine if there are any resource conflicts among two manually parallelized instructions. Some of this was lifted from parallel_ok. */ -static void +static void check_resource_conflict (op1, insn1, op2, insn2) struct d10v_opcode *op1, *op2; unsigned long insn1, insn2; @@ -1127,35 +1127,35 @@ check_resource_conflict (op1, insn1, op2, insn2) if (flags & (OPERAND_ACC0 | OPERAND_ACC1)) regno += 16; else if (flags & OPERAND_CONTROL) /* mvtc or mvfc */ - { + { if (regno == 0) regno = 19; else - regno = 18; + regno = 18; } else if (flags & OPERAND_FFLAG) regno = 22; else if (flags & OPERAND_CFLAG) regno = 21; - - if ( flags & OPERAND_DEST ) + + if ( flags & OPERAND_DEST ) { mod[j] |= 1 << regno; if (flags & OPERAND_EVEN) mod[j] |= 1 << (regno + 1); } - else - { - used[j] |= 1 << regno ; - if (flags & OPERAND_EVEN) - used[j] |= 1 << (regno + 1); - - /* Auto inc/dec also modifies the register. */ - if (op->operands[i+1] != 0 - && (d10v_operands[op->operands[i+1]].flags - & (OPERAND_PLUS | OPERAND_MINUS)) != 0) - mod[j] |= 1 << regno; - } + else + { + used[j] |= 1 << regno ; + if (flags & OPERAND_EVEN) + used[j] |= 1 << (regno + 1); + + /* Auto inc/dec also modifies the register. */ + if (op->operands[i+1] != 0 + && (d10v_operands[op->operands[i+1]].flags + & (OPERAND_PLUS | OPERAND_MINUS)) != 0) + mod[j] |= 1 << regno; + } } else if (flags & OPERAND_ATMINUS) { @@ -1294,7 +1294,7 @@ md_assemble (str) d10v_cleanup (); if (prev_opcode - && (0 == write_2_short (prev_opcode, prev_insn, opcode, insn, extype, + && (0 == write_2_short (prev_opcode, prev_insn, opcode, insn, extype, fixups))) { /* No instructions saved. */ @@ -1520,7 +1520,7 @@ find_opcode (opcode, myops) } match = 0; - + /* Now search the opcode table table for one with operands that matches what we've got. */ while (!match) @@ -1562,19 +1562,19 @@ find_opcode (opcode, myops) break; } - /* Unfortunatly, for the indirect operand in instructions such - as ``ldb r1, @(c,r14)'' this function can be passed - X_op == O_register (because 'c' is a valid register name). - However we cannot just ignore the case when X_op == O_register - but flags & OPERAND_REG is null, so we check to see if a symbol - of the same name as the register exists. If the symbol does - exist, then the parser was unable to distinguish the two cases + /* Unfortunatly, for the indirect operand in instructions such + as ``ldb r1, @(c,r14)'' this function can be passed + X_op == O_register (because 'c' is a valid register name). + However we cannot just ignore the case when X_op == O_register + but flags & OPERAND_REG is null, so we check to see if a symbol + of the same name as the register exists. If the symbol does + exist, then the parser was unable to distinguish the two cases and we fix things here. (Ref: PR14826) */ if (!(flags & OPERAND_REG) && (X_op == O_register)) { symbolS * sym; - + sym = find_symbol_matching_register (& myops[i]); if (sym != NULL) @@ -1672,9 +1672,9 @@ tc_gen_reloc (seg, fixp) if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) reloc->address = fixp->fx_offset; - + reloc->addend = fixp->fx_addnumber; - + return reloc; } @@ -1769,13 +1769,13 @@ md_apply_fix3 (fixP, valP, seg) XXX - Do we have to worry about branches to a symbol + offset ? */ if (fixP->fx_addsy != NULL && S_IS_EXTERN (fixP->fx_addsy) ) - { - segT fseg = S_GET_SEGMENT (fixP->fx_addsy); - segment_info_type *segf = seg_info(fseg); + { + segT fseg = S_GET_SEGMENT (fixP->fx_addsy); + segment_info_type *segf = seg_info(fseg); if ( segf && segf->sym != fixP->fx_addsy) value = 0; - } + } /* Drop through. */ case BFD_RELOC_D10V_18: /* Instruction addresses are always right-shifted by 2. */ @@ -1789,9 +1789,9 @@ md_apply_fix3 (fixP, valP, seg) rep = (struct d10v_opcode *) hash_find (d10v_hash, "rep"); repi = (struct d10v_opcode *) hash_find (d10v_hash, "repi"); if ((insn & FM11) == FM11 - && ((repi != NULL + && ((repi != NULL && (insn & repi->mask) == (unsigned) repi->opcode) - || (rep != NULL + || (rep != NULL && (insn & rep->mask) == (unsigned) rep->opcode)) && value < 4) as_fatal |