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| author | Nelson Chu <nelson.chu@sifive.com> | 2021-06-11 17:23:43 +0800 |
|---|---|---|
| committer | Nelson Chu <nelson.chu@sifive.com> | 2021-06-11 17:34:54 +0800 |
| commit | 28b2963ffb4b55cbe720538040623f5c7ccb0a1b (patch) | |
| tree | f242ee4bdc89e42a734f4160182f7ae02f8427e7 /gas/ChangeLog | |
| parent | 066f8fbede55e781c6241c445e0940f8368d0ef9 (diff) | |
| download | binutils-gdb-28b2963ffb4b55cbe720538040623f5c7ccb0a1b.tar.gz | |
RISC-V: Update the riscv_opts.[rvc|rve] in the riscv_set_arch.
We also need to update the riscv_opts.[rvc|rve] for elf attributes.
Otherwise, the following case will fail,
$ cat cadd.s
.attribute arch, "rv64gc"
c.add a0, a1
$ riscv64-unknown-elf-as cadd.s -o cadd.o
cadd.s: Assembler messages:
cadd.s:2: Error: illegal operands `c.add a0,a1
After applying this patch,
$ riscv64-unknown-elf-as cadd.s -o cadd.o
$ riscv64-unknown-elf-objdump -d cadd.o
cadd.o: file format elf64-littleriscv
Disassembly of section .text:
0000000000000000 <.text>:
0: 952e add a0,a0,a1
...
gas/
* config/tc-riscv.c (riscv_set_arch): Call riscv_set_rvc
and riscv_set_rve both for -march and elf attributes.
(riscv_after_parse_args): Likewise.
Diffstat (limited to 'gas/ChangeLog')
| -rw-r--r-- | gas/ChangeLog | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog index 8ffba29fe76..11693d33182 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,9 @@ +2021-06-11 Nelson Chu <nelson.chu@sifive.com> + + * config/tc-riscv.c (riscv_set_arch): Call riscv_set_rvc + and riscv_set_rve both for -march and elf attributes. + (riscv_after_parse_args): Likewise. + 2021-06-10 Jan Beulich <jbeulich@suse.com> * config/tc-arm.c (do_bfloat_vfma): Rename index to idx. |