ubsan: frv: left shift of negative value

More non-bugs flagged by ubsan, unless you happen to be compiling for
a 1's complement host.

cpu/
	* frv.cpu (f-u12): Multiply rather than left shift signed values.
	(f-label16, f-label24): Likewise.
opcodes/
	* frv-ibld.c: Regenerate.

2 files changed, 9 insertions, 4 deletions

diff --git a/cpu/ChangeLog b/cpu/ChangeLog
index 3e8f019e353..5611cd19e2f 100644
--- a/cpu/ChangeLog
+++ b/cpu/ChangeLog
@@ -1,3 +1,8 @@
+2020-02-01  Alan Modra  <amodra@gmail.com>
+
+	* frv.cpu (f-u12): Multiply rather than left shift signed values.
+	(f-label16, f-label24): Likewise.
+
 2020-01-30  Alan Modra  <amodra@gmail.com>
 
 	* m32c.cpu (f-src32-rn-unprefixed-QI): Shift before inverting.
diff --git a/cpu/frv.cpu b/cpu/frv.cpu
index b6c4f809bd6..cdb169eddc1 100644
--- a/cpu/frv.cpu
+++ b/cpu/frv.cpu
@@ -1984,7 +1984,7 @@
 		(set (ifield f-u12-l) (and (ifield f-u12) #x3f))
 		)
       (sequence () ; extract
-		(set (ifield f-u12) (or (sll (ifield f-u12-h) 6)
+		(set (ifield f-u12) (or (mul (ifield f-u12-h) 64)
 					(ifield f-u12-l)))
 		)
 )
@@ -2016,7 +2016,7 @@
 
 (df  f-label16    "18 bit pc relative signed offset" (PCREL-ADDR) 15 16 INT
      ((value pc) (sra WI (sub WI value pc) (const 2)))
-     ((value pc) (add WI (sll WI value (const 2)) pc))
+     ((value pc) (add WI (mul WI value (const 4)) pc))
 )
 
 (df   f-labelH6   "upper 6  bits of label24"  () 30  6 INT #f #f)
@@ -2034,9 +2034,9 @@
       ; extract
       (sequence ()
 		(set (ifield f-label24)
-		     (add (sll (or (sll (ifield f-labelH6) (const 18))
+		     (add (mul (or (mul (ifield f-labelH6) (sll 1 18))
 				   (ifield f-labelL18))
-			       (const 2))
+			       (const 4))
 			  pc)))
 )