This commit was manufactured by cvs2svn to create branch 'jimb-jimb-ppc64-linux-20030613-branchpoint

ppc64-linux-20030613-branch'.

Sprout from cagney_convert-20030606-branch 2003-06-06 10:04:21 UTC nobody 'This commit was manufactured by cvs2svn to create branch'
Cherrypick from master 2003-06-13 21:56:27 UTC Jim Blandy <jimb@codesourcery.com> '* solib-svr4.c (solib_break_names): Recognize the 64-bit PowerPC':
    COPYING.LIBGLOSS
    ChangeLog
    Makefile.in
    Makefile.tpl
    bfd/ChangeLog
    bfd/Makefile.am
    bfd/Makefile.in
    bfd/archures.c
    bfd/bfd-in2.h
    bfd/config.bfd
    bfd/configure
    bfd/configure.in
    bfd/cpu-h8300.c
    bfd/ecoff.c
    bfd/elf32-h8300.c
    bfd/elf32-mips.c
    bfd/elf64-mips.c
    bfd/elf64-ppc.c
    bfd/elf64-ppc.h
    bfd/elfn32-mips.c
    bfd/elfxx-mips.c
    bfd/elfxx-mips.h
    bfd/opncls.c
    bfd/po/Make-in
    bfd/po/SRC-POTFILES.in
    bfd/section.c
    bfd/version.h
    config.guess
    config.sub
    configure
    configure.in
    cpu/ChangeLog
    cpu/frv.cpu
    cpu/iq10.cpu
    cpu/iq2000.cpu
    cpu/iq2000.opc
    cpu/iq2000m.cpu
    gdb/ChangeLog
    gdb/Makefile.in
    gdb/abug-rom.c
    gdb/acinclude.m4
    gdb/aclocal.m4
    gdb/ada-lang.c
    gdb/alpha-tdep.c
    gdb/arch-utils.c
    gdb/arch-utils.h
    gdb/arm-linux-tdep.c
    gdb/arm-tdep.c
    gdb/avr-tdep.c
    gdb/block.h
    gdb/breakpoint.c
    gdb/buildsym.c
    gdb/charset.c
    gdb/cli/cli-cmds.c
    gdb/cli/cli-decode.c
    gdb/cli/cli-dump.c
    gdb/cli/cli-interp.c
    gdb/cli/cli-script.c
    gdb/coffread.c
    gdb/config.in
    gdb/config/arm/tm-linux.h
    gdb/config/h8300/tm-h8300.h
    gdb/config/m68k/tm-delta68.h
    gdb/config/m68k/tm-m68klynx.h
    gdb/config/m68k/tm-sun3.h
    gdb/config/pa/tm-hppa.h
    gdb/config/pa/tm-hppa64.h
    gdb/config/powerpc/nm-ppc64-linux.h
    gdb/config/powerpc/ppc64-linux.mh
    gdb/config/powerpc/tm-linux.h
    gdb/config/sh/tm-sh.h
    gdb/config/sparc/tm-sparc.h
    gdb/config/vax/tm-vax.h
    gdb/configure
    gdb/configure.host
    gdb/configure.in
    gdb/configure.tgt
    gdb/cp-abi.c
    gdb/cp-namespace.c
    gdb/cp-support.c
    gdb/cp-support.h
    gdb/cpu32bug-rom.c
    gdb/cris-tdep.c
    gdb/d10v-tdep.c
    gdb/dbug-rom.c
    gdb/dbxread.c
    gdb/defs.h
    gdb/dictionary.c
    gdb/dictionary.h
    gdb/dink32-rom.c
    gdb/doc/ChangeLog
    gdb/doc/gdb.texinfo
    gdb/doc/gdbint.texinfo
    gdb/doublest.c
    gdb/dummy-frame.c
    gdb/dwarf2-frame.c
    gdb/dwarf2expr.h
    gdb/dwarf2read.c
    gdb/dwarfread.c
    gdb/elfread.c
    gdb/findvar.c
    gdb/frame-base.c
    gdb/frame-unwind.c
    gdb/frame.c
    gdb/frame.h
    gdb/frv-tdep.c
    gdb/gdb-stabs.h
    gdb/gdbarch.c
    gdb/gdbarch.h
    gdb/gdbarch.sh
    gdb/gdbserver/ChangeLog
    gdb/gdbserver/configure.srv
    gdb/gdbtypes.c
    gdb/gnu-v2-abi.c
    gdb/gnu-v3-abi.c
    gdb/h8300-tdep.c
    gdb/hpacc-abi.c
    gdb/hppa-tdep.c
    gdb/hpread.c
    gdb/i386-interix-tdep.c
    gdb/i386-tdep.c
    gdb/ia64-tdep.c
    gdb/infcall.c
    gdb/infcmd.c
    gdb/inferior.h
    gdb/interps.c
    gdb/interps.h
    gdb/jv-exp.y
    gdb/jv-lang.c
    gdb/linespec.c
    gdb/m68hc11-tdep.c
    gdb/m68k-tdep.c
    gdb/m68klinux-tdep.c
    gdb/macrocmd.c
    gdb/macrotab.c
    gdb/main.c
    gdb/maint.c
    gdb/mcore-tdep.c
    gdb/mdebugread.c
    gdb/memattr.c
    gdb/mi/ChangeLog
    gdb/mi/mi-cmd-stack.c
    gdb/mi/mi-interp.c
    gdb/mi/mi-main.c
    gdb/mi/mi-parse.c
    gdb/mips-tdep.c
    gdb/mips-tdep.h
    gdb/mn10300-tdep.c
    gdb/monitor.c
    gdb/nlm/configure
    gdb/nlm/configure.in
    gdb/ns32k-tdep.c
    gdb/ns32knbsd-tdep.c
    gdb/objc-exp.y
    gdb/objc-lang.c
    gdb/objc-lang.h
    gdb/objfiles.c
    gdb/ocd.c
    gdb/osabi.c
    gdb/p-exp.y
    gdb/p-valprint.c
    gdb/pa64solib.c
    gdb/ppc-bdm.c
    gdb/ppc-linux-nat.c
    gdb/ppc-linux-tdep.c
    gdb/ppcbug-rom.c
    gdb/printcmd.c
    gdb/regcache.c
    gdb/reggroups.c
    gdb/remote-e7000.c
    gdb/remote-est.c
    gdb/remote-fileio.c
    gdb/remote-fileio.h
    gdb/remote-hms.c
    gdb/remote-mips.c
    gdb/remote-rdi.c
    gdb/remote-rdp.c
    gdb/remote.c
    gdb/remote.h
    gdb/rom68k-rom.c
    gdb/rs6000-nat.c
    gdb/rs6000-tdep.c
    gdb/s390-tdep.c
    gdb/sentinel-frame.c
    gdb/ser-e7kpc.c
    gdb/sh-tdep.c
    gdb/sh3-rom.c
    gdb/signals/signals.c
    gdb/solib-legacy.c
    gdb/solib-svr4.c
    gdb/solib.c
    gdb/somread.c
    gdb/sparc-tdep.c
    gdb/stack.c
    gdb/stack.h
    gdb/std-regs.c
    gdb/symfile.c
    gdb/symfile.h
    gdb/symmisc.c
    gdb/symtab.c
    gdb/symtab.h
    gdb/testsuite/ChangeLog
    gdb/testsuite/gdb.base/attach.exp
    gdb/testsuite/gdb.base/fileio.c
    gdb/testsuite/gdb.base/fileio.exp
    gdb/testsuite/gdb.base/float.exp
    gdb/testsuite/gdb.base/gdb_history
    gdb/testsuite/gdb.base/readline.exp
    gdb/testsuite/gdb.base/shreloc.c
    gdb/testsuite/gdb.base/shreloc.exp
    gdb/testsuite/gdb.base/shreloc1.c
    gdb/testsuite/gdb.base/shreloc2.c
    gdb/testsuite/gdb.base/signals.exp
    gdb/testsuite/gdb.c++/Makefile.in
    gdb/testsuite/gdb.c++/ambiguous.cc
    gdb/testsuite/gdb.c++/ambiguous.exp
    gdb/testsuite/gdb.c++/annota2.cc
    gdb/testsuite/gdb.c++/annota2.exp
    gdb/testsuite/gdb.c++/anon-union.cc
    gdb/testsuite/gdb.c++/anon-union.exp
    gdb/testsuite/gdb.c++/casts.cc
    gdb/testsuite/gdb.c++/casts.exp
    gdb/testsuite/gdb.c++/classes.exp
    gdb/testsuite/gdb.c++/cplusfuncs.cc
    gdb/testsuite/gdb.c++/cplusfuncs.exp
    gdb/testsuite/gdb.c++/ctti.exp
    gdb/testsuite/gdb.c++/cttiadd.cc
    gdb/testsuite/gdb.c++/cttiadd1.cc
    gdb/testsuite/gdb.c++/cttiadd2.cc
    gdb/testsuite/gdb.c++/cttiadd3.cc
    gdb/testsuite/gdb.c++/demangle.exp
    gdb/testsuite/gdb.c++/derivation.cc
    gdb/testsuite/gdb.c++/derivation.exp
    gdb/testsuite/gdb.c++/hang.H
    gdb/testsuite/gdb.c++/hang.exp
    gdb/testsuite/gdb.c++/hang1.C
    gdb/testsuite/gdb.c++/hang2.C
    gdb/testsuite/gdb.c++/hang3.C
    gdb/testsuite/gdb.c++/inherit.exp
    gdb/testsuite/gdb.c++/local.cc
    gdb/testsuite/gdb.c++/local.exp
    gdb/testsuite/gdb.c++/m-data.cc
    gdb/testsuite/gdb.c++/m-data.exp
    gdb/testsuite/gdb.c++/m-static.cc
    gdb/testsuite/gdb.c++/m-static.exp
    gdb/testsuite/gdb.c++/m-static.h
    gdb/testsuite/gdb.c++/m-static1.cc
    gdb/testsuite/gdb.c++/maint.exp
    gdb/testsuite/gdb.c++/member-ptr.cc
    gdb/testsuite/gdb.c++/member-ptr.exp
    gdb/testsuite/gdb.c++/method.cc
    gdb/testsuite/gdb.c++/method.exp
    gdb/testsuite/gdb.c++/misc.cc
    gdb/testsuite/gdb.c++/misc.exp
    gdb/testsuite/gdb.c++/namespace.cc
    gdb/testsuite/gdb.c++/namespace.exp
    gdb/testsuite/gdb.c++/namespace1.cc
    gdb/testsuite/gdb.c++/overload.cc
    gdb/testsuite/gdb.c++/overload.exp
    gdb/testsuite/gdb.c++/ovldbreak.cc
    gdb/testsuite/gdb.c++/ovldbreak.exp
    gdb/testsuite/gdb.c++/pr-1023.cc
    gdb/testsuite/gdb.c++/pr-1023.exp
    gdb/testsuite/gdb.c++/pr-574.cc
    gdb/testsuite/gdb.c++/pr-574.exp
    gdb/testsuite/gdb.c++/printmethod.cc
    gdb/testsuite/gdb.c++/printmethod.exp
    gdb/testsuite/gdb.c++/psmang.exp
    gdb/testsuite/gdb.c++/psmang1.cc
    gdb/testsuite/gdb.c++/psmang2.cc
    gdb/testsuite/gdb.c++/ref-types.cc
    gdb/testsuite/gdb.c++/ref-types.exp
    gdb/testsuite/gdb.c++/rtti.exp
    gdb/testsuite/gdb.c++/rtti.h
    gdb/testsuite/gdb.c++/rtti1.cc
    gdb/testsuite/gdb.c++/rtti2.cc
    gdb/testsuite/gdb.c++/templates.cc
    gdb/testsuite/gdb.c++/templates.exp
    gdb/testsuite/gdb.c++/try_catch.cc
    gdb/testsuite/gdb.c++/try_catch.exp
    gdb/testsuite/gdb.c++/userdef.cc
    gdb/testsuite/gdb.c++/userdef.exp
    gdb/testsuite/gdb.c++/virtfunc.cc
    gdb/testsuite/gdb.c++/virtfunc.exp
    gdb/testsuite/gdb.objc/Makefile.in
    gdb/testsuite/gdb.objc/basicclass.exp
    gdb/testsuite/gdb.objc/basicclass.m
    gdb/top.c
    gdb/top.h
    gdb/tracepoint.c
    gdb/trad-frame.c
    gdb/trad-frame.h
    gdb/tui/ChangeLog
    gdb/tui/tui-hooks.c
    gdb/tui/tuiDisassem.c
    gdb/tui/tuiSource.c
    gdb/tui/tuiSourceWin.c
    gdb/tui/tuiStack.c
    gdb/tui/tuiWin.c
    gdb/typeprint.c
    gdb/ui-file.c
    gdb/ui-file.h
    gdb/ui-out.c
    gdb/v850-tdep.c
    gdb/valops.c
    gdb/vax-tdep.c
    gdb/version.in
    gdb/win32-nat.c
    gdb/wince.c
    gdb/x86-64-tdep.c
    gdb/xcoffread.c
    gdb/xstormy16-tdep.c
    include/elf/ChangeLog
    include/elf/common.h
    include/elf/h8.h
    include/gdb/ChangeLog
    include/gdb/fileio.h
    include/opcode/ChangeLog
    include/opcode/h8300.h
    include/opcode/ppc.h
    libiberty/ChangeLog
    libiberty/config.in
    libiberty/configure
    libiberty/configure.in
    libiberty/physmem.c
    opcodes/ChangeLog
    opcodes/Makefile.am
    opcodes/Makefile.in
    opcodes/cgen-asm.in
    opcodes/fr30-asm.c
    opcodes/fr30-desc.c
    opcodes/fr30-desc.h
    opcodes/frv-asm.c
    opcodes/frv-desc.c
    opcodes/frv-desc.h
    opcodes/h8300-dis.c
    opcodes/ip2k-asm.c
    opcodes/ip2k-desc.c
    opcodes/ip2k-desc.h
    opcodes/iq2000-asm.c
    opcodes/iq2000-desc.c
    opcodes/iq2000-desc.h
    opcodes/m32r-asm.c
    opcodes/m32r-desc.c
    opcodes/m32r-desc.h
    opcodes/m32r-opc.c
    opcodes/openrisc-asm.c
    opcodes/openrisc-desc.c
    opcodes/openrisc-desc.h
    opcodes/po/Make-in
    opcodes/po/POTFILES.in
    opcodes/ppc-opc.c
    opcodes/xstormy16-asm.c
    opcodes/xstormy16-desc.c
    opcodes/xstormy16-desc.h
Cherrypick from master 2003-03-19 06:21:14 UTC Kevin Buettner <kevinb@redhat.com> 'Print correct register names for MIPS targets using n32/n64 ABIs.':
    gdb/config/mips/bigmips.mt
    gdb/config/mips/bigmips64.mt
    gdb/config/mips/decstation.mt
    gdb/config/mips/littlemips.mt
    gdb/config/mips/tm-bigmips.h
    gdb/config/mips/tm-bigmips64.h
    gdb/config/mips/tm-embed64.h
    gdb/config/mips/tm-embedl.h
    gdb/config/mips/tm-embedl64.h
    gdb/config/mips/tm-tx39l.h
    gdb/config/mips/tm-vr4100.h
    gdb/config/mips/tm-vr4300.h
    gdb/config/mips/tm-vr4300el.h
    gdb/config/mips/tm-vr4xxx.h
    gdb/config/mips/tm-vr4xxxel.h
    gdb/config/mips/tm-vr5000.h
    gdb/config/mips/tm-vr5000el.h
    gdb/config/mips/vr4100.mt
    gdb/config/mips/vr4300.mt
    gdb/config/mips/vr4300el.mt
    gdb/config/mips/vr4xxx.mt
    gdb/config/mips/vr4xxxel.mt
    gdb/config/mips/vr5000.mt
    gdb/config/mips/vr5000el.mt
Cherrypick from jimb-ppc64-linux-20030528-branch 2003-05-29 23:06:59 UTC Jim Blandy <jimb@codesourcery.com> 'gdb/ChangeLog:':
    gdb/gdbserver/linux-ppc64-low.c
    gdb/regformats/reg-ppc64.dat
Delete:
    sim/testsuite/sim/sh64/ChangeLog
    sim/testsuite/sim/sh64/compact.exp
    sim/testsuite/sim/sh64/compact/ChangeLog
    sim/testsuite/sim/sh64/compact/add.cgs
    sim/testsuite/sim/sh64/compact/addc.cgs
    sim/testsuite/sim/sh64/compact/addi.cgs
    sim/testsuite/sim/sh64/compact/addv.cgs
    sim/testsuite/sim/sh64/compact/and.cgs
    sim/testsuite/sim/sh64/compact/andb.cgs
    sim/testsuite/sim/sh64/compact/andi.cgs
    sim/testsuite/sim/sh64/compact/bf.cgs
    sim/testsuite/sim/sh64/compact/bfs.cgs
    sim/testsuite/sim/sh64/compact/bra.cgs
    sim/testsuite/sim/sh64/compact/braf.cgs
    sim/testsuite/sim/sh64/compact/brk.cgs
    sim/testsuite/sim/sh64/compact/bsr.cgs
    sim/testsuite/sim/sh64/compact/bsrf.cgs
    sim/testsuite/sim/sh64/compact/bt.cgs
    sim/testsuite/sim/sh64/compact/bts.cgs
    sim/testsuite/sim/sh64/compact/clrmac.cgs
    sim/testsuite/sim/sh64/compact/clrs.cgs
    sim/testsuite/sim/sh64/compact/clrt.cgs
    sim/testsuite/sim/sh64/compact/cmpeq.cgs
    sim/testsuite/sim/sh64/compact/cmpeqi.cgs
    sim/testsuite/sim/sh64/compact/cmpge.cgs
    sim/testsuite/sim/sh64/compact/cmpgt.cgs
    sim/testsuite/sim/sh64/compact/cmphi.cgs
    sim/testsuite/sim/sh64/compact/cmphs.cgs
    sim/testsuite/sim/sh64/compact/cmppl.cgs
    sim/testsuite/sim/sh64/compact/cmppz.cgs
    sim/testsuite/sim/sh64/compact/cmpstr.cgs
    sim/testsuite/sim/sh64/compact/div0s.cgs
    sim/testsuite/sim/sh64/compact/div0u.cgs
    sim/testsuite/sim/sh64/compact/div1.cgs
    sim/testsuite/sim/sh64/compact/dmulsl.cgs
    sim/testsuite/sim/sh64/compact/dmulul.cgs
    sim/testsuite/sim/sh64/compact/dt.cgs
    sim/testsuite/sim/sh64/compact/extsb.cgs
    sim/testsuite/sim/sh64/compact/extsw.cgs
    sim/testsuite/sim/sh64/compact/extub.cgs
    sim/testsuite/sim/sh64/compact/extuw.cgs
    sim/testsuite/sim/sh64/compact/fabs.cgs
    sim/testsuite/sim/sh64/compact/fadd.cgs
    sim/testsuite/sim/sh64/compact/fcmpeq.cgs
    sim/testsuite/sim/sh64/compact/fcmpgt.cgs
    sim/testsuite/sim/sh64/compact/fcnvds.cgs
    sim/testsuite/sim/sh64/compact/fcnvsd.cgs
    sim/testsuite/sim/sh64/compact/fdiv.cgs
    sim/testsuite/sim/sh64/compact/fipr.cgs
    sim/testsuite/sim/sh64/compact/fldi0.cgs
    sim/testsuite/sim/sh64/compact/fldi1.cgs
    sim/testsuite/sim/sh64/compact/flds.cgs
    sim/testsuite/sim/sh64/compact/float.cgs
    sim/testsuite/sim/sh64/compact/fmac.cgs
    sim/testsuite/sim/sh64/compact/fmov.cgs
    sim/testsuite/sim/sh64/compact/fmul.cgs
    sim/testsuite/sim/sh64/compact/fneg.cgs
    sim/testsuite/sim/sh64/compact/frchg.cgs
    sim/testsuite/sim/sh64/compact/fschg.cgs
    sim/testsuite/sim/sh64/compact/fsqrt.cgs
    sim/testsuite/sim/sh64/compact/fsts.cgs
    sim/testsuite/sim/sh64/compact/fsub.cgs
    sim/testsuite/sim/sh64/compact/ftrc.cgs
    sim/testsuite/sim/sh64/compact/ftrv.cgs
    sim/testsuite/sim/sh64/compact/jmp.cgs
    sim/testsuite/sim/sh64/compact/jsr.cgs
    sim/testsuite/sim/sh64/compact/ldc-gbr.cgs
    sim/testsuite/sim/sh64/compact/ldcl-gbr.cgs
    sim/testsuite/sim/sh64/compact/lds-fpscr.cgs
    sim/testsuite/sim/sh64/compact/lds-fpul.cgs
    sim/testsuite/sim/sh64/compact/lds-mach.cgs
    sim/testsuite/sim/sh64/compact/lds-macl.cgs
    sim/testsuite/sim/sh64/compact/lds-pr.cgs
    sim/testsuite/sim/sh64/compact/ldsl-fpscr.cgs
    sim/testsuite/sim/sh64/compact/ldsl-fpul.cgs
    sim/testsuite/sim/sh64/compact/ldsl-mach.cgs
    sim/testsuite/sim/sh64/compact/ldsl-macl.cgs
    sim/testsuite/sim/sh64/compact/ldsl-pr.cgs
    sim/testsuite/sim/sh64/compact/macl.cgs
    sim/testsuite/sim/sh64/compact/macw.cgs
    sim/testsuite/sim/sh64/compact/mov.cgs
    sim/testsuite/sim/sh64/compact/mova.cgs
    sim/testsuite/sim/sh64/compact/movb1.cgs
    sim/testsuite/sim/sh64/compact/movb10.cgs
    sim/testsuite/sim/sh64/compact/movb2.cgs
    sim/testsuite/sim/sh64/compact/movb3.cgs
    sim/testsuite/sim/sh64/compact/movb4.cgs
    sim/testsuite/sim/sh64/compact/movb5.cgs
    sim/testsuite/sim/sh64/compact/movb6.cgs
    sim/testsuite/sim/sh64/compact/movb7.cgs
    sim/testsuite/sim/sh64/compact/movb8.cgs
    sim/testsuite/sim/sh64/compact/movb9.cgs
    sim/testsuite/sim/sh64/compact/movcal.cgs
    sim/testsuite/sim/sh64/compact/movi.cgs
    sim/testsuite/sim/sh64/compact/movl1.cgs
    sim/testsuite/sim/sh64/compact/movl10.cgs
    sim/testsuite/sim/sh64/compact/movl11.cgs
    sim/testsuite/sim/sh64/compact/movl2.cgs
    sim/testsuite/sim/sh64/compact/movl3.cgs
    sim/testsuite/sim/sh64/compact/movl4.cgs
    sim/testsuite/sim/sh64/compact/movl5.cgs
    sim/testsuite/sim/sh64/compact/movl6.cgs
    sim/testsuite/sim/sh64/compact/movl7.cgs
    sim/testsuite/sim/sh64/compact/movl8.cgs
    sim/testsuite/sim/sh64/compact/movl9.cgs
    sim/testsuite/sim/sh64/compact/movt.cgs
    sim/testsuite/sim/sh64/compact/movw1.cgs
    sim/testsuite/sim/sh64/compact/movw10.cgs
    sim/testsuite/sim/sh64/compact/movw11.cgs
    sim/testsuite/sim/sh64/compact/movw2.cgs
    sim/testsuite/sim/sh64/compact/movw3.cgs
    sim/testsuite/sim/sh64/compact/movw4.cgs
    sim/testsuite/sim/sh64/compact/movw5.cgs
    sim/testsuite/sim/sh64/compact/movw6.cgs
    sim/testsuite/sim/sh64/compact/movw7.cgs
    sim/testsuite/sim/sh64/compact/movw8.cgs
    sim/testsuite/sim/sh64/compact/movw9.cgs
    sim/testsuite/sim/sh64/compact/mull.cgs
    sim/testsuite/sim/sh64/compact/mulsw.cgs
    sim/testsuite/sim/sh64/compact/muluw.cgs
    sim/testsuite/sim/sh64/compact/neg.cgs
    sim/testsuite/sim/sh64/compact/negc.cgs
    sim/testsuite/sim/sh64/compact/nop.cgs
    sim/testsuite/sim/sh64/compact/not.cgs
    sim/testsuite/sim/sh64/compact/ocbi.cgs
    sim/testsuite/sim/sh64/compact/ocbp.cgs
    sim/testsuite/sim/sh64/compact/ocbwb.cgs
    sim/testsuite/sim/sh64/compact/or.cgs
    sim/testsuite/sim/sh64/compact/orb.cgs
    sim/testsuite/sim/sh64/compact/ori.cgs
    sim/testsuite/sim/sh64/compact/pref.cgs
    sim/testsuite/sim/sh64/compact/rotcl.cgs
    sim/testsuite/sim/sh64/compact/rotcr.cgs
    sim/testsuite/sim/sh64/compact/rotl.cgs
    sim/testsuite/sim/sh64/compact/rotr.cgs
    sim/testsuite/sim/sh64/compact/rts.cgs
    sim/testsuite/sim/sh64/compact/sets.cgs
    sim/testsuite/sim/sh64/compact/sett.cgs
    sim/testsuite/sim/sh64/compact/shad.cgs
    sim/testsuite/sim/sh64/compact/shal.cgs
    sim/testsuite/sim/sh64/compact/shar.cgs
    sim/testsuite/sim/sh64/compact/shld.cgs
    sim/testsuite/sim/sh64/compact/shll.cgs
    sim/testsuite/sim/sh64/compact/shll16.cgs
    sim/testsuite/sim/sh64/compact/shll2.cgs
    sim/testsuite/sim/sh64/compact/shll8.cgs
    sim/testsuite/sim/sh64/compact/shlr.cgs
    sim/testsuite/sim/sh64/compact/shlr16.cgs
    sim/testsuite/sim/sh64/compact/shlr2.cgs
    sim/testsuite/sim/sh64/compact/shlr8.cgs
    sim/testsuite/sim/sh64/compact/stc-gbr.cgs
    sim/testsuite/sim/sh64/compact/stcl-gbr.cgs
    sim/testsuite/sim/sh64/compact/sts-fpscr.cgs
    sim/testsuite/sim/sh64/compact/sts-fpul.cgs
    sim/testsuite/sim/sh64/compact/sts-mach.cgs
    sim/testsuite/sim/sh64/compact/sts-macl.cgs
    sim/testsuite/sim/sh64/compact/sts-pr.cgs
    sim/testsuite/sim/sh64/compact/stsl-fpscr.cgs
    sim/testsuite/sim/sh64/compact/stsl-fpul.cgs
    sim/testsuite/sim/sh64/compact/stsl-mach.cgs
    sim/testsuite/sim/sh64/compact/stsl-macl.cgs
    sim/testsuite/sim/sh64/compact/stsl-pr.cgs
    sim/testsuite/sim/sh64/compact/sub.cgs
    sim/testsuite/sim/sh64/compact/subc.cgs
    sim/testsuite/sim/sh64/compact/subv.cgs
    sim/testsuite/sim/sh64/compact/swapb.cgs
    sim/testsuite/sim/sh64/compact/swapw.cgs
    sim/testsuite/sim/sh64/compact/tasb.cgs
    sim/testsuite/sim/sh64/compact/testutils.inc
    sim/testsuite/sim/sh64/compact/trapa.cgs
    sim/testsuite/sim/sh64/compact/tst.cgs
    sim/testsuite/sim/sh64/compact/tstb.cgs
    sim/testsuite/sim/sh64/compact/tsti.cgs
    sim/testsuite/sim/sh64/compact/xor.cgs
    sim/testsuite/sim/sh64/compact/xorb.cgs
    sim/testsuite/sim/sh64/compact/xori.cgs
    sim/testsuite/sim/sh64/compact/xtrct.cgs
    sim/testsuite/sim/sh64/interwork.exp
    sim/testsuite/sim/sh64/media.exp
    sim/testsuite/sim/sh64/media/ChangeLog
    sim/testsuite/sim/sh64/media/add.cgs
    sim/testsuite/sim/sh64/media/addi.cgs
    sim/testsuite/sim/sh64/media/addil.cgs
    sim/testsuite/sim/sh64/media/addl.cgs
    sim/testsuite/sim/sh64/media/addzl.cgs
    sim/testsuite/sim/sh64/media/alloco.cgs
    sim/testsuite/sim/sh64/media/and.cgs
    sim/testsuite/sim/sh64/media/andc.cgs
    sim/testsuite/sim/sh64/media/andi.cgs
    sim/testsuite/sim/sh64/media/beq.cgs
    sim/testsuite/sim/sh64/media/beqi.cgs
    sim/testsuite/sim/sh64/media/bge.cgs
    sim/testsuite/sim/sh64/media/bgeu.cgs
    sim/testsuite/sim/sh64/media/bgt.cgs
    sim/testsuite/sim/sh64/media/bgtu.cgs
    sim/testsuite/sim/sh64/media/blink.cgs
    sim/testsuite/sim/sh64/media/bne.cgs
    sim/testsuite/sim/sh64/media/bnei.cgs
    sim/testsuite/sim/sh64/media/brk.cgs
    sim/testsuite/sim/sh64/media/byterev.cgs
    sim/testsuite/sim/sh64/media/cmpeq.cgs
    sim/testsuite/sim/sh64/media/cmpgt.cgs
    sim/testsuite/sim/sh64/media/cmpgtu.cgs
    sim/testsuite/sim/sh64/media/cmveq.cgs
    sim/testsuite/sim/sh64/media/cmvne.cgs
    sim/testsuite/sim/sh64/media/fabsd.cgs
    sim/testsuite/sim/sh64/media/fabss.cgs
    sim/testsuite/sim/sh64/media/faddd.cgs
    sim/testsuite/sim/sh64/media/fadds.cgs
    sim/testsuite/sim/sh64/media/fcmpeqd.cgs
    sim/testsuite/sim/sh64/media/fcmpeqs.cgs
    sim/testsuite/sim/sh64/media/fcmpged.cgs
    sim/testsuite/sim/sh64/media/fcmpges.cgs
    sim/testsuite/sim/sh64/media/fcmpgtd.cgs
    sim/testsuite/sim/sh64/media/fcmpgts.cgs
    sim/testsuite/sim/sh64/media/fcmpund.cgs
    sim/testsuite/sim/sh64/media/fcmpuns.cgs
    sim/testsuite/sim/sh64/media/fcnvds.cgs
    sim/testsuite/sim/sh64/media/fcnvsd.cgs
    sim/testsuite/sim/sh64/media/fdivd.cgs
    sim/testsuite/sim/sh64/media/fdivs.cgs
    sim/testsuite/sim/sh64/media/fgetscr.cgs
    sim/testsuite/sim/sh64/media/fiprs.cgs
    sim/testsuite/sim/sh64/media/fldd.cgs
    sim/testsuite/sim/sh64/media/fldp.cgs
    sim/testsuite/sim/sh64/media/flds.cgs
    sim/testsuite/sim/sh64/media/fldxd.cgs
    sim/testsuite/sim/sh64/media/fldxp.cgs
    sim/testsuite/sim/sh64/media/fldxs.cgs
    sim/testsuite/sim/sh64/media/floatld.cgs
    sim/testsuite/sim/sh64/media/floatls.cgs
    sim/testsuite/sim/sh64/media/floatqd.cgs
    sim/testsuite/sim/sh64/media/floatqs.cgs
    sim/testsuite/sim/sh64/media/fmacs.cgs
    sim/testsuite/sim/sh64/media/fmovd.cgs
    sim/testsuite/sim/sh64/media/fmovdq.cgs
    sim/testsuite/sim/sh64/media/fmovls.cgs
    sim/testsuite/sim/sh64/media/fmovqd.cgs
    sim/testsuite/sim/sh64/media/fmovs.cgs
    sim/testsuite/sim/sh64/media/fmovsl.cgs
    sim/testsuite/sim/sh64/media/fmuld.cgs
    sim/testsuite/sim/sh64/media/fmuls.cgs
    sim/testsuite/sim/sh64/media/fnegd.cgs
    sim/testsuite/sim/sh64/media/fnegs.cgs
    sim/testsuite/sim/sh64/media/fputscr.cgs
    sim/testsuite/sim/sh64/media/fsqrtd.cgs
    sim/testsuite/sim/sh64/media/fsqrts.cgs
    sim/testsuite/sim/sh64/media/fstd.cgs
    sim/testsuite/sim/sh64/media/fstp.cgs
    sim/testsuite/sim/sh64/media/fsts.cgs
    sim/testsuite/sim/sh64/media/fstxd.cgs
    sim/testsuite/sim/sh64/media/fstxp.cgs
    sim/testsuite/sim/sh64/media/fstxs.cgs
    sim/testsuite/sim/sh64/media/fsubd.cgs
    sim/testsuite/sim/sh64/media/fsubs.cgs
    sim/testsuite/sim/sh64/media/ftrcdl.cgs
    sim/testsuite/sim/sh64/media/ftrcdq.cgs
    sim/testsuite/sim/sh64/media/ftrcsl.cgs
    sim/testsuite/sim/sh64/media/ftrcsq.cgs
    sim/testsuite/sim/sh64/media/ftrvs.cgs
    sim/testsuite/sim/sh64/media/getcfg.cgs
    sim/testsuite/sim/sh64/media/getcon.cgs
    sim/testsuite/sim/sh64/media/gettr.cgs
    sim/testsuite/sim/sh64/media/icbi.cgs
    sim/testsuite/sim/sh64/media/ldb.cgs
    sim/testsuite/sim/sh64/media/ldhil.cgs
    sim/testsuite/sim/sh64/media/ldhiq.cgs
    sim/testsuite/sim/sh64/media/ldl.cgs
    sim/testsuite/sim/sh64/media/ldlol.cgs
    sim/testsuite/sim/sh64/media/ldloq.cgs
    sim/testsuite/sim/sh64/media/ldq.cgs
    sim/testsuite/sim/sh64/media/ldub.cgs
    sim/testsuite/sim/sh64/media/lduw.cgs
    sim/testsuite/sim/sh64/media/ldw.cgs
    sim/testsuite/sim/sh64/media/ldxb.cgs
    sim/testsuite/sim/sh64/media/ldxl.cgs
    sim/testsuite/sim/sh64/media/ldxq.cgs
    sim/testsuite/sim/sh64/media/ldxub.cgs
    sim/testsuite/sim/sh64/media/ldxuw.cgs
    sim/testsuite/sim/sh64/media/ldxw.cgs
    sim/testsuite/sim/sh64/media/mabsl.cgs
    sim/testsuite/sim/sh64/media/mabsw.cgs
    sim/testsuite/sim/sh64/media/maddl.cgs
    sim/testsuite/sim/sh64/media/maddsl.cgs
    sim/testsuite/sim/sh64/media/maddsub.cgs
    sim/testsuite/sim/sh64/media/maddsw.cgs
    sim/testsuite/sim/sh64/media/maddw.cgs
    sim/testsuite/sim/sh64/media/mcmpeqb.cgs
    sim/testsuite/sim/sh64/media/mcmpeql.cgs
    sim/testsuite/sim/sh64/media/mcmpeqw.cgs
    sim/testsuite/sim/sh64/media/mcmpgtl.cgs
    sim/testsuite/sim/sh64/media/mcmpgtub.cgs
    sim/testsuite/sim/sh64/media/mcmpgtw.cgs
    sim/testsuite/sim/sh64/media/mcmv.cgs
    sim/testsuite/sim/sh64/media/mcnvslw.cgs
    sim/testsuite/sim/sh64/media/mcnvswb.cgs
    sim/testsuite/sim/sh64/media/mcnvswub.cgs
    sim/testsuite/sim/sh64/media/mextr1.cgs
    sim/testsuite/sim/sh64/media/mextr2.cgs
    sim/testsuite/sim/sh64/media/mextr3.cgs
    sim/testsuite/sim/sh64/media/mextr4.cgs
    sim/testsuite/sim/sh64/media/mextr5.cgs
    sim/testsuite/sim/sh64/media/mextr6.cgs
    sim/testsuite/sim/sh64/media/mextr7.cgs
    sim/testsuite/sim/sh64/media/mmacfxwl.cgs
    sim/testsuite/sim/sh64/media/mmacnfx-wl.cgs
    sim/testsuite/sim/sh64/media/mmulfxl.cgs
    sim/testsuite/sim/sh64/media/mmulfxrpw.cgs
    sim/testsuite/sim/sh64/media/mmulfxw.cgs
    sim/testsuite/sim/sh64/media/mmulhiwl.cgs
    sim/testsuite/sim/sh64/media/mmull.cgs
    sim/testsuite/sim/sh64/media/mmullowl.cgs
    sim/testsuite/sim/sh64/media/mmulsumwq.cgs
    sim/testsuite/sim/sh64/media/mmulw.cgs
    sim/testsuite/sim/sh64/media/movi.cgs
    sim/testsuite/sim/sh64/media/mpermw.cgs
    sim/testsuite/sim/sh64/media/msadubq.cgs
    sim/testsuite/sim/sh64/media/mshaldsl.cgs
    sim/testsuite/sim/sh64/media/mshaldsw.cgs
    sim/testsuite/sim/sh64/media/mshardl.cgs
    sim/testsuite/sim/sh64/media/mshardsq.cgs
    sim/testsuite/sim/sh64/media/mshardw.cgs
    sim/testsuite/sim/sh64/media/mshfhib.cgs
    sim/testsuite/sim/sh64/media/mshfhil.cgs
    sim/testsuite/sim/sh64/media/mshfhiw.cgs
    sim/testsuite/sim/sh64/media/mshflob.cgs
    sim/testsuite/sim/sh64/media/mshflol.cgs
    sim/testsuite/sim/sh64/media/mshflow.cgs
    sim/testsuite/sim/sh64/media/mshlldl.cgs
    sim/testsuite/sim/sh64/media/mshlldw.cgs
    sim/testsuite/sim/sh64/media/mshlrdl.cgs
    sim/testsuite/sim/sh64/media/mshlrdw.cgs
    sim/testsuite/sim/sh64/media/msubl.cgs
    sim/testsuite/sim/sh64/media/msubsl.cgs
    sim/testsuite/sim/sh64/media/msubsub.cgs
    sim/testsuite/sim/sh64/media/msubsw.cgs
    sim/testsuite/sim/sh64/media/msubw.cgs
    sim/testsuite/sim/sh64/media/mulsl.cgs
    sim/testsuite/sim/sh64/media/mulul.cgs
    sim/testsuite/sim/sh64/media/nop.cgs
    sim/testsuite/sim/sh64/media/nsb.cgs
    sim/testsuite/sim/sh64/media/ocbi.cgs
    sim/testsuite/sim/sh64/media/ocbp.cgs
    sim/testsuite/sim/sh64/media/ocbwb.cgs
    sim/testsuite/sim/sh64/media/or.cgs
    sim/testsuite/sim/sh64/media/ori.cgs
    sim/testsuite/sim/sh64/media/prefi.cgs
    sim/testsuite/sim/sh64/media/pta.cgs
    sim/testsuite/sim/sh64/media/ptabs.cgs
    sim/testsuite/sim/sh64/media/ptb.cgs
    sim/testsuite/sim/sh64/media/ptrel.cgs
    sim/testsuite/sim/sh64/media/putcfg.cgs
    sim/testsuite/sim/sh64/media/putcon.cgs
    sim/testsuite/sim/sh64/media/rte.cgs
    sim/testsuite/sim/sh64/media/shard.cgs
    sim/testsuite/sim/sh64/media/shardl.cgs
    sim/testsuite/sim/sh64/media/shari.cgs
    sim/testsuite/sim/sh64/media/sharil.cgs
    sim/testsuite/sim/sh64/media/shlld.cgs
    sim/testsuite/sim/sh64/media/shlldl.cgs
    sim/testsuite/sim/sh64/media/shlli.cgs
    sim/testsuite/sim/sh64/media/shllil.cgs
    sim/testsuite/sim/sh64/media/shlrd.cgs
    sim/testsuite/sim/sh64/media/shlrdl.cgs
    sim/testsuite/sim/sh64/media/shlri.cgs
    sim/testsuite/sim/sh64/media/shlril.cgs
    sim/testsuite/sim/sh64/media/shori.cgs
    sim/testsuite/sim/sh64/media/sleep.cgs
    sim/testsuite/sim/sh64/media/stb.cgs
    sim/testsuite/sim/sh64/media/sthil.cgs
    sim/testsuite/sim/sh64/media/sthiq.cgs
    sim/testsuite/sim/sh64/media/stl.cgs
    sim/testsuite/sim/sh64/media/stlol.cgs
    sim/testsuite/sim/sh64/media/stloq.cgs
    sim/testsuite/sim/sh64/media/stq.cgs
    sim/testsuite/sim/sh64/media/stw.cgs
    sim/testsuite/sim/sh64/media/stxb.cgs
    sim/testsuite/sim/sh64/media/stxl.cgs
    sim/testsuite/sim/sh64/media/stxq.cgs
    sim/testsuite/sim/sh64/media/stxw.cgs
    sim/testsuite/sim/sh64/media/sub.cgs
    sim/testsuite/sim/sh64/media/subl.cgs
    sim/testsuite/sim/sh64/media/swapq.cgs
    sim/testsuite/sim/sh64/media/synci.cgs
    sim/testsuite/sim/sh64/media/synco.cgs
    sim/testsuite/sim/sh64/media/testutils.inc
    sim/testsuite/sim/sh64/media/trapa.cgs
    sim/testsuite/sim/sh64/media/xor.cgs
    sim/testsuite/sim/sh64/media/xori.cgs
    sim/testsuite/sim/sh64/misc/fr-dr.s

1 files changed, 1111 insertions, 0 deletions

diff --git a/cpu/iq10.cpu b/cpu/iq10.cpu
new file mode 100644
index 00000000000..322f3ccbe34
--- /dev/null
+++ b/cpu/iq10.cpu
@@ -0,0 +1,1111 @@
+; IQ10-only CPU description. -*- Scheme -*-
+;
+; Copyright 2001, 2002 Free Software Foundation, Inc.
+;
+; Contributed by Red Hat Inc; developed under contract from Vitesse.
+;
+; This file is part of the GNU Binutils.
+;
+; This program is free software; you can redistribute it and/or modify
+; it under the terms of the GNU General Public License as published by
+; the Free Software Foundation; either version 2 of the License, or
+; (at your option) any later version.
+;
+; This program is distributed in the hope that it will be useful,
+; but WITHOUT ANY WARRANTY; without even the implied warranty of
+; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+; GNU General Public License for more details.
+;
+; You should have received a copy of the GNU General Public License
+; along with this program; if not, write to the Free Software
+; Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+
+; Instructions.
+
+(dni andoui-q10 "iq10 and upper ones immediate" (MACH10 USES-RS USES-RT)
+     "andoui $rt,$rs,$hi16"
+     (+ OP10_ANDOUI rs rt hi16)
+     (set rt (and rs (or (sll hi16 16) #xFFFF)))
+     ())
+
+(dni andoui2-q10 "iq10 and upper ones immediate" (ALIAS NO-DIS MACH10 USES-RS USES-RT)
+     "andoui ${rt-rs},$hi16"
+     (+ OP10_ANDOUI rt-rs hi16)
+     (set rt-rs (and rt-rs (or (sll hi16 16) #xFFFF)))
+     ())
+
+(dni orui-q10 "or upper immediate" (MACH10 USES-RS USES-RT)
+     "orui $rt,$rs,$hi16"
+     (+ OP10_ORUI rs rt hi16)
+     (set rt (or rs (sll hi16 16)))
+     ())
+
+(dni orui2-q10 "or upper immediate" (ALIAS NO-DIS MACH10 USES-RS USES-RT)
+     "orui ${rt-rs},$hi16"
+     (+ OP10_ORUI rt-rs hi16)
+     (set rt-rs (or rt-rs (sll hi16 16)))
+     ())
+
+(dni mrgbq10 "merge bytes" (MACH10 USES-RD USES-RS USES-RT)
+     "mrgb $rd,$rs,$rt,$maskq10"
+     (+ OP_SPECIAL rs rt rd maskq10 FUNC_MRGB)
+     (sequence ((SI temp))
+	       (if (bitclear? mask 0)
+		   (set temp (and rs #xFF))
+		   (set temp (and rt #xFF)))
+	       (if (bitclear? mask 1)
+		   (set temp (or temp (and rs #xFF00)))
+		   (set temp (or temp (and rt #xFF00))))
+	       (if (bitclear? mask 2)
+		   (set temp (or temp (and rs #xFF0000)))
+		   (set temp (or temp (and rt #xFF0000))))
+	       (if (bitclear? mask 3)
+		   (set temp (or temp (and rs #xFF000000)))
+		   (set temp (or temp (and rt #xFF000000))))
+	       (set rd temp))
+     ())
+
+(dni mrgbq102 "merge bytes" (ALIAS NO-DIS MACH10 USES-RD USES-RS USES-RT)
+     "mrgb ${rd-rs},$rt,$maskq10"
+     (+ OP_SPECIAL rt rd-rs maskq10 FUNC_MRGB)
+     (sequence ((SI temp))
+	       (if (bitclear? mask 0)
+		   (set temp (and rd-rs #xFF))
+		   (set temp (and rt #xFF)))
+	       (if (bitclear? mask 1)
+		   (set temp (or temp (and rd-rs #xFF00)))
+		   (set temp (or temp (and rt #xFF00))))
+	       (if (bitclear? mask 2)
+		   (set temp (or temp (and rd-rs #xFF0000)))
+		   (set temp (or temp (and rt #xFF0000))))
+	       (if (bitclear? mask 3)
+		   (set temp (or temp (and rd-rs #xFF000000)))
+		   (set temp (or temp (and rt #xFF000000))))
+	       (set rd-rs temp))
+     ())
+
+; In the future, we'll want the j & jal to use the 21 bit target, with 
+; the upper five bits shifted up.  For now, give 'em the 16 bit target.
+
+(dni jq10 "jump" (MACH10)
+     "j $jmptarg"
+     (+ OP_J (f-rs 0) (f-rt 0) jmptarg)
+;     "j $jmptargq10"
+;     (+ OP_J upper-5-jmptargq10 (f-rt 0) lower-16-jmptargq10)
+     (delay 1 (set pc jmptarg))
+     ())
+
+(dni jalq10 "jump and link" (MACH10 USES-RT)
+     "jal $rt,$jmptarg"
+     (+ OP_JAL (f-rs 0) rt jmptarg)
+;     "jal $rt,$jmptargq10"
+;     (+ OP_JAL upper-5-jmptargq10 rt lower-16-jmptargq10)
+     (delay 1
+	    (sequence ()
+		      (set rt (add pc 8))
+		      (set pc jmptarg)))
+     ())
+
+(dni jalq10-2 "jump and link, implied r31" (MACH10 USES-RT)
+     "jal $jmptarg"
+     (+ OP_JAL (f-rs 0) (f-rt 31) jmptarg)
+     (delay 1
+	    (sequence ()
+		      (set rt (add pc 8))
+		      (set pc jmptarg)))
+     ())
+
+; Branch instructions.
+
+(dni bbil "branch bit immediate likely" (MACH10 USES-RS)
+     "bbil $rs($bitnum),$offset"
+     (+ OP10_BBIL rs bitnum offset)
+     (if (bitset? rs bitnum)
+	 (delay 1 (set pc offset))
+	 (skip 1))
+     ())
+
+(dni bbinl "branch bit immediate negated likely" (MACH10 USES-RS)
+     "bbinl $rs($bitnum),$offset"
+     (+ OP10_BBINL rs bitnum offset)
+     (if (bitclear? rs bitnum)
+	 (delay 1 (set pc offset))
+	 (skip 1))
+     ())
+
+(dni bbvl "branch bit variable likely" (MACH10 USES-RS USES-RT)
+     "bbvl $rs,$rt,$offset"
+     (+ OP10_BBVL rs rt offset)
+     (if (bitset? rs (and rt #x1F))
+	 (delay 1 (set pc offset))
+	 (skip 1))
+     ())
+
+(dni bbvnl "branch bit variable negated likely" (MACH10 USES-RS USES-RT)
+     "bbvnl $rs,$rt,$offset"
+     (+ OP10_BBVNL rs rt offset)
+     (if (bitclear? rs (and rt #x1F))
+	 (delay 1 (set pc offset))
+	 (skip 1))
+     ())
+
+(dni bgtzal "branch if greater than zero and link" (MACH10 USES-RS USES-R31)
+     "bgtzal $rs,$offset"
+     (+ OP_REGIMM rs FUNC_BGTZAL offset)
+     (if (gt rs 0)
+	 (sequence ()
+		   (set (reg h-gr 31) (add pc 8))
+		   (delay 1 (set pc offset))))
+     ())
+
+(dni bgtzall
+     "branch if greater than zero and link likely" (MACH10 USES-RS USES-R31)
+     "bgtzall $rs,$offset"
+     (+ OP_REGIMM rs FUNC_BGTZALL offset)
+     (if (gt rs 0)
+	 (sequence ()
+		   (set (reg h-gr 31) (add pc 8))
+		   (delay 1 (set pc offset)))
+	 (skip 1))
+     ())
+
+(dni blezal "branch if less than or equal to zero and link" (MACH10 USES-RS USES-R31)
+     "blezal $rs,$offset"
+     (+ OP_REGIMM rs FUNC_BLEZAL offset)
+     (if (le rs 0)
+	 (sequence ()
+		   (set (reg h-gr 31) (add pc 8))
+		   (delay 1 (set pc offset))))
+     ())
+
+(dni blezall
+     "branch if less than or equal to zero and link likely" (MACH10 USES-RS USES-R31)
+     "blezall $rs,$offset"
+     (+ OP_REGIMM rs FUNC_BLEZALL offset)
+     (if (le rs 0)
+	 (sequence ()
+		   (set (reg h-gr 31) (add pc 8))
+		   (delay 1 (set pc offset)))
+	 (skip 1))
+     ())
+
+(dni bgtz-q10 "branch if greater than zero" (MACH10 USES-RS)
+     "bgtz $rs,$offset"
+     (+ OP_REGIMM rs FUNC_BGTZ offset)
+     (if (gt rs 0)
+	 (delay 1 (set pc offset)))
+     ())
+
+(dni bgtzl-q10 "branch if greater than zero likely" (MACH10 USES-RS)
+     "bgtzl $rs,$offset"
+     (+ OP_REGIMM rs FUNC_BGTZL offset)
+     (if (gt rs 0)
+	 (delay 1 (set pc offset))
+	 (skip 1))
+     ())
+
+
+(dni blez-q10 "branch if less than or equal to zero" (MACH10 USES-RS)
+     "blez $rs,$offset"
+     (+ OP_REGIMM rs FUNC_BLEZ offset)
+     (if (le rs 0)
+	 (delay 1 (set pc offset)))
+     ())
+
+(dni blezl-q10 "branch if less than or equal to zero likely" (MACH10 USES-RS)
+     "blezl $rs,$offset"
+     (+ OP_REGIMM rs FUNC_BLEZL offset)
+     (if (le rs 0)
+	 (delay 1 (set pc offset))
+	 (skip 1))
+     ())
+
+(dni bmb-q10 "branch if matching byte-lane" (MACH10 USES-RS USES-RT)
+     "bmb $rs,$rt,$offset"
+     (+ OP10_BMB rs rt offset)
+     (sequence ((BI branch?))
+	       (set branch? 0)
+	       (if (eq (and rs #xFF) (and rt #xFF))
+		   (set branch? 1))
+	       (if (eq (and rs #xFF00) (and rt #xFF00))
+		   (set branch? 1))
+	       (if (eq (and rs #xFF0000) (and rt #xFF0000))
+		   (set branch? 1))
+	       (if (eq (and rs #xFF000000) (and rt #xFF000000))
+		   (set branch? 1))
+	       (if branch?
+		   (delay 1 (set pc offset))))
+     ())
+
+(dni bmbl "branch if matching byte-lane likely" (MACH10 USES-RS USES-RT)
+     "bmbl $rs,$rt,$offset"
+     (+ OP10_BMBL rs rt offset)
+     (sequence ((BI branch?))
+	       (set branch? 0)
+	       (if (eq (and rs #xFF) (and rt #xFF))
+		   (set branch? 1))
+	       (if (eq (and rs #xFF00) (and rt #xFF00))
+		   (set branch? 1))
+	       (if (eq (and rs #xFF0000) (and rt #xFF0000))
+		   (set branch? 1))
+	       (if (eq (and rs #xFF000000) (and rt #xFF000000))
+		   (set branch? 1))
+	       (if branch?
+		   (delay 1 (set pc offset))
+		   (skip 1)))
+     ())
+
+(dni bri "branch if register invalid" (MACH10 USES-RS)
+     "bri $rs,$offset"
+     (+ OP_REGIMM rs FUNC_BRI offset)
+     (if (gt rs 0)
+	 (delay 1 (set pc offset))
+	 (skip 1))
+     ())
+
+(dni brv "branch if register invalid" (MACH10 USES-RS)
+     "brv $rs,$offset"
+     (+ OP_REGIMM rs FUNC_BRV offset)
+     (if (gt rs 0)
+	 (delay 1 (set pc offset))
+	 (skip 1))
+     ())
+
+; debug instructions
+
+(dni bctx "branch if the current context == instruction[21]" (MACH10 USES-RS)
+     "bctx $rs,$offset"
+     (+ OP_REGIMM rs FUNC_BCTX offset)
+     (delay 1 (set pc offset))
+     ())
+
+(dni yield "unconditional yield to the other context" (MACH10)
+     "yield"
+     (+ OP_SPECIAL (f-rs 0) (f-rt 0) (f-rd 0) (f-shamt 0) FUNC10_YIELD)
+     (unimp yield)
+     ())
+
+; Special instructions.
+
+(dni crc32 "CRC, 32 bit input" (MACH10 USES-RD USES-RS USES-RT)
+     "crc32 $rd,$rs,$rt"
+     (+ OP_COP3 rs rt rd (f-shamt 0) FUNC10_CRC32)
+     (unimp crc32)
+     ())
+
+(dni crc32b "CRC, 8 bit input" (MACH10 USES-RD USES-RS USES-RT)
+     "crc32b $rd,$rs,$rt"
+     (+ OP_COP3 rs rt rd (f-shamt 0) FUNC10_CRC32B)
+     (unimp crc32b)
+     ())
+
+(dni cnt1s "Count ones" (MACH10 USES-RD USES-RS)
+     "cnt1s $rd,$rs"
+     (+ OP_SPECIAL rs rt rd (f-shamt 0) FUNC10_CNT1S)
+     (unimp crcp)
+     ())
+
+
+; Special Instructions
+
+(dni avail "Mark Header Buffer Available" (MACH10 USES-RD)
+     "avail $rd"
+     (+ OP_COP3 (f-rs 0) (f-rt 0) rd (f-shamt 0) FUNC10_AVAIL)
+     (unimp avail)
+     ())
+
+(dni free "Mark Header Buffer Free" (MACH10 USES-RS USES-RD)
+     "free $rd,$rs"
+     (+ OP_COP3 rs (f-rt 0) rd (f-shamt 0) FUNC10_FREE)
+     (unimp free)
+     ())
+
+(dni tstod "Test Header Buffer Order Dependency" (MACH10 USES-RS USES-RD)
+     "tstod $rd,$rs"
+     (+ OP_COP3 rs (f-rt 0) rd (f-shamt 0) FUNC10_TSTOD)
+     (unimp tstod)
+     ())
+
+(dni cmphdr "Get a Complete Header" (MACH10 USES-RD)
+     "cmphdr $rd"
+     (+ OP_COP3 (f-rs 0) (f-rt 0) rd (f-shamt 0) FUNC10_CMPHDR)
+     (unimp cmphdr)
+     ())
+
+(dni mcid "Allocate a Multicast ID" (MACH10 USES-RD USES-RT)
+     "mcid $rd,$rt"
+     (+ OP_COP3 (f-rs 0) rt rd (f-shamt 0) FUNC10_MCID)
+     (unimp mcid)
+     ())
+
+(dni dba "Allocate a Data Buffer Pointer" (MACH10 USES-RD)
+     "dba $rd"
+     (+ OP_COP3 (f-rs 0) (f-rt 0) rd (f-shamt 0) FUNC10_DBA)
+     (unimp dba)
+     ())
+
+(dni dbd "Deallocate a Data Buffer Pointer" (MACH10 USES-RS USES-RT USES-RD)
+     "dbd $rd,$rs,$rt"
+     (+ OP_COP3 rs rt rd (f-shamt 0) FUNC10_DBD)
+     (unimp dbd)
+     ())
+
+(dni dpwt "DSTN_PORT Write" (MACH10 USES-RS USES-RD)
+     "dpwt $rd,$rs"
+     (+ OP_COP3 rs (f-rt 0) rd (f-shamt 0) FUNC10_DPWT)
+     (unimp dpwt)
+     ())
+
+; Architectural and coprocessor instructions.
+
+(dni chkhdrq10 "" (MACH10 USES-RS USES-RD)
+     "chkhdr $rd,$rs"
+     (+ OP_COP3 rs (f-rt 0) rd (f-shamt 0) FUNC10_CHKHDR)
+     (unimp chkhdr)
+     ())
+
+; Coprocessor DMA Instructions (IQ10)
+
+(dni rba "Read Bytes Absolute" (MACH10 USES-RS USES-RT USES-RD)
+     "rba $rd,$rs,$rt"
+     (+ OP_COP3 rs rt rd (f-shamt 0) FUNC10_RBA)
+     (unimp rba)
+     ())
+
+(dni rbal "Read Bytes Absolute and Lock" (MACH10 USES-RS USES-RT USES-RD)
+     "rbal $rd,$rs,$rt"
+     (+ OP_COP3 rs rt rd (f-shamt 0) FUNC10_RBAL)
+     (unimp rbal)
+     ())
+
+(dni rbar "Read Bytes Absolute and Release" (MACH10 USES-RS USES-RT USES-RD)
+     "rbar $rd,$rs,$rt"
+     (+ OP_COP3 rs rt rd (f-shamt 0) FUNC10_RBAR)
+     (unimp rbar)
+     ())
+
+(dni wba "Write Bytes Absolute" (MACH10 USES-RS USES-RT USES-RD)
+     "wba $rd,$rs,$rt"
+     (+ OP_COP3 rs rt rd (f-shamt 0) FUNC10_WBA)
+     (unimp wba)
+     ())
+
+(dni wbau "Write Bytes Absolute and Unlock" (MACH10 USES-RS USES-RT USES-RD)
+     "wbau $rd,$rs,$rt"
+     (+ OP_COP3 rs rt rd (f-shamt 0) FUNC10_WBAU)
+     (unimp wbau)
+     ())
+
+(dni wbac "Write Bytes Absolute Cacheable" (MACH10 USES-RS USES-RT USES-RD)
+     "wbac $rd,$rs,$rt"
+     (+ OP_COP3 rs rt rd (f-shamt 0) FUNC10_WBAC)
+     (unimp wbac)
+     ())
+
+(dni rbi "Read Bytes Immediate" (MACH10 USES-RD USES-RS USES-RT)
+     "rbi $rd,$rs,$rt,$bytecount"
+     (+ OP_COP3 rs rt rd FUNC10_RBI bytecount)
+     (unimp rbi)
+     ())
+
+(dni rbil "Read Bytes Immediate and Lock" (MACH10 USES-RD USES-RS USES-RT)
+     "rbil $rd,$rs,$rt,$bytecount"
+     (+ OP_COP3 rs rt rd FUNC10_RBIL bytecount)
+     (unimp rbil)
+     ())
+
+(dni rbir "Read Bytes Immediate and Release" (MACH10 USES-RD USES-RS USES-RT)
+     "rbir $rd,$rs,$rt,$bytecount"
+     (+ OP_COP3 rs rt rd FUNC10_RBIR bytecount)
+     (unimp rbir)
+     ())
+
+(dni wbi "Write Bytes Immediate" (MACH10 USES-RD USES-RS USES-RT)
+     "wbi $rd,$rs,$rt,$bytecount"
+     (+ OP_COP3 rs rt rd FUNC10_WBI bytecount)
+     (unimp wbi)
+     ())
+
+(dni wbic "Write Bytes Immediate Cacheable" (MACH10 USES-RD USES-RS USES-RT)
+     "wbic $rd,$rs,$rt,$bytecount"
+     (+ OP_COP3 rs rt rd FUNC10_WBIC bytecount)
+     (unimp wbic)
+     ())
+
+(dni wbiu "Write Bytes Immediate" (MACH10 USES-RD USES-RS USES-RT)
+     "wbiu $rd,$rs,$rt,$bytecount"
+     (+ OP_COP3 rs rt rd FUNC10_WBIU bytecount)
+     (unimp wbiu)
+     ())
+
+(dni pkrli "Packet Release Immediate" (MACH10 USES-RD USES-RS USES-RT)
+     "pkrli $rd,$rs,$rt,$bytecount"
+     (+ OP_COP2 rs rt rd FUNC10_PKRLI bytecount)
+     (unimp pkrli)
+     ())
+
+(dni pkrlih "Packet Release Immediate and Hold" (MACH10 USES-RD USES-RS USES-RT)
+     "pkrlih $rd,$rs,$rt,$bytecount"
+     (+ OP_COP2 rs rt rd FUNC10_PKRLIH bytecount)
+     (unimp pkrlih)
+     ())
+
+(dni pkrliu "Packet Release Immediate Unconditional" (MACH10 USES-RD USES-RS USES-RT)
+     "pkrliu $rd,$rs,$rt,$bytecount"
+     (+ OP_COP2 rs rt rd FUNC10_PKRLIU bytecount)
+     (unimp pkrliu)
+     ())
+
+(dni pkrlic "Packet Release Immediate Continue" (MACH10 USES-RD USES-RS USES-RT)
+     "pkrlic $rd,$rs,$rt,$bytecount"
+     (+ OP_COP2 rs rt rd FUNC10_PKRLIC bytecount)
+     (unimp pkrlic)
+     ())
+
+(dni pkrla "Packet Release Absolute" (MACH10 USES-RS USES-RT USES-RD)
+     "pkrla $rd,$rs,$rt"
+     (+ OP_COP3 rs rt rd (f-shamt 0) FUNC10_PKRLA)
+     (unimp pkrla)
+     ())
+
+(dni pkrlau "Packet Release Absolute Unconditional" (MACH10 USES-RS USES-RT USES-RD)
+     "pkrlau $rd,$rs,$rt"
+     (+ OP_COP3 rs rt rd (f-shamt 0) FUNC10_PKRLAU)
+     (unimp pkrlau)
+     ())
+
+(dni pkrlah "Packet Release Absolute and Hold" (MACH10 USES-RS USES-RT USES-RD)
+     "pkrlah $rd,$rs,$rt"
+     (+ OP_COP3 rs rt rd (f-shamt 0) FUNC10_PKRLAH)
+     (unimp pkrlah)
+     ())
+
+(dni pkrlac "Packet Release Absolute Continue" (MACH10 USES-RS USES-RT USES-RD)
+     "pkrlac $rd,$rs,$rt"
+     (+ OP_COP3 rs rt rd (f-shamt 0) FUNC10_PKRLAC)
+     (unimp pkrlac)
+     ())
+
+; Main Memory Access Instructions
+
+(dni lock "lock memory" (MACH10 USES-RD USES-RT)
+     "lock $rd,$rt"
+     (+ OP_COP3 (f-rs 0) rt rd (f-shamt 0) FUNC10_LOCK)
+     (unimp lock)
+     ())
+
+(dni unlk "unlock memory" (MACH10 USES-RT USES-RD)
+     "unlk $rd,$rt"
+     (+ OP_COP3 (f-rs 0) rt rd (f-shamt 0) FUNC10_UNLK)
+     (unimp unlk)
+     ())
+     
+(dni swrd "Single Word Read" (MACH10 USES-RT USES-RD)
+     "swrd $rd,$rt"
+     (+ OP_COP3 (f-rs 0) rt rd (f-shamt 0) FUNC10_SWRD)
+     (unimp swrd)
+     ())
+
+(dni swrdl "Single Word Read and Lock" (MACH10 USES-RT USES-RD)
+     "swrdl $rd,$rt"
+     (+ OP_COP3 (f-rs 0) rt rd (f-shamt 0) FUNC10_SWRDL)
+     (unimp swrdl)
+     ())
+
+(dni swwr "Single Word Write" (MACH10 USES-RS USES-RT USES-RD)
+     "swwr $rd,$rs,$rt"
+     (+ OP_COP3 rs rt rd (f-shamt 0) FUNC10_SWWR)
+     (unimp swwr)
+     ())
+
+(dni swwru "Single Word Write and Unlock" (MACH10 USES-RS USES-RT USES-RD)
+     "swwru $rd,$rs,$rt"
+     (+ OP_COP3 rs rt rd (f-shamt 0) FUNC10_SWWRU)
+     (unimp swwru)
+     ())
+
+(dni dwrd "Double Word Read" (MACH10 EVEN-REG-NUM USES-RT USES-RD)
+     "dwrd $rd,$rt"
+     (+ OP_COP3 (f-rs 0) rt rd (f-shamt 0) FUNC10_DWRD)
+     (unimp dwrd)
+     ())
+
+(dni dwrdl "Double Word Read and Lock" (MACH10 EVEN-REG-NUM USES-RT USES-RD)
+     "dwrdl $rd,$rt"
+     (+ OP_COP3 (f-rs 0) rt rd (f-shamt 0) FUNC10_DWRDL)
+     (unimp dwrdl)
+     ())
+
+; CAM access instructions (IQ10)
+
+(dni cam36 "CAM Access in 36-bit Mode" (MACH10 USES-RT USES-RD)
+     "cam36 $rd,$rt,${cam-z},${cam-y}"
+     (+ OP_COP3 (f-rs 0) rt rd FUNC10_CAM36 cam-z cam-y)
+     (unimp cam36)
+     ())
+
+(dni cam72 "CAM Access in 72-bit Mode" (MACH10 USES-RT USES-RD)
+     "cam72 $rd,$rt,${cam-y},${cam-z}"
+     (+ OP_COP3 (f-rs 0) rt rd FUNC10_CAM72 cam-z cam-y)
+     (unimp cam72)
+     ())
+
+(dni cam144 "CAM Access in 144-bit Mode" (MACH10 USES-RT USES-RD)
+     "cam144 $rd,$rt,${cam-y},${cam-z}"
+     (+ OP_COP3 (f-rs 0) rt rd FUNC10_CAM144 cam-z cam-y)
+     (unimp cam144)
+     ())
+
+(dni cam288 "CAM Access in 288-bit Mode" (MACH10 USES-RT USES-RD)
+     "cam288 $rd,$rt,${cam-y},${cam-z}"
+     (+ OP_COP3 (f-rs 0) rt rd FUNC10_CAM288 cam-z cam-y)
+     (unimp cam288)
+     ())
+
+; Counter manager instructions (IQ10)
+
+(dni cm32and "Counter Manager And" (MACH10 USES-RS USES-RT USES-RD)
+     "cm32and $rd,$rs,$rt"
+     (+ OP_COP3 rs rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM32AND)
+     (unimp cm32and)
+     ())
+
+(dni cm32andn "Counter Manager And With Inverse" (MACH10 USES-RS USES-RT USES-RD)
+     "cm32andn $rd,$rs,$rt"
+     (+ OP_COP3 rs rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM32ANDN)
+     (unimp cm32andn)
+     ())
+
+(dni cm32or "Counter Manager Or" (MACH10 USES-RS USES-RT USES-RD)
+     "cm32or $rd,$rs,$rt"
+     (+ OP_COP3 rs rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM32OR)
+     (unimp cm32or)
+     ())
+
+(dni cm32ra "Counter Manager 32-bit Rolling Add" (MACH10 USES-RS USES-RT USES-RD)
+     "cm32ra $rd,$rs,$rt"
+     (+ OP_COP3 rs rt rd (f-shamt 2) FUNC10_CM32RA)
+     (unimp cm32ra)
+     ())
+
+(dni cm32rd "Counter Manager 32-bit Rolling Decrement" (MACH10 USES-RT USES-RD)
+     "cm32rd $rd,$rt"
+     (+ OP_COP3 (f-rs 0) rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM32RD)
+     (unimp cm32rd)
+     ())
+
+(dni cm32ri "Counter Manager 32-bit Rolling Increment" (MACH10 USES-RT USES-RD)
+     "cm32ri $rd,$rt"
+     (+ OP_COP3 (f-rs 0) rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM32RI)
+     (unimp cm32ri)
+     ())
+
+(dni cm32rs "Counter Manager 32-bit Rolling Subtract" (MACH10 USES-RS USES-RT USES-RD)
+     "cm32rs $rd,$rs,$rt"
+     (+ OP_COP3 rs rt rd (f-shamt 2) FUNC10_CM32RS)
+     (unimp cm32rs)
+     ())
+
+(dni cm32sa "Counter Manager 32-bit Saturating Add" (MACH10 USES-RS USES-RT USES-RD)
+     "cm32sa $rd,$rs,$rt"
+     (+ OP_COP3 rs rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM32SA)
+     (unimp cm32sa)
+     ())
+
+(dni cm32sd "Counter Manager 32-bit Saturating Decrement" (MACH10 USES-RT USES-RD)
+     "cm32sd $rd,$rt"
+     (+ OP_COP3 (f-rs 0) rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM32SD)
+     (unimp cm32sd)
+     ())
+
+(dni cm32si "Counter Manager 32-bit Saturating Increment" (MACH10 USES-RT USES-RD)
+     "cm32si $rd,$rt"
+     (+ OP_COP3 (f-rs 0) rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM32SI)
+     (unimp cm32si)
+     ())
+
+(dni cm32ss "Counter Manager 32-bit Saturating Subtract" (MACH10 USES-RS USES-RT USES-RD)
+     "cm32ss $rd,$rs,$rt"
+     (+ OP_COP3 rs rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM32SS)
+     (unimp cm32ss)
+     ())
+
+(dni cm32xor "Counter Manager Xor" (MACH10 USES-RS USES-RT USES-RD)
+     "cm32xor $rd,$rs,$rt"
+     (+ OP_COP3 rs rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM32XOR)
+     (unimp cm32xor)
+     ())
+
+(dni cm64clr "Counter Manager Clear" (MACH10 EVEN-REG-NUM USES-RT USES-RD)
+     "cm64clr $rd,$rt"
+     (+ OP_COP3 (f-rs 0) rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM64CLR)
+     (unimp cm64clr)
+     ())
+
+(dni cm64ra "Counter Manager 64-bit Rolling Add" (MACH10 EVEN-REG-NUM USES-RS USES-RT USES-RD)
+     "cm64ra $rd,$rs,$rt"
+     (+ OP_COP3 rs rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM64RA)
+     (unimp cm64ra)
+     ())
+
+(dni cm64rd "Counter Manager 64-bit Rolling Decrement" (MACH10 EVEN-REG-NUM USES-RT USES-RD)
+     "cm64rd $rd,$rt"
+     (+ OP_COP3 (f-rs 0) rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM64RD)
+     (unimp cm64rd)
+     ())
+
+(dni cm64ri "Counter Manager 32-bit Rolling Increment" (MACH10 EVEN-REG-NUM USES-RT USES-RD)
+     "cm64ri $rd,$rt"
+     (+ OP_COP3 (f-rs 0) rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM64RI)
+     (unimp cm64ri)
+     ())
+
+(dni cm64ria2 "Counter Manager 32/32 Rolling Increment/Add" (MACH10 EVEN-REG-NUM USES-RS USES-RT USES-RD)
+     "cm64ria2 $rd,$rs,$rt"
+     (+ OP_COP3 rs rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM64RIA2)
+     (unimp cm64ria2)
+     ())
+
+(dni cm64rs "Counter Manager 64-bit Rolling Subtract" (MACH10 EVEN-REG-NUM USES-RS USES-RT USES-RD)
+     "cm64rs $rd,$rs,$rt"
+     (+ OP_COP3 rs rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM64RS)
+     (unimp cm64rs)
+     ())
+
+(dni cm64sa "Counter Manager 64-bit Saturating Add" (MACH10 EVEN-REG-NUM USES-RS USES-RT USES-RD)
+     "cm64sa $rd,$rs,$rt"
+     (+ OP_COP3 rs rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM64SA)
+     (unimp cm64sa)
+     ())
+
+(dni cm64sd "Counter Manager 64-bit Saturating Decrement" (MACH10 EVEN-REG-NUM USES-RT USES-RD)
+     "cm64sd $rd,$rt"
+     (+ OP_COP3 (f-rs 0) rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM64SD)
+     (unimp cm64sd)
+     ())
+
+(dni cm64si "Counter Manager 64-bit Saturating Increment" (MACH10 EVEN-REG-NUM USES-RT USES-RD)
+     "cm64si $rd,$rt"
+     (+ OP_COP3 (f-rs 0) rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM64SI)
+     (unimp cm64si)
+     ())
+
+(dni cm64sia2 "Counter Manager 32/32 Saturating Increment/Add" (MACH10 EVEN-REG-NUM USES-RS USES-RT USES-RD)
+     "cm64sia2 $rd,$rs,$rt"
+     (+ OP_COP3 rs rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM64SIA2)
+     (unimp cm64sia2)
+     ())
+
+(dni cm64ss "Counter Manager 64-bit Saturating Subtract" (MACH10 EVEN-REG-NUM USES-RS USES-RT USES-RD)
+     "cm64ss $rd,$rs,$rt"
+     (+ OP_COP3 rs rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM64SS)
+     (unimp cm64ss)
+     ())
+
+(dni cm128ria2 "Counter Manager 128-bit 64/64 Rolling Increment/Add" (MACH10 EVEN-REG-NUM USES-RS USES-RT USES-RD)
+     "cm128ria2 $rd,$rs,$rt"
+     (+ OP_COP3 rs rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM128RIA2)
+     (unimp cm128ria2)
+     ())
+
+(dni cm128ria3 "Counter Manager 128-bit 32/32/64 Rolling Increment/Add" (MACH10 EVEN-REG-NUM USES-RS USES-RT USES-RD)
+     "cm128ria3 $rd,$rs,$rt,${cm-3z}"
+     (+ OP_COP3 rs rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM128RIA3 cm-3z)
+     (unimp cm128ria3)
+     ())
+
+(dni cm128ria4 "Counter Manager 128-bit 32/32/32/32 Rolling Inc/Add" (MACH10 USES-RS USES-RT USES-RD)
+     "cm128ria4 $rd,$rs,$rt,${cm-4z}"
+     (+ OP_COP3 rs rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM128RIA4 cm-4z)
+     (unimp cm128ria4)
+     ())
+
+(dni cm128sia2 "Counter Manager 128-bit 64/64 Saturating Inc/Add" (MACH10 EVEN-REG-NUM USES-RS USES-RT USES-RD)
+     "cm128sia2 $rd,$rs,$rt"
+     (+ OP_COP3 rs rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM128SIA2)
+     (unimp cm128sia2)
+     ())
+
+(dni cm128sia3 "Counter Manager 128-bit 32/32/64 Saturating Inc/Add" (MACH10 EVEN-REG-NUM USES-RS USES-RT USES-RD)
+     "cm128sia3 $rd,$rs,$rt,${cm-3z}"
+     (+ OP_COP3 rs rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM128SIA3 cm-3z)
+     (unimp cm128sia3)
+     ())
+
+(dni cm128sia4 "Counter Manager 128-bit 32/32/32/32 Saturating Inc/Add" (MACH10 USES-RS USES-RT USES-RD)
+     "cm128sia4 $rd,$rs,$rt,${cm-4z}"
+     (+ OP_COP3 rs rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM128SIA4 cm-4z)
+     (unimp cm128sia4)
+     ())
+
+(dni cm128vsa "Counter Manager Continuous State Dual Leaky Token Bucket Policing" (MACH10 USES-RS USES-RT USES-RD)
+     "cm128vsa $rd,$rs,$rt"
+     (+ OP_COP3 rs rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM128VSA)
+     (unimp cm128vsa)
+     ())
+
+; Coprocessor Data Movement Instructions
+
+; Note that we don't set the USES-RD or USES-RT attributes for many of the following 
+; instructions, as it's the COP register that's being specified.
+
+; ??? Is YIELD-INSN the right attribute for IQ10?  The IQ2000 used the attribute to warn about 
+; yielding instructions in a delay slot, but that's not relevant in IQ10.  What *is* relevant 
+; (and unique to IQ10) is instructions that yield if the destination register is accessed 
+; before the value is there, causing a yield.
+
+(dni cfc "copy from coprocessor control register" (MACH10 LOAD-DELAY USES-RD YIELD-INSN)
+     "cfc $rd,$rt"
+     (+ OP_COP3 (f-rs 0) rt rd (f-shamt 0) FUNC10_CFC)
+     (unimp cfc)
+     ())
+
+(dni ctc "copy to coprocessor control register" (MACH10 USES-RS)
+     "ctc $rs,$rt"
+     (+ OP_COP3 rs rt (f-rd 0) (f-shamt 0) FUNC10_CTC)
+     (unimp ctc)
+     ())
+
+; Macros
+
+(dnmi m-avail "Mark Header Buffer Available" (MACH10 NO-DIS)
+     "avail"
+     (emit avail (f-rd 0))
+)
+
+(dnmi m-cam36 "CAM Access in 36-bit Mode" (MACH10 USES-RT USES-RD NO-DIS)
+     "cam36 $rd,$rt,${cam-z}"
+     (emit cam36 rd rt cam-z (f-cam-y 0))
+)
+
+(dnmi m-cam72 "CAM Access in 72-bit Mode" (MACH10 USES-RT USES-RD NO-DIS)
+     "cam72 $rd,$rt,${cam-z}"
+     (emit cam72 rd rt cam-z (f-cam-y 0))
+)
+
+(dnmi m-cam144 "CAM Access in 144-bit Mode" (MACH10 USES-RT USES-RD NO-DIS)
+     "cam144 $rd,$rt,${cam-z}"
+     (emit cam144 rd rt cam-z (f-cam-y 0))
+)
+
+(dnmi m-cam288 "CAM Access in 288-bit Mode" (MACH10 USES-RT USES-RD NO-DIS)
+     "cam288 $rd,$rt,${cam-z}"
+     (emit cam288 rd rt cam-z (f-cam-y 0))
+)
+
+(dnmi m-cm32read "Counter Manager 32-bit Rolling Add R0" (MACH10 USES-RT USES-RD NO-DIS)
+     "cm32read $rd,$rt"
+     (emit cm32ra rd (f-rs 0) rt)
+)
+
+(dnmi m-cm64read "Counter Manager 64-bit Rolling Add R0" (MACH10 USES-RT USES-RD NO-DIS)
+     "cm64read $rd,$rt"
+     (emit cm64ra rd (f-rs 0) rt)
+)
+
+(dnmi m-cm32mlog "Counter Manager 32-bit or R0" (MACH10 USES-RS USES-RT NO-DIS)
+     "cm32mlog $rs,$rt"
+     (emit cm32or (f-rd 0) rs rt)
+)
+
+(dnmi m-cm32and "Counter Manager And" (MACH10 USES-RS USES-RT USES-RD NO-DIS)
+     "cm32and $rs,$rt"
+     (emit cm32and (f-rd 0) rs rt)
+)
+
+(dnmi m-cm32andn "Counter Manager And With Inverse" (MACH10 USES-RS USES-RT USES-RD NO-DIS)
+     "cm32andn $rs,$rt"
+     (emit cm32andn (f-rd 0) rs rt)
+)
+
+(dnmi m-cm32or "Counter Manager Or" (MACH10 USES-RS USES-RT USES-RD NO-DIS)
+     "cm32or $rs,$rt"
+     (emit cm32or (f-rd 0) rs rt)
+)
+
+(dnmi m-cm32ra "Counter Manager 32-bit Rolling Add" (MACH10 USES-RS USES-RT USES-RD NO-DIS)
+     "cm32ra $rs,$rt"
+     (emit cm32ra (f-rd 0) rs rt)
+)
+
+(dnmi m-cm32rd "Counter Manager 32-bit Rolling Decrement" (MACH10 USES-RT USES-RD NO-DIS)
+     "cm32rd $rt"
+     (emit cm32rd (f-rd 0) rt)
+)
+
+(dnmi m-cm32ri "Counter Manager 32-bit Rolling Increment" (MACH10 USES-RT USES-RD NO-DIS)
+     "cm32ri $rt"
+     (emit cm32ri (f-rd 0) rt)
+)
+
+(dnmi m-cm32rs "Counter Manager 32-bit Rolling Subtract" (MACH10 USES-RS USES-RT USES-RD NO-DIS)
+     "cm32rs $rs,$rt"
+     (emit cm32rs (f-rd 0) rs rt)
+)
+
+(dnmi m-cm32sa "Counter Manager 32-bit Saturating Add" (MACH10 USES-RS USES-RT USES-RD NO-DIS)
+     "cm32sa $rs,$rt"
+     (emit cm32sa (f-rd 0) rs rt)
+)
+
+(dnmi m-cm32sd "Counter Manager 32-bit Saturating Decrement" (MACH10 USES-RT USES-RD NO-DIS)
+     "cm32sd $rt"
+     (emit cm32sd (f-rd 0) rt)
+)
+
+(dnmi m-cm32si "Counter Manager 32-bit Saturating Increment" (MACH10 USES-RT USES-RD NO-DIS)
+     "cm32si $rt"
+     (emit cm32si (f-rd 0) rt)
+)
+
+(dnmi m-cm32ss "Counter Manager 32-bit Saturating Subtract" (MACH10 USES-RS USES-RT USES-RD NO-DIS)
+     "cm32ss $rs,$rt"
+     (emit cm32ss (f-rd 0) rs rt)
+)
+
+(dnmi m-cm32xor "Counter Manager Xor" (MACH10 USES-RS USES-RT USES-RD NO-DIS)
+     "cm32xor $rs,$rt"
+     (emit cm32xor (f-rd 0) rs rt)
+)
+
+(dnmi m-cm64clr "Counter Manager Clear" (MACH10 USES-RT USES-RD NO-DIS)
+     "cm64clr $rt"
+     (emit cm64clr (f-rd 0) rt)
+)
+
+(dnmi m-cm64ra "Counter Manager 64-bit Rolling Add" (MACH10 USES-RS USES-RT USES-RD NO-DIS)
+     "cm64ra $rs,$rt"
+     (emit cm64ra (f-rd 0) rs rt)
+)
+
+(dnmi m-cm64rd "Counter Manager 64-bit Rolling Decrement" (MACH10 USES-RT USES-RD NO-DIS)
+     "cm64rd $rt"
+     (emit cm64rd (f-rd 0) rt)
+)
+
+(dnmi m-cm64ri "Counter Manager 32-bit Rolling Increment" (MACH10 USES-RT USES-RD NO-DIS)
+     "cm64ri $rt"
+     (emit cm64ri (f-rd 0) rt)
+)
+
+(dnmi m-cm64ria2 "Counter Manager 32/32 Rolling Increment/Add" (MACH10 USES-RS USES-RT USES-RD NO-DIS)
+     "cm64ria2 $rs,$rt"
+     (emit cm64ria2 (f-rd 0) rs rt)
+)
+
+(dnmi m-cm64rs "Counter Manager 64-bit Rolling Subtract" (MACH10 USES-RS USES-RT USES-RD NO-DIS)
+     "cm64rs $rs,$rt"
+     (emit cm64rs (f-rd 0) rs rt)
+)
+
+(dnmi m-cm64sa "Counter Manager 64-bit Saturating Add" (MACH10 USES-RS USES-RT USES-RD NO-DIS)
+     "cm64sa $rs,$rt"
+     (emit cm64sa (f-rd 0) rs rt)
+)
+
+(dnmi m-cm64sd "Counter Manager 64-bit Saturating Decrement" (MACH10 USES-RT USES-RD NO-DIS)
+     "cm64sd $rt"
+     (emit cm64sd (f-rd 0) rt)
+)
+
+(dnmi m-cm64si "Counter Manager 64-bit Saturating Increment" (MACH10 USES-RT USES-RD NO-DIS)
+     "cm64si $rt"
+     (emit cm64si (f-rd 0) rt)
+)
+
+(dnmi m-cm64sia2 "Counter Manager 32/32 Saturating Increment/Add" (MACH10 USES-RS USES-RT USES-RD NO-DIS)
+     "cm64sia2 $rs,$rt"
+     (emit cm64sia2 (f-rd 0) rs rt)
+)
+
+(dnmi m-cm64ss "Counter Manager 64-bit Saturating Subtract" (MACH10 USES-RS USES-RT USES-RD NO-DIS)
+     "cm64ss $rs,$rt"
+     (emit cm64ss (f-rd 0) rs rt)
+)
+
+(dnmi m-cm128ria2 "Counter Manager 128-bit 64/64 Rolling Increment/Add" (MACH10 USES-RS USES-RT USES-RD NO-DIS)
+     "cm128ria2 $rs,$rt"
+     (emit cm128ria2 (f-rd 0) rs rt)
+)
+
+(dnmi m-cm128ria3 "Counter Manager 128-bit 32/32/64 Rolling Increment/Add" (MACH10 USES-RS USES-RT USES-RD NO-DIS)
+     "cm128ria3 $rs,$rt,${cm-3z}"
+     (emit cm128ria3 (f-rd 0) rs rt cm-3z)
+)
+
+(dnmi m-cm128ria4 "Counter Manager 128-bit 32/32/32/32 Rolling Inc/Add" (MACH10 USES-RS USES-RT USES-RD NO-DIS)
+     "cm128ria4 $rs,$rt,${cm-4z}"
+     (emit cm128ria4 (f-rd 0) rs rt cm-4z)
+)
+
+(dnmi m-cm128sia2 "Counter Manager 128-bit 64/64 Saturating Inc/Add" (MACH10 USES-RS USES-RT USES-RD NO-DIS)
+     "cm128sia2 $rs,$rt"
+     (emit cm128sia2 (f-rd 0) rs rt)
+)
+
+(dnmi m-cm128sia3 "Counter Manager 128-bit 32/32/64 Saturating Inc/Add" (MACH10 USES-RS USES-RT USES-RD NO-DIS)
+     "cm128sia3 $rs,$rt,${cm-3z}"
+     (emit cm128sia3 (f-rd 0) rs rt cm-3z)
+)
+
+(dnmi m-cm128sia4 "Counter Manager 128-bit 32/32/32/32 Saturating Inc/Add" (MACH10 USES-RS USES-RT USES-RD NO-DIS)
+     "cm128sia4 $rs,$rt,${cm-4z}"
+     (emit cm128sia4 (f-rd 0) rs rt cm-4z)
+)
+
+(dnmi m-cmphdr "Get a Complete Header" (MACH10 NO-DIS)
+     "cmphdr"
+     (emit cmphdr (f-rd 0))
+)
+
+(dnmi m-dbd "Deallocate a Data Buffer Pointer" (MACH10 USES-RD USES-RT NO-DIS)
+     "dbd $rd,$rt"
+     (emit dbd rd (f-rs 0) rt)
+)
+
+(dnmi m2-dbd "Deallocate a Data Buffer Pointer" (MACH10 USES-RT NO-DIS)
+     "dbd $rt"
+     (emit dbd (f-rd 0) (f-rs 0) rt)
+)
+
+(dnmi m-dpwt "DSTN_PORT Write" (MACH10 USES-RS NO-DIS)
+     "dpwt $rs"
+     (emit dpwt (f-rd 0) rs)
+)
+
+(dnmi m-free "" (MACH10 USES-RS USES-RD NO-DIS)
+     "free $rs"
+     (emit free (f-rd 0) rs)
+)
+
+;(dnmi m-jal "jump and link, implied r31" (MACH10 USES-RT NO-DIS)
+;     "jal $jmptarg"
+;     (emit jal (f-rt 31) jmptarg)
+;)
+
+(dnmi m-lock "lock memory" (MACH10 USES-RT NO-DIS)
+     "lock $rt"
+     (emit lock (f-rd 0) rt)
+)
+
+(dnmi m-pkrla "Packet Release Absolute" (MACH10 USES-RS USES-RT USES-RD NO-DIS)
+     "pkrla $rs,$rt"
+     (emit pkrla (f-rd 0) rs rt)
+)
+
+(dnmi m-pkrlac "Packet Release Absolute Continue" (MACH10 USES-RS USES-RT USES-RD NO-DIS)
+     "pkrlac $rs,$rt"
+     (emit pkrlac (f-rd 0) rs rt)
+)
+
+(dnmi m-pkrlah "Packet Release Absolute and Hold" (MACH10 USES-RS USES-RT USES-RD NO-DIS)
+     "pkrlah $rs,$rt"
+     (emit pkrlah (f-rd 0) rs rt)
+)
+
+(dnmi m-pkrlau "Packet Release Absolute Unconditional" (MACH10 USES-RS USES-RT USES-RD NO-DIS)
+     "pkrlau $rs,$rt"
+     (emit pkrlau (f-rd 0) rs rt)
+)
+
+(dnmi m-pkrli "Packet Release Immediate" (MACH10 USES-RD USES-RS USES-RT NO-DIS)
+     "pkrli $rs,$rt,$bytecount"
+     (emit pkrli (f-rd 0) rs rt bytecount)
+)
+
+(dnmi m-pkrlic "Packet Release Immediate Continue" (MACH10 USES-RS USES-RT NO-DIS)
+     "pkrlic $rs,$rt,$bytecount"
+     (emit pkrlic (f-rd 0) rs rt bytecount)
+)
+
+(dnmi m-pkrlih "Packet Release Immediate and Hold" (MACH10 USES-RD USES-RS USES-RT NO-DIS)
+     "pkrlih $rs,$rt,$bytecount"
+     (emit pkrlih (f-rd 0) rs rt bytecount)
+)
+
+(dnmi m-pkrliu "Packet Release Immediate Unconditional" (MACH10 USES-RD USES-RS USES-RT NO-DIS)
+     "pkrliu $rs,$rt,$bytecount"
+     (emit pkrliu (f-rd 0) rs rt bytecount)
+)
+
+(dnmi m-rba "Read Bytes Absolute" (MACH10 USES-RS USES-RT USES-RD NO-DIS)
+     "rba $rs,$rt"
+     (emit rba (f-rd 0) rs rt)
+)
+
+(dnmi m-rbal "Read Bytes Absolute and Lock" (MACH10 USES-RS USES-RT USES-RD NO-DIS)
+     "rbal $rs,$rt"
+     (emit rbal (f-rd 0) rs rt)
+)
+
+(dnmi m-rbar "Read Bytes Absolute and Release" (MACH10 USES-RS USES-RT USES-RD NO-DIS)
+     "rbar $rs,$rt"
+     (emit rbar (f-rd 0) rs rt)
+)
+
+(dnmi m-rbi "Read Bytes Immediate" (MACH10 USES-RS USES-RT NO-DIS)
+     "rbi $rs,$rt,$bytecount"
+     (emit rbi (f-rd 0) rs rt bytecount)
+)
+
+(dnmi m-rbil "Read Bytes Immediate and Lock" (MACH10 USES-RS USES-RT NO-DIS)
+     "rbil $rs,$rt,$bytecount"
+     (emit rbil (f-rd 0) rs rt bytecount)
+)
+
+(dnmi m-rbir "Read Bytes Immediate and Release" (MACH10 USES-RS USES-RT NO-DIS)
+     "rbir $rs,$rt,$bytecount"
+     (emit rbir (f-rd 0) rs rt bytecount)
+)
+
+(dnmi m-swwr "Single Word Write" (MACH10 USES-RS USES-RT USES-RD NO-DIS)
+     "swwr $rs,$rt"
+     (emit swwr (f-rd 0) rs rt)
+)
+
+(dnmi m-swwru "Single Word Write and Unlock" (MACH10 USES-RS USES-RT USES-RD NO-DIS)
+     "swwru $rs,$rt"
+     (emit swwru (f-rd 0) rs rt)
+)
+
+(dnmi m-tstod "Test Header Buffer Order Dependency" (MACH10 USES-RS USES-RD NO-DIS)
+     "tstod $rs"
+     (emit tstod (f-rd 0) rs)
+)
+
+(dnmi m-unlk "" (MACH10 USES-RT USES-RD NO-DIS)
+     "unlk $rt"
+     (emit unlk (f-rd 0) rt)
+)
+     
+(dnmi m-wba "Write Bytes Absolute" (MACH10 USES-RS USES-RT USES-RD NO-DIS)
+     "wba $rs,$rt"
+     (emit wba (f-rd 0) rs rt)
+)
+
+(dnmi m-wbac "Write Bytes Absolute Cacheable" (MACH10 USES-RS USES-RT USES-RD NO-DIS)
+     "wbac $rs,$rt"
+     (emit wbac (f-rd 0) rs rt)
+)
+
+(dnmi m-wbau "Write Bytes Absolute and Unlock" (MACH10 USES-RS USES-RT USES-RD NO-DIS)
+     "wbau $rs,$rt"
+     (emit wbau (f-rd 0) rs rt)
+)
+
+(dnmi m-wbi "Write Bytes Immediate" (MACH10 USES-RD USES-RS USES-RT NO-DIS)
+     "wbi $rs,$rt,$bytecount"
+     (emit wbi (f-rd 0) rs rt bytecount)
+)
+
+(dnmi m-wbic "Write Bytes Immediate Cacheable" (MACH10 USES-RD USES-RS USES-RT NO-DIS)
+     "wbic $rs,$rt,$bytecount"
+     (emit wbic (f-rd 0) rs rt bytecount)
+)
+
+(dnmi m-wbiu "Write Bytes Immediate" (MACH10 USES-RD USES-RS USES-RT NO-DIS)
+     "wbiu $rs,$rt,$bytecount"
+     (emit wbiu (f-rd 0) rs rt bytecount)
+)
+