e200 LSP support

It has bothered me for a long time that we have disabled LSP (and SPE)
tests.  Also the LSP test comment indicating there is something wrong
with get_powerpc_dialect.  I don't think there is.  Decoding of a VLE
instruction depends on whether the processor is in VLE mode (some
processors support both VLE and standard PPC) which we flag per
section with SHF_PPC_VLE for decoding when disassembling.

Background: Some versions of powerpc e200 have "Lightweight Signal
Processing" support, examples being e200z215 and e200z425.  As far as
I can tell, LSP and SPE are mutually exclusive.  This seems to be
borne out by insn encoding, for example LSP "zvaddih" and SPE "evaddw"
have the same encoding.  So none of the processor descriptions in
ppc_opts ought to have both PPC_OPCODE_LSP and PPC_OPCODE_SPE/2, if we
want disassembly to work.  I also could not find anything to suggest
that the LSP insns are enabled only in VLE mode, which means the LSP
insns should not be in vle_opcodes.

Fix all this by moving the LSP insns to their own table, and add a new
e200z2 cpu entry with LSP support, removing LSP from -me200z4 and from
-mvle.  (Yes, I know, as I said above some of the e200z4 processors
have LSP.  Others have SPE.  It's hard to choose good options.  Think
of z2 as meaning earlier, z4 as later.)  Also add -mlsp to allow
adding the LSP insn set.

include/
	* opcode/ppc.h (lsp_opcodes, lsp_num_opcodes): Declare.
	(LSP_OP_TO_SEG): Define.
binutils/
	* doc/binutils.texi: Update ppc docs.
gas/
	* config/tc-ppc.c (ppc_setup_opcodes): Add lsp opcodes to ppc_hash.
	* doc/c-ppc.texi: Document e200 and lsp.
	* testsuite/gas/ppc/lsp-checks.d: Assemble with -me200z2.
	* testsuite/gas/ppc/lsp.d: Likewise, disassembly too.
	* testsuite/gas/ppc/ppc.exp: Don't xfail lsp test.
opcodes/
	* ppc-dis.c (ppc_opts): Add e200z2 and lsp.  Don't set
	PPC_OPCODE_LSP for e200z4 or vle.
	(ppc_parse_cpu): Mutually exclude LSP and SPE.
	(LSP_OPCD_SEGS): Define.
	(lsp_opcd_indices): New array.
	(disassemble_init_powerpc): Init lsp_opcd_indices.
	(lookup_lsp): New function.
	(print_insn_powerpc): Call it.
	* ppc-opc.c: Include libiberty.h for ARRAY_SIZE and use throughout.
	(vle_opcodes): Move LSP opcodes to..
	(lsp_opcodes): ..here, and sort.
	(lsp_num_opcodes): New.

1 files changed, 5 insertions, 4 deletions

diff --git a/binutils/doc/binutils.texi b/binutils/doc/binutils.texi
index 5ea95edecf1..6eea08fb91b 100644
--- a/binutils/doc/binutils.texi
+++ b/binutils/doc/binutils.texi
@@ -2632,7 +2632,7 @@ rather than @code{li}.  All of the @option{-m} arguments for
 @option{601}, @option{603}, @option{604}, @option{620}, @option{7400},
 @option{7410}, @option{7450}, @option{7455}, @option{750cl},
 @option{821}, @option{850}, @option{860}, @option{a2}, @option{booke},
-@option{booke32}, @option{cell}, @option{com}, @option{e200z4},
+@option{booke32}, @option{cell}, @option{com}, @option{e200z2}, @option{e200z4},
 @option{e300}, @option{e500}, @option{e500mc}, @option{e500mc64},
 @option{e500x2}, @option{e5500}, @option{e6500}, @option{efs},
 @option{power4}, @option{power5}, @option{power6}, @option{power7},
@@ -2643,9 +2643,10 @@ rather than @code{li}.  All of the @option{-m} arguments for
 @option{pwrx}, @option{titan}, @option{vle}, and @option{future}.
 @option{32} and @option{64} modify the default or a prior CPU
 selection, disabling and enabling 64-bit insns respectively.  In
-addition, @option{altivec}, @option{any}, @option{htm}, @option{vsx},
-and @option{spe} add capabilities to a previous @emph{or later} CPU
-selection.  @option{any} will disassemble any opcode known to
+addition, @option{altivec}, @option{any}, @option{lsp}, @option{htm},
+@option{vsx}, @option{spe} and  @option{spe2} add capabilities to a
+previous @emph{or later} CPU selection.
+@option{any} will disassemble any opcode known to
 binutils, but in cases where an opcode has two different meanings or
 different arguments, you may not see the disassembly you expect.
 If you disassemble without giving a CPU selection, a default will be