Add support for MIPS R6.

bfd/
 	* aoutx.h (NAME (aout, machine_type)): Add mips32r6 and mips64r6.
 	* archures.c (bfd_architecture): Likewise.
 	* bfd-in2.h (bfd_architecture): Likewise.
 	(bfd_reloc_code_real): Add relocs BFD_RELOC_MIPS_21_PCREL_S2,
 	BFD_RELOC_MIPS_26_PCREL_S2, BFD_RELOC_MIPS_18_PCREL_S3 and
 	BFD_RELOC_MIPS_19_PCREL_S2.
 	* cpu-mips.c (arch_info_struct): Add mips32r6 and mips64r6.
 	* elf32-mips.c: Define relocs R_MIPS_PC21_S2, R_MIPS_PC26_S2
 	R_MIPS_PC18_S3, R_MIPS_PC19_S2, R_MIPS_PCHI16 and R_MIPS_PCLO16.
 	(mips_reloc_map): Add entries for BFD_RELOC_MIPS_21_PCREL_S2,
 	BFD_RELOC_MIPS_26_PCREL_S2, BFD_RELOC_MIPS_18_PCREL_S3,
 	BFD_RELOC_MIPS_19_PCREL_S2, BFD_RELOC_HI16_S_PCREL and
 	BFD_RELOC_LO16_PCREL.
 	* elf64-mips.c: Define REL, and RELA relocations R_MIPS_PC21_S2,
	R_MIPS_PC26_S2, R_MIPS_PC18_S3, R_MIPS_PC19_S2, R_MIPS_PCHI16
	and R_MIPS_PCLO16.
 	(mips_reloc_map): Add entries for BFD_RELOC_MIPS_21_PCREL_S2,
 	BFD_RELOC_MIPS_26_PCREL_S2, BFD_RELOC_MIPS_18_PCREL_S3,
 	BFD_RELOC_MIPS_19_PCREL_S2, BFD_RELOC_HI16_S_PCREL and
 	BFD_RELOC_LO16_PCREL.
 	* elfn32-mips.c: Likewise.
 	* elfxx-mips.c (MIPSR6_P): New define.
 	(mipsr6_exec_plt_entry): New array.
	(hi16_reloc_p): Add support for R_MIPS_PCHI16.
	(lo16_reloc_p): Add support for R_MIPS_PCLO16.
 	(aligned_pcrel_reloc_p): New function.
 	(mips_elf_relocation_needs_la25_stub): Add support for relocs:
 	R_MIPS_PC21_S2 and R_MIPS_PC26_S2.
 	(mips_elf_calculate_relocation): Add support for relocs:
 	R_MIPS_PC21_S2, R_MIPS_PC26_S2, R_MIPS_PC18_S3, R_MIPS_PC19_S2,
 	R_MIPS_PCHI16 and R_MIPS_PCLO16.
 	(_bfd_elf_mips_mach): Add support for mips32r6 and mips64r6.
	(mips_elf_add_lo16_rel_addend): Add support for R_MIPS_PCHI16.
 	(_bfd_mips_elf_check_relocs): Add support for relocs:
	R_MIPS_PC21_S2 and R_MIPS_PC26_S2.
 	(_bfd_mips_elf_relocate_section): Add a check for unaligned
 	pc relative relocs.
 	(_bfd_mips_elf_finish_dynamic_symbol): Add support for MIPS r6
 	plt entry.
 	(mips_set_isa_flags): Add support for mips32r6 and mips64r6.
 	(_bfd_mips_elf_print_private_bfd_data): Likewise.
 	(mips_32bit_flags_p): Add support for mips32r6.
 	* libbfd.h (bfd_reloc_code_real_names): Add entries for
 	BFD_RELOC_MIPS_21_PCREL_S2, BFD_RELOC_MIPS_26_PCREL_S2,
 	BFD_RELOC_MIPS_18_PCREL_S3 and BFD_RELOC_MIPS_19_PCREL_S2.
 	* reloc.c: Document relocs BFD_RELOC_MIPS_21_PCREL_S2,
 	BFD_RELOC_MIPS_26_PCREL_S2, BFD_RELOC_MIPS_18_PCREL_S3 and
 	BFD_RELOC_MIPS_19_PCREL_S2.

binutils/
 	* readelf.c (get_machine_flags): Add support for mips32r6 and
 	mips64r6.

elfcpp/
 	* mips.h (E_MIPS_ARCH_32R6, E_MIPS_ARCH_64R6): New enum constants.

gas/
 	* config/tc-mips.c (mips_nan2008): New static global.
	(mips_flag_nan2008): Removed.
	(LL_SC_FMT): New define.
	(COP12_FMT): Updated.
	(ISA_IS_R6): New define.
 	(ISA_HAS_64BIT_REGS): Add mips64r6.
 	(ISA_HAS_DROR): Likewise.
 	(ISA_HAS_64BIT_FPRS): Add mips32r6 and mips64r6.
 	(ISA_HAS_ROR): Likewise.
 	(ISA_HAS_ODD_SINGLE_FPR): Likewise.
 	(ISA_HAS_MXHC1): Likewise.
 	(hilo_interlocks): Likewise.
 	(md_longopts): Likewise.
	(ISA_HAS_LEGACY_NAN): New define.
 	(options): Add OPTION_MIPS32R6 and OPTION_MIPS64R6.
 	(mips_ase): Add field rem_rev.
 	(mips_ases): Updated to add which ISA an ASE was removed in.
 	(mips_isa_rev): Add support for mips32r6 and mips64r6.
 	(mips_check_isa_supports_ase): Add support to check if an ASE
 	has been removed in the specified MIPS ISA revision.
 	(validate_mips_insn): Skip '-' character.
	(macro_build): Likewise.
	(mips_check_options): Prevent R6 working with fp32, mips16,
	micromips, or branch relaxation.
	(file_mips_check_options): Set R6 floating point registers to
	64 bit.  Also deal with the nan2008 option.
 	(limited_pcrel_reloc_p): Add relocs: BFD_RELOC_MIPS_21_PCREL_S2,
 	BFD_RELOC_MIPS_26_PCREL_S2, BFD_RELOC_MIPS_18_PCREL_S3,
 	BFD_RELOC_MIPS_19_PCREL_S2, BFD_RELOC_HI16_S_PCREL and
 	BFD_RELOC_LO16_PCREL.
 	(operand_reg_mask): Add support for OP_SAME_RS_RT, OP_CHECK_PREV
	and OP_NON_ZERO_REG.
 	(match_check_prev_operand): New static function.
 	(match_same_rs_rt_operand): New static function.
	(match_non_zero_reg_operand): New static function.
 	(match_operand): Added entries for: OP_SAME_RS_RT, OP_CHECK_PREV
	and OP_NON_ZERO_REG.
 	(insns_between): Added case to deal with forbidden slots.
 	(append_insn): Added support for relocs: BFD_RELOC_MIPS_21_PCREL_S2
 	and BFD_RELOC_MIPS_26_PCREL_S2.
 	(match_insn): Add support for operands -A, -B, +' and +".  Also
 	skip '-' character.
 	(mips_percent_op): Add entries for %pcrel_hi and %pcrel_lo.
 	(md_parse_option): Add support for mips32r6 and mips64r6.  Also
	update the nan option handling.
 	(md_pcrel_from): Add cases for relocs: BFD_RELOC_MIPS_21_PCREL_S2,
 	BFD_RELOC_MIPS_26_PCREL_S2.
 	(mips_force_relocation): Prevent forced relaxation for MIPS r6.
 	(md_apply_fix): Add support for relocs: BFD_RELOC_MIPS_21_PCREL_S2,
 	BFD_RELOC_MIPS_26_PCREL_S2, BFD_RELOC_MIPS_18_PCREL_S3,
 	BFD_RELOC_MIPS_19_PCREL_S2, BFD_RELOC_HI16_S_PCREL and
 	BFD_RELOC_LO16_PCREL.
 	(s_mipsset): Add support for mips32r6 and mips64r6.
	(s_nan): Update to support the new nan2008 framework.
 	(tc_gen_reloc): Add relocs: BFD_RELOC_MIPS_21_PCREL_S2,
 	BFD_RELOC_MIPS_26_PCREL_S2, BFD_RELOC_MIPS_18_PCREL_S3,
 	BFD_RELOC_MIPS_19_PCREL_S2, BFD_RELOC_HI16_S_PCREL and
 	BFD_RELOC_LO16_PCREL.
	(mips_elf_final_processing): Updated to use the mips_nan2008.
 	(mips_cpu_info_table): Add entries for mips32r6 and mips64r6.
	(macro): Enable ldc2, sdc2, ll, lld, swc2, sc, scd, cache, pref
	macros for R6.
	(mips_fix_adjustable): Make PC relative R6 relocations relative
	to the symbol and not the section.
 	* configure.ac: Add support for mips32r6 and mips64r6.
 	* configure: Regenerate.
 	* doc/c-mips.texi: Document the -mips32r6 and -mips64r6 command line
 	options.
	* doc/as.texinfo: Likewise.

gas/testsuite/
	* gas/mips/24k-triple-stores-1.s: If testing for r6 prevent
	non-supported instructions from being tested.
	* gas/mips/24k-triple-stores-2.s: Likewise.
	* gas/mips/24k-triple-stores-3.s: Likewise.
	* gas/mips/24k-triple-stores-6.s: Likewise.
	* gas/mips/beq.s: Likewise.
	* gas/mips/eva.s: Likewise.
	* gas/mips/ld-zero-3.s: Likewise.
	* gas/mips/mips32-cp2.s: Likewise.
	* gas/mips/mips32.s: Likewise.
	* gas/mips/mips4.s: Likewise.
	* gas/mips/add.s: Don't test the add instructions if r6, and
	add padding.
	* gas/mips/add.d: Check for a triple dot not a nop at the end of the
	disassembly output.
	* gas/mips/micromips@add.d: Likewise.
	* gas/mips/mipsr6@24k-branch-delay-1.d: New file.
	* gas/mips/mipsr6@24k-triple-stores-1.d: New file.
	* gas/mips/mipsr6@24k-triple-stores-2-llsc.d: New file.
	* gas/mips/mipsr6@24k-triple-stores-2.d: New file.
	* gas/mips/mipsr6@24k-triple-stores-3.d: New file.
	* gas/mips/mipsr6@24k-triple-stores-6.d: New file.
	* gas/mips/mipsr6@add.d: New file.
	* gas/mips/mipsr6@attr-gnu-4-1-msingle-float.l: New file.
	* gas/mips/mipsr6@attr-gnu-4-1-msingle-float.s: New file.
	* gas/mips/mipsr6@attr-gnu-4-1-msoft-float.l: New file.
	* gas/mips/mipsr6@attr-gnu-4-1-msoft-float.s: New file.
	* gas/mips/mipsr6@attr-gnu-4-2-mdouble-float.l: New file.
	* gas/mips/mipsr6@attr-gnu-4-2-mdouble-float.s: New file.
	* gas/mips/mipsr6@beq.d: New file.
	* gas/mips/mipsr6@bge.d: New file.
	* gas/mips/mipsr6@bgeu.d: New file.
	* gas/mips/mipsr6@blt.d: New file.
	* gas/mips/mipsr6@bltu.d: New file.
	* gas/mips/mipsr6@branch-misc-1.d: New file.
	* gas/mips/mipsr6@branch-misc-2-64.d: New file.
	* gas/mips/mipsr6@branch-misc-2pic-64.d: New file.
	* gas/mips/mipsr6@branch-misc-4-64.d: New file.
	* gas/mips/mipsr6@cache.d: New file.
	* gas/mips/mipsr6@eva.d: New file.
	* gas/mips/mipsr6@jal-svr4pic-noreorder.d: New file.
	* gas/mips/mipsr6@jal-svr4pic.d: New file.
	* gas/mips/mipsr6@ld-zero-2.d: New file.
	* gas/mips/mipsr6@ld-zero-3.d: New file.
	* gas/mips/mipsr6@loc-swap-dis.d: New file.
	* gas/mips/mipsr6@mips32-cp2.d: New file.
	* gas/mips/mipsr6@mips32-imm.d: New file.
	* gas/mips/mipsr6@mips32.d: New file.
	* gas/mips/mipsr6@mips32r2.d: New file.
	* gas/mips/mipsr6@mips4-fp.d: New file.
	* gas/mips/mipsr6@mips4-fp.l: New file.
	* gas/mips/mipsr6@mips4-fp.s: New file.
	* gas/mips/mipsr6@mips4.d: New file.
	* gas/mips/mipsr6@mips5-fp.d: New file.
	* gas/mips/mipsr6@mips5-fp.l: New file.
	* gas/mips/mipsr6@mips5-fp.s: New file.
	* gas/mips/mipsr6@mips64.d: New file.
	* gas/mips/mipsr6@msa-branch.d: New file.
	* gas/mips/mipsr6@msa.d: New file.
	* gas/mips/mipsr6@pref.d: New file.
	* gas/mips/mipsr6@relax-swap3.d: New file.
	* gas/mips/r6-64-n32.d: New file.
	* gas/mips/r6-64-n64.d: New file.
	* gas/mips/r6-64-removed.l: New file.
	* gas/mips/r6-64-removed.s: New file.
	* gas/mips/r6-64.s: New file.
	* gas/mips/r6-attr-none-double.d: New file.
	* gas/mips/r6-n32.d: New file.
	* gas/mips/r6-n64.d: New file.
	* gas/mips/r6-removed.l: New file.
	* gas/mips/r6-removed.s: New file.
	* gas/mips/r6.d: New file.
	* gas/mips/r6.s: New file.
	* gas/mips/mipsr6@mips32-dsp.d: New file.
	* gas/mips/mipsr6@mips32-dspr2.d: New file.
	* gas/mips/mipsr6@mips32r2-ill.l: New file.
	* gas/mips/mipsr6@mips32r2-ill.s: New file.
	* gas/mips/cache.s: Add r6 instruction varients.
	* gas/mips/mips.exp: Add support for the mips32r6 and mips64r6
	architectures.  Also prevent non r6 supported tests from running.
	Finally, add in support for running the new r6 tests.
	(run_dump_test_arch): Add support for mipsr6 tests.
	(run_list_test_arch): Add support for using files of the
	form arch@testname.l .

include/elf/
 	* mips.h: Add relocs: R_MIPS_PC21_S2, R_MIPS_PC26_S2, R_MIPS_PC18_S3,
 	R_MIPS_PC19_S2, R_MIPS_PCHI16 and R_MIPS_PCLO16.
 	(E_MIPS_ARCH_32R6): New define.
 	(E_MIPS_ARCH_64R6): New define.

include/opcode/
 	* mips.h (mips_operand_type): Add new entries: OP_SAME_RS_RT,
 	OP_CHECK_PREV and OP_NON_ZERO_REG.  Add descriptions for the MIPS R6
	instruction arguments: -a, -b, -d, -s, -t, -u, -v, -w, -x, -y, -A, -B,
	 +I, +O, +R, +:, +\, +", +;
	(mips_check_prev_operand): New struct.
 	(INSN2_FORBIDDEN_SLOT): New define.
 	(INSN_ISA32R6): New define.
 	(INSN_ISA64R6): New define.
	(INSN_UPTO32R6): New define.
	(INSN_UPTO64R6): New define.
	(mips_isa_table): Add INSN_UPTO32R6 and INSN_UPTO64R6.
 	(ISA_MIPS32R6): New define.
 	(ISA_MIPS64R6): New define.
 	(CPU_MIPS32R6): New define.
 	(CPU_MIPS64R6): New define.
 	(cpu_is_member): Add cases for CPU_MIPS32R6, and CPU_MIPS64R6.

ld/
 	* ldmain.c (get_emulation): Add support for -mips32r6 and -mips64r6.

opcodes/
 	* mips-dis.c (mips_arch_choices): Add entries for mips32r6 and
 	mips64r6.
 	(parse_mips_dis_option): Allow MSA and virtualization support for
 	mips64r6.
 	(mips_print_arg_state): Add fields dest_regno and seen_dest.
 	(mips_seen_register): New function.
 	(print_insn_arg): Refactored code to use mips_seen_register
	function.  Add support for OP_SAME_RS_RT, OP_CHECK_PREV and
	OP_NON_ZERO_REG.  Changed OP_REPEAT_DEST_REG case to print out
	the register rather than aborting.
 	(print_insn_args): Add length argument.  Add code to correctly
	calculate the instruction address for pc relative instructions.
	(validate_insn_args): New static function.
 	(print_insn_mips): Prevent jalx disassembling for r6.  Use
	validate_insn_args.
	(print_insn_micromips): Use validate_insn_args.
	all the arguments are valid.
	* mips-formats.h (PREV_CHECK): New define.
 	* mips-opc.c (decode_mips_operand): Add support for -a, -b, -d, -s,
 	-t, -u, -v, -w, -x, -y, -A, -B, +I, +O, +R, +:, +\, +", +;
 	(RD_pc): New define.
 	(FS): New define.
 	(I37): New define.
 	(I69): New define.
 	(mips_builtin_opcodes): Add MIPS R6 instructions.  Exclude recoded
 	MIPS R6 instructions from MIPS R2 instructions.

107 files changed, 8476 insertions, 479 deletions

diff --git a/bfd/ChangeLog b/bfd/ChangeLog
index af83e3e1d70..ca5f7b72757 100644
--- a/bfd/ChangeLog
+++ b/bfd/ChangeLog
@@ -1,3 +1,56 @@
+2014-09-15  Andrew Bennett  <andrew.bennett@imgtec.com>
+	    Matthew Fortune  <matthew.fortune@imgtec.com>
+
+	* aoutx.h (NAME (aout, machine_type)): Add mips32r6 and mips64r6.
+	* archures.c (bfd_architecture): Likewise.
+	* bfd-in2.h (bfd_architecture): Likewise.
+	(bfd_reloc_code_real): Add relocs BFD_RELOC_MIPS_21_PCREL_S2,
+	BFD_RELOC_MIPS_26_PCREL_S2, BFD_RELOC_MIPS_18_PCREL_S3 and
+	BFD_RELOC_MIPS_19_PCREL_S2.
+	* cpu-mips.c (arch_info_struct): Add mips32r6 and mips64r6.
+	* elf32-mips.c: Define relocs R_MIPS_PC21_S2, R_MIPS_PC26_S2
+	R_MIPS_PC18_S3, R_MIPS_PC19_S2, R_MIPS_PCHI16 and R_MIPS_PCLO16.
+	(mips_reloc_map): Add entries for BFD_RELOC_MIPS_21_PCREL_S2,
+	BFD_RELOC_MIPS_26_PCREL_S2, BFD_RELOC_MIPS_18_PCREL_S3,
+	BFD_RELOC_MIPS_19_PCREL_S2, BFD_RELOC_HI16_S_PCREL and
+	BFD_RELOC_LO16_PCREL.
+	* elf64-mips.c: Define REL, and RELA relocations R_MIPS_PC21_S2,
+	R_MIPS_PC26_S2, R_MIPS_PC18_S3, R_MIPS_PC19_S2, R_MIPS_PCHI16
+	and R_MIPS_PCLO16.
+	(mips_reloc_map): Add entries for BFD_RELOC_MIPS_21_PCREL_S2,
+	BFD_RELOC_MIPS_26_PCREL_S2, BFD_RELOC_MIPS_18_PCREL_S3,
+	BFD_RELOC_MIPS_19_PCREL_S2, BFD_RELOC_HI16_S_PCREL and
+	BFD_RELOC_LO16_PCREL.
+	* elfn32-mips.c: Likewise.
+	* elfxx-mips.c (MIPSR6_P): New define.
+	(mipsr6_exec_plt_entry): New array.
+	(hi16_reloc_p): Add support for R_MIPS_PCHI16.
+	(lo16_reloc_p): Add support for R_MIPS_PCLO16.
+	(aligned_pcrel_reloc_p): New function.
+	(mips_elf_relocation_needs_la25_stub): Add support for relocs:
+	R_MIPS_PC21_S2 and R_MIPS_PC26_S2.
+	(mips_elf_calculate_relocation): Add support for relocs:
+	R_MIPS_PC21_S2, R_MIPS_PC26_S2, R_MIPS_PC18_S3, R_MIPS_PC19_S2,
+	R_MIPS_PCHI16 and R_MIPS_PCLO16.
+	(_bfd_elf_mips_mach): Add support for mips32r6 and mips64r6.
+	(mips_elf_add_lo16_rel_addend): Add support for R_MIPS_PCHI16.
+	(_bfd_mips_elf_check_relocs): Add support for relocs:
+	R_MIPS_PC21_S2 and R_MIPS_PC26_S2.
+	(_bfd_mips_elf_relocate_section): Add a check for unaligned
+	pc relative relocs.
+	(_bfd_mips_elf_finish_dynamic_symbol): Add support for MIPS r6
+	plt entry.
+	(mips_set_isa_flags): Add support for mips32r6 and mips64r6.
+	(_bfd_mips_elf_print_private_bfd_data): Likewise.
+	(mips_32bit_flags_p): Add support for mips32r6.
+	* libbfd.h (bfd_reloc_code_real_names): Add entries for
+	BFD_RELOC_MIPS_21_PCREL_S2, BFD_RELOC_MIPS_26_PCREL_S2,
+	BFD_RELOC_MIPS_18_PCREL_S3 and BFD_RELOC_MIPS_19_PCREL_S2.
+	* reloc.c: Document relocs BFD_RELOC_MIPS_21_PCREL_S2,
+	BFD_RELOC_MIPS_26_PCREL_S2, BFD_RELOC_MIPS_18_PCREL_S3 and
+	BFD_RELOC_MIPS_19_PCREL_S2.
+	* config.bfd: Add mips*-img-elf* target triple.
+
 2014-09-12  Andrew Bennett  <andrew.bennett@imgtec.com>
 
 	* config.bfd: Add mips*-img-elf* target triple.
diff --git a/bfd/aoutx.h b/bfd/aoutx.h
index b28d6a1033d..37365c4e253 100644
--- a/bfd/aoutx.h
+++ b/bfd/aoutx.h
@@ -793,11 +793,13 @@ NAME (aout, machine_type) (enum bfd_architecture arch,
 	case bfd_mach_mipsisa32r2:
 	case bfd_mach_mipsisa32r3:
 	case bfd_mach_mipsisa32r5:
+	case bfd_mach_mipsisa32r6:
 	case bfd_mach_mips5:
 	case bfd_mach_mipsisa64:
 	case bfd_mach_mipsisa64r2:
 	case bfd_mach_mipsisa64r3:
 	case bfd_mach_mipsisa64r5:
+	case bfd_mach_mipsisa64r6:
 	case bfd_mach_mips_sb1:
 	case bfd_mach_mips_xlr:
 	  /* FIXME: These should be MIPS3, MIPS4, MIPS16, MIPS32, etc.  */
diff --git a/bfd/archures.c b/bfd/archures.c
index 44c9199adf4..c9fd6c81f43 100644
--- a/bfd/archures.c
+++ b/bfd/archures.c
@@ -184,10 +184,12 @@ DESCRIPTION
 .#define bfd_mach_mipsisa32r2           33
 .#define bfd_mach_mipsisa32r3           34
 .#define bfd_mach_mipsisa32r5           36
+.#define bfd_mach_mipsisa32r6           37
 .#define bfd_mach_mipsisa64             64
 .#define bfd_mach_mipsisa64r2           65
 .#define bfd_mach_mipsisa64r3           66
 .#define bfd_mach_mipsisa64r5           68
+.#define bfd_mach_mipsisa64r6           69
 .#define bfd_mach_mips_micromips        96
 .  bfd_arch_i386,      {* Intel 386 *}
 .#define bfd_mach_i386_intel_syntax	(1 << 0)
diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
index 27fc3fea2eb..1f1aed521a8 100644
--- a/bfd/bfd-in2.h
+++ b/bfd/bfd-in2.h
@@ -1971,10 +1971,12 @@ enum bfd_architecture
 #define bfd_mach_mipsisa32r2           33
 #define bfd_mach_mipsisa32r3           34
 #define bfd_mach_mipsisa32r5           36
+#define bfd_mach_mipsisa32r6           37
 #define bfd_mach_mipsisa64             64
 #define bfd_mach_mipsisa64r2           65
 #define bfd_mach_mipsisa64r3           66
 #define bfd_mach_mipsisa64r5           68
+#define bfd_mach_mipsisa64r6           69
 #define bfd_mach_mips_micromips        96
   bfd_arch_i386,      /* Intel 386 */
 #define bfd_mach_i386_intel_syntax     (1 << 0)
@@ -2943,6 +2945,12 @@ to compensate for the borrow when the low bits are added.  */
   BFD_RELOC_MICROMIPS_10_PCREL_S1,
   BFD_RELOC_MICROMIPS_16_PCREL_S1,
 
+/* MIPS PC-relative relocations.  */
+  BFD_RELOC_MIPS_21_PCREL_S2,
+  BFD_RELOC_MIPS_26_PCREL_S2,
+  BFD_RELOC_MIPS_18_PCREL_S3,
+  BFD_RELOC_MIPS_19_PCREL_S2,
+
 /* microMIPS versions of generic BFD relocs.  */
   BFD_RELOC_MICROMIPS_GPREL16,
   BFD_RELOC_MICROMIPS_HI16,
diff --git a/bfd/cpu-mips.c b/bfd/cpu-mips.c
index 360049ce972..b617aaa72ab 100644
--- a/bfd/cpu-mips.c
+++ b/bfd/cpu-mips.c
@@ -89,10 +89,12 @@ enum
   I_mipsisa32r2,
   I_mipsisa32r3,
   I_mipsisa32r5,
+  I_mipsisa32r6,
   I_mipsisa64,
   I_mipsisa64r2,
   I_mipsisa64r3,
   I_mipsisa64r5,
+  I_mipsisa64r6,
   I_sb1,
   I_loongson_2e,
   I_loongson_2f,
@@ -137,10 +139,12 @@ static const bfd_arch_info_type arch_info_struct[] =
   N (32, 32, bfd_mach_mipsisa32r2,"mips:isa32r2", FALSE, NN(I_mipsisa32r2)),
   N (32, 32, bfd_mach_mipsisa32r3,"mips:isa32r3", FALSE, NN(I_mipsisa32r3)),
   N (32, 32, bfd_mach_mipsisa32r5,"mips:isa32r5", FALSE, NN(I_mipsisa32r5)),
+  N (32, 32, bfd_mach_mipsisa32r6,"mips:isa32r6", FALSE, NN(I_mipsisa32r6)),
   N (64, 64, bfd_mach_mipsisa64,  "mips:isa64",   FALSE, NN(I_mipsisa64)),
   N (64, 64, bfd_mach_mipsisa64r2,"mips:isa64r2", FALSE, NN(I_mipsisa64r2)),
   N (64, 64, bfd_mach_mipsisa64r3,"mips:isa64r3", FALSE, NN(I_mipsisa64r3)),
   N (64, 64, bfd_mach_mipsisa64r5,"mips:isa64r5", FALSE, NN(I_mipsisa64r5)),
+  N (64, 64, bfd_mach_mipsisa64r6,"mips:isa64r6", FALSE, NN(I_mipsisa64r6)),
   N (64, 64, bfd_mach_mips_sb1, "mips:sb1",       FALSE, NN(I_sb1)),
   N (64, 64, bfd_mach_mips_loongson_2e, "mips:loongson_2e",       FALSE, NN(I_loongson_2e)),
   N (64, 64, bfd_mach_mips_loongson_2f, "mips:loongson_2f",       FALSE, NN(I_loongson_2f)),
diff --git a/bfd/elf32-mips.c b/bfd/elf32-mips.c
index af405bc989c..4cfef7a20e0 100644
--- a/bfd/elf32-mips.c
+++ b/bfd/elf32-mips.c
@@ -716,6 +716,99 @@ static reloc_howto_type elf_mips_howto_table_rel[] =
 	 0x0,			/* src_mask */
 	 0xffffffff,		/* dst_mask */
 	 FALSE),		/* pcrel_offset */
+
+  EMPTY_HOWTO (52),
+  EMPTY_HOWTO (53),
+  EMPTY_HOWTO (54),
+  EMPTY_HOWTO (55),
+  EMPTY_HOWTO (56),
+  EMPTY_HOWTO (57),
+  EMPTY_HOWTO (58),
+  EMPTY_HOWTO (59),
+
+  HOWTO (R_MIPS_PC21_S2,	/* type */
+	 2,			/* rightshift */
+	 2,			/* size (0 = byte, 1 = short, 2 = long) */
+	 21,			/* bitsize */
+	 TRUE,			/* pc_relative */
+	 0,			/* bitpos */
+	 complain_overflow_signed, /* complain_on_overflow */
+	 _bfd_mips_elf_generic_reloc, /* special_function */
+	 "R_MIPS_PC21_S2",	/* name */
+	 TRUE,			/* partial_inplace */
+	 0x001fffff,		/* src_mask */
+	 0x001fffff,		/* dst_mask */
+	 TRUE),			/* pcrel_offset */
+
+  HOWTO (R_MIPS_PC26_S2,	/* type */
+	 2,			/* rightshift */
+	 2,			/* size (0 = byte, 1 = short, 2 = long) */
+	 26,			/* bitsize */
+	 TRUE,			/* pc_relative */
+	 0,			/* bitpos */
+	 complain_overflow_signed, /* complain_on_overflow */
+	 _bfd_mips_elf_generic_reloc, /* special_function */
+	 "R_MIPS_PC26_S2",	/* name */
+	 TRUE,			/* partial_inplace */
+	 0x03ffffff,		/* src_mask */
+	 0x03ffffff,		/* dst_mask */
+	 TRUE),			/* pcrel_offset */
+
+  HOWTO (R_MIPS_PC18_S3,	/* type */
+	 3,			/* rightshift */
+	 2,			/* size (0 = byte, 1 = short, 2 = long) */
+	 18,			/* bitsize */
+	 TRUE,			/* pc_relative */
+	 0,			/* bitpos */
+	 complain_overflow_signed, /* complain_on_overflow */
+	 _bfd_mips_elf_generic_reloc,   /* special_function */
+	 "R_MIPS_PC18_S3",	/* name */
+	 TRUE,			/* partial_inplace */
+	 0x0003ffff,		/* src_mask */
+	 0x0003ffff,		/* dst_mask */
+	 TRUE),			/* pcrel_offset */
+
+  HOWTO (R_MIPS_PC19_S2,	/* type */
+	 2,			/* rightshift */
+	 2,			/* size (0 = byte, 1 = short, 2 = long) */
+	 19,			/* bitsize */
+	 TRUE,			/* pc_relative */
+	 0,			/* bitpos */
+	 complain_overflow_signed, /* complain_on_overflow */
+	 _bfd_mips_elf_generic_reloc,   /* special_function */
+	 "R_MIPS_PC19_S2",	/* name */
+	 TRUE,			/* partial_inplace */
+	 0x0007ffff,		/* src_mask */
+	 0x0007ffff,		/* dst_mask */
+	 TRUE),			/* pcrel_offset */
+
+  HOWTO (R_MIPS_PCHI16,		/* type */
+	 16,			/* rightshift */
+	 2,			/* size (0 = byte, 1 = short, 2 = long) */
+	 16,			/* bitsize */
+	 TRUE,			/* pc_relative */
+	 0,			/* bitpos */
+	 complain_overflow_signed, /* complain_on_overflow */
+	 _bfd_mips_elf_generic_reloc,   /* special_function */
+	 "R_MIPS_PCHI16",	/* name */
+	 TRUE,			/* partial_inplace */
+	 0x0000ffff,		/* src_mask */
+	 0x0000ffff,		/* dst_mask */
+	 TRUE),			/* pcrel_offset */
+
+  HOWTO (R_MIPS_PCLO16,		/* type */
+	 0,			/* rightshift */
+	 2,			/* size (0 = byte, 1 = short, 2 = long) */
+	 16,			/* bitsize */
+	 TRUE,			/* pc_relative */
+	 0,			/* bitpos */
+	 complain_overflow_dont, /* complain_on_overflow */
+	 _bfd_mips_elf_generic_reloc,   /* special_function */
+	 "R_MIPS_PCLO16",	/* name */
+	 TRUE,			/* partial_inplace */
+	 0x0000ffff,		/* src_mask */
+	 0x0000ffff,		/* dst_mask */
+	 TRUE),			/* pcrel_offset */
 };
 
 /* The reloc used for BFD_RELOC_CTOR when doing a 64 bit link.  This
@@ -1905,7 +1998,13 @@ static const struct elf_reloc_map mips_reloc_map[] =
   { BFD_RELOC_MIPS_TLS_TPREL32, R_MIPS_TLS_TPREL32 },
   { BFD_RELOC_MIPS_TLS_TPREL64, R_MIPS_TLS_TPREL64 },
   { BFD_RELOC_MIPS_TLS_TPREL_HI16, R_MIPS_TLS_TPREL_HI16 },
-  { BFD_RELOC_MIPS_TLS_TPREL_LO16, R_MIPS_TLS_TPREL_LO16 }
+  { BFD_RELOC_MIPS_TLS_TPREL_LO16, R_MIPS_TLS_TPREL_LO16 },
+  { BFD_RELOC_MIPS_21_PCREL_S2, R_MIPS_PC21_S2 },
+  { BFD_RELOC_MIPS_26_PCREL_S2, R_MIPS_PC26_S2 },
+  { BFD_RELOC_MIPS_18_PCREL_S3, R_MIPS_PC18_S3 },
+  { BFD_RELOC_MIPS_19_PCREL_S2, R_MIPS_PC19_S2 },
+  { BFD_RELOC_HI16_S_PCREL, R_MIPS_PCHI16 },
+  { BFD_RELOC_LO16_PCREL, R_MIPS_PCLO16 }
 };
 
 static const struct elf_reloc_map mips16_reloc_map[] =
diff --git a/bfd/elf64-mips.c b/bfd/elf64-mips.c
index 8662d6663df..2f323c6d7fd 100644
--- a/bfd/elf64-mips.c
+++ b/bfd/elf64-mips.c
@@ -805,6 +805,100 @@ static reloc_howto_type mips_elf64_howto_table_rel[] =
 	 0x0,			/* src_mask */
 	 0xffffffff,		/* dst_mask */
 	 FALSE),		/* pcrel_offset */
+
+  EMPTY_HOWTO (52),
+  EMPTY_HOWTO (53),
+  EMPTY_HOWTO (54),
+  EMPTY_HOWTO (55),
+  EMPTY_HOWTO (56),
+  EMPTY_HOWTO (57),
+  EMPTY_HOWTO (58),
+  EMPTY_HOWTO (59),
+
+  HOWTO (R_MIPS_PC21_S2,	/* type */
+	 2,			/* rightshift */
+	 2,			/* size (0 = byte, 1 = short, 2 = long) */
+	 21,			/* bitsize */
+	 TRUE,			/* pc_relative */
+	 0,			/* bitpos */
+	 complain_overflow_signed, /* complain_on_overflow */
+	 _bfd_mips_elf_generic_reloc, /* special_function */
+	 "R_MIPS_PC21_S2",	/* name */
+	 TRUE,			/* partial_inplace */
+	 0x001fffff,		/* src_mask */
+	 0x001fffff,		/* dst_mask */
+	 TRUE),			/* pcrel_offset */
+
+  HOWTO (R_MIPS_PC26_S2,	/* type */
+	 2,			/* rightshift */
+	 2,			/* size (0 = byte, 1 = short, 2 = long) */
+	 26,			/* bitsize */
+	 TRUE,			/* pc_relative */
+	 0,			/* bitpos */
+	 complain_overflow_signed, /* complain_on_overflow */
+	 _bfd_mips_elf_generic_reloc, /* special_function */
+	 "R_MIPS_PC26_S2",	/* name */
+	 TRUE,			/* partial_inplace */
+	 0x03ffffff,		/* src_mask */
+	 0x03ffffff,		/* dst_mask */
+	 TRUE),			/* pcrel_offset */
+
+  HOWTO (R_MIPS_PC18_S3,	/* type */
+	 3,			/* rightshift */
+	 2,			/* size (0 = byte, 1 = short, 2 = long) */
+	 18,			/* bitsize */
+	 TRUE,			/* pc_relative */
+	 0,			/* bitpos */
+	 complain_overflow_signed, /* complain_on_overflow */
+	 _bfd_mips_elf_generic_reloc,   /* special_function */
+	 "R_MIPS_PC18_S3",	/* name */
+	 TRUE,			/* partial_inplace */
+	 0x0003ffff,		/* src_mask */
+	 0x0003ffff,		/* dst_mask */
+	 TRUE),			/* pcrel_offset */
+
+  HOWTO (R_MIPS_PC19_S2,	/* type */
+	 2,			/* rightshift */
+	 2,			/* size (0 = byte, 1 = short, 2 = long) */
+	 19,			/* bitsize */
+	 TRUE,			/* pc_relative */
+	 0,			/* bitpos */
+	 complain_overflow_signed, /* complain_on_overflow */
+	 _bfd_mips_elf_generic_reloc,   /* special_function */
+	 "R_MIPS_PC19_S2",	/* name */
+	 TRUE,			/* partial_inplace */
+	 0x0007ffff,		/* src_mask */
+	 0x0007ffff,		/* dst_mask */
+	 TRUE),			/* pcrel_offset */
+
+  HOWTO (R_MIPS_PCHI16,		/* type */
+	 16,			/* rightshift */
+	 2,			/* size (0 = byte, 1 = short, 2 = long) */
+	 16,			/* bitsize */
+	 TRUE,			/* pc_relative */
+	 0,			/* bitpos */
+	 complain_overflow_signed, /* complain_on_overflow */
+	 _bfd_mips_elf_generic_reloc,   /* special_function */
+	 "R_MIPS_PCHI16",	/* name */
+	 TRUE,			/* partial_inplace */
+	 0x0000ffff,		/* src_mask */
+	 0x0000ffff,		/* dst_mask */
+	 TRUE),			/* pcrel_offset */
+
+  HOWTO (R_MIPS_PCLO16,		/* type */
+	 0,			/* rightshift */
+	 2,			/* size (0 = byte, 1 = short, 2 = long) */
+	 16,			/* bitsize */
+	 TRUE,			/* pc_relative */
+	 0,			/* bitpos */
+	 complain_overflow_dont, /* complain_on_overflow */
+	 _bfd_mips_elf_generic_reloc,   /* special_function */
+	 "R_MIPS_PCLO16",	/* name */
+	 TRUE,			/* partial_inplace */
+	 0x0000ffff,		/* src_mask */
+	 0x0000ffff,		/* dst_mask */
+	 TRUE),			/* pcrel_offset */
+
 };
 
 /* The relocation table used for SHT_RELA sections.  */
@@ -1492,6 +1586,100 @@ static reloc_howto_type mips_elf64_howto_table_rela[] =
 	 0x0,			/* src_mask */
 	 0xffffffff,		/* dst_mask */
 	 FALSE),		/* pcrel_offset */
+
+  EMPTY_HOWTO (52),
+  EMPTY_HOWTO (53),
+  EMPTY_HOWTO (54),
+  EMPTY_HOWTO (55),
+  EMPTY_HOWTO (56),
+  EMPTY_HOWTO (57),
+  EMPTY_HOWTO (58),
+  EMPTY_HOWTO (59),
+
+  HOWTO (R_MIPS_PC21_S2,	/* type */
+	 2,			/* rightshift */
+	 2,			/* size (0 = byte, 1 = short, 2 = long) */
+	 21,			/* bitsize */
+	 TRUE,			/* pc_relative */
+	 0,			/* bitpos */
+	 complain_overflow_signed, /* complain_on_overflow */
+	 _bfd_mips_elf_generic_reloc, /* special_function */
+	 "R_MIPS_PC21_S2",	/* name */
+	 FALSE,			/* partial_inplace */
+	 0,			/* src_mask */
+	 0x001fffff,		/* dst_mask */
+	 TRUE),			/* pcrel_offset */
+
+  HOWTO (R_MIPS_PC26_S2,	/* type */
+	 2,			/* rightshift */
+	 2,			/* size (0 = byte, 1 = short, 2 = long) */
+	 26,			/* bitsize */
+	 TRUE,			/* pc_relative */
+	 0,			/* bitpos */
+	 complain_overflow_signed, /* complain_on_overflow */
+	 _bfd_mips_elf_generic_reloc, /* special_function */
+	 "R_MIPS_PC26_S2",	/* name */
+	 FALSE,			/* partial_inplace */
+	 0,			/* src_mask */
+	 0x03ffffff,		/* dst_mask */
+	 TRUE),			/* pcrel_offset */
+
+  HOWTO (R_MIPS_PC18_S3,	/* type */
+	 3,			/* rightshift */
+	 2,			/* size (0 = byte, 1 = short, 2 = long) */
+	 18,			/* bitsize */
+	 TRUE,			/* pc_relative */
+	 0,			/* bitpos */
+	 complain_overflow_signed, /* complain_on_overflow */
+	 _bfd_mips_elf_generic_reloc,   /* special_function */
+	 "R_MIPS_PC18_S3",	/* name */
+	 FALSE,			/* partial_inplace */
+	 0,			/* src_mask */
+	 0x0003ffff,		/* dst_mask */
+	 TRUE),			/* pcrel_offset */
+
+  HOWTO (R_MIPS_PC19_S2,	/* type */
+	 2,			/* rightshift */
+	 2,			/* size (0 = byte, 1 = short, 2 = long) */
+	 19,			/* bitsize */
+	 TRUE,			/* pc_relative */
+	 0,			/* bitpos */
+	 complain_overflow_signed, /* complain_on_overflow */
+	 _bfd_mips_elf_generic_reloc,   /* special_function */
+	 "R_MIPS_PC19_S2",	/* name */
+	 FALSE,			/* partial_inplace */
+	 0,			/* src_mask */
+	 0x0007ffff,		/* dst_mask */
+	 TRUE),			/* pcrel_offset */
+
+  HOWTO (R_MIPS_PCHI16,		/* type */
+	 16,			/* rightshift */
+	 2,			/* size (0 = byte, 1 = short, 2 = long) */
+	 16,			/* bitsize */
+	 TRUE,			/* pc_relative */
+	 0,			/* bitpos */
+	 complain_overflow_signed, /* complain_on_overflow */
+	 _bfd_mips_elf_generic_reloc,   /* special_function */
+	 "R_MIPS_PCHI16",	/* name */
+	 FALSE,			/* partial_inplace */
+	 0,			/* src_mask */
+	 0x0000ffff,		/* dst_mask */
+	 TRUE),			/* pcrel_offset */
+
+  HOWTO (R_MIPS_PCLO16,		/* type */
+	 0,			/* rightshift */
+	 2,			/* size (0 = byte, 1 = short, 2 = long) */
+	 16,			/* bitsize */
+	 TRUE,			/* pc_relative */
+	 0,			/* bitpos */
+	 complain_overflow_dont, /* complain_on_overflow */
+	 _bfd_mips_elf_generic_reloc,   /* special_function */
+	 "R_MIPS_PCLO16",	/* name */
+	 FALSE,			/* partial_inplace */
+	 0,			/* src_mask */
+	 0x0000ffff,		/* dst_mask */
+	 TRUE),			/* pcrel_offset */
+
 };
 
 static reloc_howto_type mips16_elf64_howto_table_rel[] =
@@ -3202,7 +3390,13 @@ static const struct elf_reloc_map mips_reloc_map[] =
   { BFD_RELOC_MIPS_TLS_TPREL32, R_MIPS_TLS_TPREL32 },
   { BFD_RELOC_MIPS_TLS_TPREL64, R_MIPS_TLS_TPREL64 },
   { BFD_RELOC_MIPS_TLS_TPREL_HI16, R_MIPS_TLS_TPREL_HI16 },
-  { BFD_RELOC_MIPS_TLS_TPREL_LO16, R_MIPS_TLS_TPREL_LO16 }
+  { BFD_RELOC_MIPS_TLS_TPREL_LO16, R_MIPS_TLS_TPREL_LO16 },
+  { BFD_RELOC_MIPS_21_PCREL_S2, R_MIPS_PC21_S2 },
+  { BFD_RELOC_MIPS_26_PCREL_S2, R_MIPS_PC26_S2 },
+  { BFD_RELOC_MIPS_18_PCREL_S3, R_MIPS_PC18_S3 },
+  { BFD_RELOC_MIPS_19_PCREL_S2, R_MIPS_PC19_S2 },
+  { BFD_RELOC_HI16_S_PCREL, R_MIPS_PCHI16 },
+  { BFD_RELOC_LO16_PCREL, R_MIPS_PCLO16 }
 };
 
 static const struct elf_reloc_map mips16_reloc_map[] =
diff --git a/bfd/elfn32-mips.c b/bfd/elfn32-mips.c
index 1286cc1bb58..9ddde245b2e 100644
--- a/bfd/elfn32-mips.c
+++ b/bfd/elfn32-mips.c
@@ -770,6 +770,100 @@ static reloc_howto_type elf_mips_howto_table_rel[] =
 	 0x0,			/* src_mask */
 	 0xffffffff,		/* dst_mask */
 	 FALSE),		/* pcrel_offset */
+
+  EMPTY_HOWTO (52),
+  EMPTY_HOWTO (53),
+  EMPTY_HOWTO (54),
+  EMPTY_HOWTO (55),
+  EMPTY_HOWTO (56),
+  EMPTY_HOWTO (57),
+  EMPTY_HOWTO (58),
+  EMPTY_HOWTO (59),
+
+  HOWTO (R_MIPS_PC21_S2,	/* type */
+	 2,			/* rightshift */
+	 2,			/* size (0 = byte, 1 = short, 2 = long) */
+	 21,			/* bitsize */
+	 TRUE,			/* pc_relative */
+	 0,			/* bitpos */
+	 complain_overflow_signed, /* complain_on_overflow */
+	 _bfd_mips_elf_generic_reloc, /* special_function */
+	 "R_MIPS_PC21_S2",	/* name */
+	 TRUE,			/* partial_inplace */
+	 0x001fffff,		/* src_mask */
+	 0x001fffff,		/* dst_mask */
+	 TRUE),			/* pcrel_offset */
+
+  HOWTO (R_MIPS_PC26_S2,	/* type */
+	 2,			/* rightshift */
+	 2,			/* size (0 = byte, 1 = short, 2 = long) */
+	 26,			/* bitsize */
+	 TRUE,			/* pc_relative */
+	 0,			/* bitpos */
+	 complain_overflow_signed, /* complain_on_overflow */
+	 _bfd_mips_elf_generic_reloc, /* special_function */
+	 "R_MIPS_PC26_S2",	/* name */
+	 TRUE,			/* partial_inplace */
+	 0x03ffffff,		/* src_mask */
+	 0x03ffffff,		/* dst_mask */
+	 TRUE),			/* pcrel_offset */
+
+  HOWTO (R_MIPS_PC18_S3,	/* type */
+	 3,			/* rightshift */
+	 2,			/* size (0 = byte, 1 = short, 2 = long) */
+	 18,			/* bitsize */
+	 TRUE,			/* pc_relative */
+	 0,			/* bitpos */
+	 complain_overflow_signed, /* complain_on_overflow */
+	 _bfd_mips_elf_generic_reloc,   /* special_function */
+	 "R_MIPS_PC18_S3",	/* name */
+	 TRUE,			/* partial_inplace */
+	 0x0003ffff,		/* src_mask */
+	 0x0003ffff,		/* dst_mask */
+	 TRUE),			/* pcrel_offset */
+
+  HOWTO (R_MIPS_PC19_S2,	/* type */
+	 2,			/* rightshift */
+	 2,			/* size (0 = byte, 1 = short, 2 = long) */
+	 19,			/* bitsize */
+	 TRUE,			/* pc_relative */
+	 0,			/* bitpos */
+	 complain_overflow_signed, /* complain_on_overflow */
+	 _bfd_mips_elf_generic_reloc,   /* special_function */
+	 "R_MIPS_PC19_S2",	/* name */
+	 TRUE,			/* partial_inplace */
+	 0x0007ffff,		/* src_mask */
+	 0x0007ffff,		/* dst_mask */
+	 TRUE),			/* pcrel_offset */
+
+  HOWTO (R_MIPS_PCHI16,		/* type */
+	 16,			/* rightshift */
+	 2,			/* size (0 = byte, 1 = short, 2 = long) */
+	 16,			/* bitsize */
+	 TRUE,			/* pc_relative */
+	 0,			/* bitpos */
+	 complain_overflow_signed, /* complain_on_overflow */
+	 _bfd_mips_elf_generic_reloc,   /* special_function */
+	 "R_MIPS_PCHI16",	/* name */
+	 TRUE,			/* partial_inplace */
+	 0x0000ffff,		/* src_mask */
+	 0x0000ffff,		/* dst_mask */
+	 TRUE),			/* pcrel_offset */
+
+  HOWTO (R_MIPS_PCLO16,		/* type */
+	 0,			/* rightshift */
+	 2,			/* size (0 = byte, 1 = short, 2 = long) */
+	 16,			/* bitsize */
+	 TRUE,			/* pc_relative */
+	 0,			/* bitpos */
+	 complain_overflow_dont, /* complain_on_overflow */
+	 _bfd_mips_elf_generic_reloc,   /* special_function */
+	 "R_MIPS_PCLO16",	/* name */
+	 TRUE,			/* partial_inplace */
+	 0x0000ffff,		/* src_mask */
+	 0x0000ffff,		/* dst_mask */
+	 TRUE),			/* pcrel_offset */
+
 };
 
 /* The relocation table used for SHT_RELA sections.  */
@@ -1458,6 +1552,100 @@ static reloc_howto_type elf_mips_howto_table_rela[] =
 	 0x0,			/* src_mask */
 	 0xffffffff,		/* dst_mask */
 	 FALSE),		/* pcrel_offset */
+
+  EMPTY_HOWTO (52),
+  EMPTY_HOWTO (53),
+  EMPTY_HOWTO (54),
+  EMPTY_HOWTO (55),
+  EMPTY_HOWTO (56),
+  EMPTY_HOWTO (57),
+  EMPTY_HOWTO (58),
+  EMPTY_HOWTO (59),
+
+  HOWTO (R_MIPS_PC21_S2,	/* type */
+	 2,			/* rightshift */
+	 2,			/* size (0 = byte, 1 = short, 2 = long) */
+	 21,			/* bitsize */
+	 TRUE,			/* pc_relative */
+	 0,			/* bitpos */
+	 complain_overflow_signed, /* complain_on_overflow */
+	 _bfd_mips_elf_generic_reloc, /* special_function */
+	 "R_MIPS_PC21_S2",	/* name */
+	 FALSE,			/* partial_inplace */
+	 0,			/* src_mask */
+	 0x001fffff,		/* dst_mask */
+	 TRUE),			/* pcrel_offset */
+
+  HOWTO (R_MIPS_PC26_S2,	/* type */
+	 2,			/* rightshift */
+	 2,			/* size (0 = byte, 1 = short, 2 = long) */
+	 26,			/* bitsize */
+	 TRUE,			/* pc_relative */
+	 0,			/* bitpos */
+	 complain_overflow_signed, /* complain_on_overflow */
+	 _bfd_mips_elf_generic_reloc, /* special_function */
+	 "R_MIPS_PC26_S2",	/* name */
+	 FALSE,			/* partial_inplace */
+	 0,			/* src_mask */
+	 0x03ffffff,		/* dst_mask */
+	 TRUE),			/* pcrel_offset */
+
+  HOWTO (R_MIPS_PC18_S3,	/* type */
+	 3,			/* rightshift */
+	 2,			/* size (0 = byte, 1 = short, 2 = long) */
+	 18,			/* bitsize */
+	 TRUE,			/* pc_relative */
+	 0,			/* bitpos */
+	 complain_overflow_signed, /* complain_on_overflow */
+	 _bfd_mips_elf_generic_reloc,   /* special_function */
+	 "R_MIPS_PC18_S3",	/* name */
+	 FALSE,			/* partial_inplace */
+	 0,			/* src_mask */
+	 0x0003ffff,		/* dst_mask */
+	 TRUE),			/* pcrel_offset */
+
+  HOWTO (R_MIPS_PC19_S2,	/* type */
+	 2,			/* rightshift */
+	 2,			/* size (0 = byte, 1 = short, 2 = long) */
+	 19,			/* bitsize */
+	 TRUE,			/* pc_relative */
+	 0,			/* bitpos */
+	 complain_overflow_signed, /* complain_on_overflow */
+	 _bfd_mips_elf_generic_reloc,   /* special_function */
+	 "R_MIPS_PC19_S2",	/* name */
+	 FALSE,			/* partial_inplace */
+	 0,			/* src_mask */
+	 0x0007ffff,		/* dst_mask */
+	 TRUE),			/* pcrel_offset */
+
+  HOWTO (R_MIPS_PCHI16,		/* type */
+	 16,			/* rightshift */
+	 2,			/* size (0 = byte, 1 = short, 2 = long) */
+	 16,			/* bitsize */
+	 TRUE,			/* pc_relative */
+	 0,			/* bitpos */
+	 complain_overflow_signed, /* complain_on_overflow */
+	 _bfd_mips_elf_generic_reloc,   /* special_function */
+	 "R_MIPS_PCHI16",	/* name */
+	 FALSE,			/* partial_inplace */
+	 0,			/* src_mask */
+	 0x0000ffff,		/* dst_mask */
+	 TRUE),			/* pcrel_offset */
+
+  HOWTO (R_MIPS_PCLO16,		/* type */
+	 0,			/* rightshift */
+	 2,			/* size (0 = byte, 1 = short, 2 = long) */
+	 16,			/* bitsize */
+	 TRUE,			/* pc_relative */
+	 0,			/* bitpos */
+	 complain_overflow_dont, /* complain_on_overflow */
+	 _bfd_mips_elf_generic_reloc,   /* special_function */
+	 "R_MIPS_PCLO16",	/* name */
+	 FALSE,			/* partial_inplace */
+	 0,			/* src_mask */
+	 0x0000ffff,		/* dst_mask */
+	 TRUE),			/* pcrel_offset */
+
 };
 
 static reloc_howto_type elf_mips16_howto_table_rel[] =
@@ -3018,7 +3206,13 @@ static const struct elf_reloc_map mips_reloc_map[] =
   { BFD_RELOC_MIPS_TLS_TPREL32, R_MIPS_TLS_TPREL32 },
   { BFD_RELOC_MIPS_TLS_TPREL64, R_MIPS_TLS_TPREL64 },
   { BFD_RELOC_MIPS_TLS_TPREL_HI16, R_MIPS_TLS_TPREL_HI16 },
-  { BFD_RELOC_MIPS_TLS_TPREL_LO16, R_MIPS_TLS_TPREL_LO16 }
+  { BFD_RELOC_MIPS_TLS_TPREL_LO16, R_MIPS_TLS_TPREL_LO16 },
+  { BFD_RELOC_MIPS_21_PCREL_S2, R_MIPS_PC21_S2 },
+  { BFD_RELOC_MIPS_26_PCREL_S2, R_MIPS_PC26_S2 },
+  { BFD_RELOC_MIPS_18_PCREL_S3, R_MIPS_PC18_S3 },
+  { BFD_RELOC_MIPS_19_PCREL_S2, R_MIPS_PC19_S2 },
+  { BFD_RELOC_HI16_S_PCREL, R_MIPS_PCHI16 },
+  { BFD_RELOC_LO16_PCREL, R_MIPS_PCLO16 }
 };
 
 static const struct elf_reloc_map mips16_reloc_map[] =
diff --git a/bfd/elfxx-mips.c b/bfd/elfxx-mips.c
index ee0204d8d6c..2c7b35f113e 100644
--- a/bfd/elfxx-mips.c
+++ b/bfd/elfxx-mips.c
@@ -799,6 +799,11 @@ static bfd *reldyn_sorting_bfd;
 #define MICROMIPS_P(abfd) \
   ((elf_elfheader (abfd)->e_flags & EF_MIPS_ARCH_ASE_MICROMIPS) != 0)
 
+/* Nonzero if ABFD is MIPS R6.  */
+#define MIPSR6_P(abfd) \
+  ((elf_elfheader (abfd)->e_flags & EF_MIPS_ARCH) == E_MIPS_ARCH_32R6 \
+    || (elf_elfheader (abfd)->e_flags & EF_MIPS_ARCH) == E_MIPS_ARCH_64R6)
+
 /* The IRIX compatibility level we are striving for.  */
 #define IRIX_COMPAT(abfd) \
   (get_elf_backend_data (abfd)->elf_backend_mips_irix_compat (abfd))
@@ -1100,6 +1105,17 @@ static const bfd_vma mips_exec_plt_entry[] =
   0x03200008	/* jr $25					*/
 };
 
+/* In the following PLT entry the JR and ADDIU instructions will
+   be swapped in _bfd_mips_elf_finish_dynamic_symbol because
+   LOAD_INTERLOCKS_P will be true for MIPS R6.  */
+static const bfd_vma mipsr6_exec_plt_entry[] =
+{
+  0x3c0f0000,	/* lui $15, %hi(.got.plt entry)			*/
+  0x01f90000,	/* l[wd] $25, %lo(.got.plt entry)($15)		*/
+  0x25f80000,	/* addiu $24, $15, %lo(.got.plt entry)		*/
+  0x03200009	/* jr $25					*/
+};
+
 /* The format of subsequent MIPS16 o32 PLT entries.  We use v0 ($2)
    and v1 ($3) as temporaries because t8 ($24) and t9 ($25) are not
    directly addressable.  */
@@ -2180,7 +2196,8 @@ hi16_reloc_p (int r_type)
 {
   return (r_type == R_MIPS_HI16
 	  || r_type == R_MIPS16_HI16
-	  || r_type == R_MICROMIPS_HI16);
+	  || r_type == R_MICROMIPS_HI16
+	  || r_type == R_MIPS_PCHI16);
 }
 
 static inline bfd_boolean
@@ -2188,7 +2205,8 @@ lo16_reloc_p (int r_type)
 {
   return (r_type == R_MIPS_LO16
 	  || r_type == R_MIPS16_LO16
-	  || r_type == R_MICROMIPS_LO16);
+	  || r_type == R_MICROMIPS_LO16
+	  || r_type == R_MIPS_PCLO16);
 }
 
 static inline bfd_boolean
@@ -2206,6 +2224,13 @@ jal_reloc_p (int r_type)
 }
 
 static inline bfd_boolean
+aligned_pcrel_reloc_p (int r_type)
+{
+  return (r_type == R_MIPS_PC18_S3
+	  || r_type == R_MIPS_PC19_S2);
+}
+
+static inline bfd_boolean
 micromips_branch_reloc_p (int r_type)
 {
   return (r_type == R_MICROMIPS_26_S1
@@ -5161,6 +5186,8 @@ mips_elf_relocation_needs_la25_stub (bfd *input_bfd, int r_type,
     {
     case R_MIPS_26:
     case R_MIPS_PC16:
+    case R_MIPS_PC21_S2:
+    case R_MIPS_PC26_S2:
     case R_MICROMIPS_26_S1:
     case R_MICROMIPS_PC7_S1:
     case R_MICROMIPS_PC10_S1:
@@ -5951,6 +5978,71 @@ mips_elf_calculate_relocation (bfd *abfd, bfd *input_bfd,
       value &= howto->dst_mask;
       break;
 
+    case R_MIPS_PC21_S2:
+      if (howto->partial_inplace)
+	addend = _bfd_mips_elf_sign_extend (addend, 23);
+
+      if ((symbol + addend) & 3)
+	return bfd_reloc_outofrange;
+
+      value = symbol + addend - p;
+      overflowed_p = mips_elf_overflow_p (value, 23);
+      value >>= howto->rightshift;
+      value &= howto->dst_mask;
+      break;
+
+    case R_MIPS_PC26_S2:
+      if (howto->partial_inplace)
+	addend = _bfd_mips_elf_sign_extend (addend, 28);
+
+      if ((symbol + addend) & 3)
+	return bfd_reloc_outofrange;
+
+      value = symbol + addend - p;
+      overflowed_p = mips_elf_overflow_p (value, 28);
+      value >>= howto->rightshift;
+      value &= howto->dst_mask;
+      break;
+
+    case R_MIPS_PC18_S3:
+      if (howto->partial_inplace)
+	addend = _bfd_mips_elf_sign_extend (addend, 21);
+
+      if ((symbol + addend) & 7)
+	return bfd_reloc_outofrange;
+
+      value = symbol + addend - ((p | 7) ^ 7);
+      overflowed_p = mips_elf_overflow_p (value, 21);
+      value >>= howto->rightshift;
+      value &= howto->dst_mask;
+      break;
+
+    case R_MIPS_PC19_S2:
+      if (howto->partial_inplace)
+	addend = _bfd_mips_elf_sign_extend (addend, 21);
+
+      if ((symbol + addend) & 3)
+	return bfd_reloc_outofrange;
+
+      value = symbol + addend - p;
+      overflowed_p = mips_elf_overflow_p (value, 21);
+      value >>= howto->rightshift;
+      value &= howto->dst_mask;
+      break;
+
+    case R_MIPS_PCHI16:
+      value = mips_elf_high (symbol + addend - p);
+      overflowed_p = mips_elf_overflow_p (value, 16);
+      value &= howto->dst_mask;
+      break;
+
+    case R_MIPS_PCLO16:
+      if (howto->partial_inplace)
+	addend = _bfd_mips_elf_sign_extend (addend, 16);
+      value = symbol + addend - p;
+      value &= howto->dst_mask;
+      break;
+
     case R_MICROMIPS_PC7_S1:
       value = symbol + _bfd_mips_elf_sign_extend (addend, 8) - p;
       overflowed_p = mips_elf_overflow_p (value, 8);
@@ -6517,6 +6609,12 @@ _bfd_elf_mips_mach (flagword flags)
 
 	case E_MIPS_ARCH_64R2:
 	  return bfd_mach_mipsisa64r2;
+
+	case E_MIPS_ARCH_32R6:
+	  return bfd_mach_mipsisa32r6;
+
+	case E_MIPS_ARCH_64R6:
+	  return bfd_mach_mipsisa64r6;
 	}
     }
 
@@ -7693,6 +7791,8 @@ mips_elf_add_lo16_rel_addend (bfd *abfd,
     lo16_type = R_MIPS16_LO16;
   else if (micromips_reloc_p (r_type))
     lo16_type = R_MICROMIPS_LO16;
+  else if (r_type == R_MIPS_PCHI16)
+    lo16_type = R_MIPS_PCLO16;
   else
     lo16_type = R_MIPS_LO16;
 
@@ -8205,6 +8305,8 @@ _bfd_mips_elf_check_relocs (bfd *abfd, struct bfd_link_info *info,
 
 	case R_MIPS_26:
 	case R_MIPS_PC16:
+	case R_MIPS_PC21_S2:
+	case R_MIPS_PC26_S2:
 	case R_MIPS16_26:
 	case R_MICROMIPS_26_S1:
 	case R_MICROMIPS_PC7_S1:
@@ -10129,6 +10231,13 @@ _bfd_mips_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
 		(info, msg, name, input_bfd, input_section, rel->r_offset);
 	      return FALSE;
 	    }
+	  if (aligned_pcrel_reloc_p (howto->type))
+	    {
+	      msg = _("PC-relative load from unaligned address");
+	      info->callbacks->warning
+		(info, msg, name, input_bfd, input_section, rel->r_offset);
+	      return FALSE;
+	    }
 	  /* Fall through.  */
 
 	default:
@@ -10418,7 +10527,11 @@ _bfd_mips_elf_finish_dynamic_symbol (bfd *output_bfd,
 	  load = MIPS_ELF_LOAD_WORD (output_bfd);
 
 	  /* Fill in the PLT entry itself.  */
-	  plt_entry = mips_exec_plt_entry;
+
+	  if (MIPSR6_P (output_bfd))
+	    plt_entry = mipsr6_exec_plt_entry;
+	  else
+	    plt_entry = mips_exec_plt_entry;
 	  bfd_put_32 (output_bfd, plt_entry[0] | got_address_high, loc);
 	  bfd_put_32 (output_bfd, plt_entry[1] | got_address_low | load,
 		      loc + 4);
@@ -11755,6 +11868,14 @@ mips_set_isa_flags (bfd *abfd)
     case bfd_mach_mipsisa64r5:
       val = E_MIPS_ARCH_64R2;
       break;
+
+    case bfd_mach_mipsisa32r6:
+      val = E_MIPS_ARCH_32R6;
+      break;
+
+    case bfd_mach_mipsisa64r6:
+      val = E_MIPS_ARCH_64R6;
+      break;
     }
   elf_elfheader (abfd)->e_flags &= ~(EF_MIPS_ARCH | EF_MIPS_MACH);
   elf_elfheader (abfd)->e_flags |= val;
@@ -13839,7 +13960,8 @@ mips_32bit_flags_p (flagword flags)
 	  || (flags & EF_MIPS_ARCH) == E_MIPS_ARCH_1
 	  || (flags & EF_MIPS_ARCH) == E_MIPS_ARCH_2
 	  || (flags & EF_MIPS_ARCH) == E_MIPS_ARCH_32
-	  || (flags & EF_MIPS_ARCH) == E_MIPS_ARCH_32R2);
+	  || (flags & EF_MIPS_ARCH) == E_MIPS_ARCH_32R2
+	  || (flags & EF_MIPS_ARCH) == E_MIPS_ARCH_32R6);
 }
 
 /* Infer the content of the ABI flags based on the elf header.  */
@@ -15528,6 +15650,10 @@ _bfd_mips_elf_print_private_bfd_data (bfd *abfd, void *ptr)
     fprintf (file, " [mips32r2]");
   else if ((elf_elfheader (abfd)->e_flags & EF_MIPS_ARCH) == E_MIPS_ARCH_64R2)
     fprintf (file, " [mips64r2]");
+  else if ((elf_elfheader (abfd)->e_flags & EF_MIPS_ARCH) == E_MIPS_ARCH_32R6)
+    fprintf (file, " [mips32r6]");
+  else if ((elf_elfheader (abfd)->e_flags & EF_MIPS_ARCH) == E_MIPS_ARCH_64R6)
+    fprintf (file, " [mips64r6]");
   else
     fprintf (file, _(" [unknown ISA]"));
 
diff --git a/bfd/libbfd.h b/bfd/libbfd.h
index f759a0a1755..c0f4e96b38a 100644
--- a/bfd/libbfd.h
+++ b/bfd/libbfd.h
@@ -1126,6 +1126,10 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@",
   "BFD_RELOC_MICROMIPS_7_PCREL_S1",
   "BFD_RELOC_MICROMIPS_10_PCREL_S1",
   "BFD_RELOC_MICROMIPS_16_PCREL_S1",
+  "BFD_RELOC_MIPS_21_PCREL_S2",
+  "BFD_RELOC_MIPS_26_PCREL_S2",
+  "BFD_RELOC_MIPS_18_PCREL_S3",
+  "BFD_RELOC_MIPS_19_PCREL_S2",
   "BFD_RELOC_MICROMIPS_GPREL16",
   "BFD_RELOC_MICROMIPS_HI16",
   "BFD_RELOC_MICROMIPS_HI16_S",
diff --git a/bfd/reloc.c b/bfd/reloc.c
index 86ff2cd7a20..79079cf056c 100644
--- a/bfd/reloc.c
+++ b/bfd/reloc.c
@@ -2289,6 +2289,17 @@ ENUMDOC
   microMIPS PC-relative relocations.
 
 ENUM
+  BFD_RELOC_MIPS_21_PCREL_S2
+ENUMX
+  BFD_RELOC_MIPS_26_PCREL_S2
+ENUMX
+  BFD_RELOC_MIPS_18_PCREL_S3
+ENUMX
+  BFD_RELOC_MIPS_19_PCREL_S2
+ENUMDOC
+  MIPS PC-relative relocations.
+
+ENUM
   BFD_RELOC_MICROMIPS_GPREL16
 ENUMX
   BFD_RELOC_MICROMIPS_HI16
diff --git a/binutils/ChangeLog b/binutils/ChangeLog
index 693e155048a..ea632186181 100644
--- a/binutils/ChangeLog
+++ b/binutils/ChangeLog
@@ -1,3 +1,9 @@
+2014-09-15  Andrew Bennett  <andrew.bennett@imgtec.com>
+	    Matthew Fortune  <matthew.fortune@imgtec.com>
+
+	* readelf.c (get_machine_flags): Add support for mips32r6 and
+	mips64r6.
+
 2014-09-01  Jon TURNEY  <jon.turney@dronecode.org.uk>
 
 	* objcopy.c (is_nondebug_keep_contents_section): Change
diff --git a/binutils/readelf.c b/binutils/readelf.c
index 7463c558b45..f7eaf7c9760 100644
--- a/binutils/readelf.c
+++ b/binutils/readelf.c
@@ -2848,8 +2848,10 @@ get_machine_flags (unsigned e_flags, unsigned e_machine)
 	    case E_MIPS_ARCH_5: strcat (buf, ", mips5"); break;
 	    case E_MIPS_ARCH_32: strcat (buf, ", mips32"); break;
 	    case E_MIPS_ARCH_32R2: strcat (buf, ", mips32r2"); break;
+	    case E_MIPS_ARCH_32R6: strcat (buf, ", mips32r6"); break;
 	    case E_MIPS_ARCH_64: strcat (buf, ", mips64"); break;
 	    case E_MIPS_ARCH_64R2: strcat (buf, ", mips64r2"); break;
+	    case E_MIPS_ARCH_64R6: strcat (buf, ", mips64r6"); break;
 	    default: strcat (buf, _(", unknown ISA")); break;
 	    }
 	  break;
diff --git a/elfcpp/ChangeLog b/elfcpp/ChangeLog
index b554287d672..01bb1017fdb 100644
--- a/elfcpp/ChangeLog
+++ b/elfcpp/ChangeLog
@@ -1,3 +1,8 @@
+2014-09-15  Andrew Bennett  <andrew.bennett@imgtec.com>
+	    Matthew Fortune  <matthew.fortune@imgtec.com>
+
+	* mips.h (E_MIPS_ARCH_32R6, E_MIPS_ARCH_64R6): New enum constants.
+
 2014-09-02  Cary Coutant  <ccoutant@google.com>
 
 	* elfcpp_file.h (Elf_file::shnum): New const function.
diff --git a/elfcpp/mips.h b/elfcpp/mips.h
index ccb017f7370..a59c3e24b61 100644
--- a/elfcpp/mips.h
+++ b/elfcpp/mips.h
@@ -250,6 +250,10 @@ enum
   E_MIPS_ARCH_32R2 = 0x70000000,
   // -mips64r2 code.
   E_MIPS_ARCH_64R2 = 0x80000000,
+  // -mips32r6 code.
+  E_MIPS_ARCH_32R6 = 0x90000000,
+  // -mips64r6 code.
+  E_MIPS_ARCH_64R6 = 0xa0000000,
 };
 
 enum
diff --git a/gas/ChangeLog b/gas/ChangeLog
index 84c90c8a9b0..3f499cc83e7 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,76 @@
+2014-09-15  Andrew Bennett  <andrew.bennett@imgtec.com>
+	    Matthew Fortune  <matthew.fortune@imgtec.com>
+
+	* config/tc-mips.c (mips_nan2008): New static global.
+	(mips_flag_nan2008): Removed.
+	(LL_SC_FMT): New define.
+	(COP12_FMT): Updated.
+	(ISA_IS_R6): New define.
+	(ISA_HAS_64BIT_REGS): Add mips64r6.
+	(ISA_HAS_DROR): Likewise.
+	(ISA_HAS_64BIT_FPRS): Add mips32r6 and mips64r6.
+	(ISA_HAS_ROR): Likewise.
+	(ISA_HAS_ODD_SINGLE_FPR): Likewise.
+	(ISA_HAS_MXHC1): Likewise.
+	(hilo_interlocks): Likewise.
+	(md_longopts): Likewise.
+	(ISA_HAS_LEGACY_NAN): New define.
+	(options): Add OPTION_MIPS32R6 and OPTION_MIPS64R6.
+	(mips_ase): Add field rem_rev.
+	(mips_ases): Updated to add which ISA an ASE was removed in.
+	(mips_isa_rev): Add support for mips32r6 and mips64r6.
+	(mips_check_isa_supports_ase): Add support to check if an ASE
+	has been removed in the specified MIPS ISA revision.
+	(validate_mips_insn): Skip '-' character.
+	(macro_build): Likewise.
+	(mips_check_options): Prevent R6 working with fp32, mips16,
+	micromips, or branch relaxation.
+	(file_mips_check_options): Set R6 floating point registers to
+	64 bit.  Also deal with the nan2008 option.
+	(limited_pcrel_reloc_p): Add relocs: BFD_RELOC_MIPS_21_PCREL_S2,
+	BFD_RELOC_MIPS_26_PCREL_S2, BFD_RELOC_MIPS_18_PCREL_S3,
+	BFD_RELOC_MIPS_19_PCREL_S2, BFD_RELOC_HI16_S_PCREL and
+	BFD_RELOC_LO16_PCREL.
+	(operand_reg_mask): Add support for OP_SAME_RS_RT, OP_CHECK_PREV
+	and OP_NON_ZERO_REG.
+	(match_check_prev_operand): New static function.
+	(match_same_rs_rt_operand): New static function.
+	(match_non_zero_reg_operand): New static function.
+	(match_operand): Added entries for: OP_SAME_RS_RT, OP_CHECK_PREV
+	and OP_NON_ZERO_REG.
+	(insns_between): Added case to deal with forbidden slots.
+	(append_insn): Added support for relocs: BFD_RELOC_MIPS_21_PCREL_S2
+	and BFD_RELOC_MIPS_26_PCREL_S2.
+	(match_insn): Add support for operands -A, -B, +' and +".  Also
+	skip '-' character.
+	(mips_percent_op): Add entries for %pcrel_hi and %pcrel_lo.
+	(md_parse_option): Add support for mips32r6 and mips64r6.  Also
+	update the nan option handling.
+	(md_pcrel_from): Add cases for relocs: BFD_RELOC_MIPS_21_PCREL_S2,
+	BFD_RELOC_MIPS_26_PCREL_S2.
+	(mips_force_relocation): Prevent forced relaxation for MIPS r6.
+	(md_apply_fix): Add support for relocs: BFD_RELOC_MIPS_21_PCREL_S2,
+	BFD_RELOC_MIPS_26_PCREL_S2, BFD_RELOC_MIPS_18_PCREL_S3,
+	BFD_RELOC_MIPS_19_PCREL_S2, BFD_RELOC_HI16_S_PCREL and
+	BFD_RELOC_LO16_PCREL.
+	(s_mipsset): Add support for mips32r6 and mips64r6.
+	(s_nan): Update to support the new nan2008 framework.
+	(tc_gen_reloc): Add relocs: BFD_RELOC_MIPS_21_PCREL_S2,
+	BFD_RELOC_MIPS_26_PCREL_S2, BFD_RELOC_MIPS_18_PCREL_S3,
+	BFD_RELOC_MIPS_19_PCREL_S2, BFD_RELOC_HI16_S_PCREL and
+	BFD_RELOC_LO16_PCREL.
+	(mips_elf_final_processing): Updated to use the mips_nan2008.
+	(mips_cpu_info_table): Add entries for mips32r6 and mips64r6.
+	(macro): Enable ldc2, sdc2, ll, lld, swc2, sc, scd, cache, pref
+	macros for R6.
+	(mips_fix_adjustable): Make PC relative R6 relocations relative
+	to the symbol and not the section.
+	* configure.ac: Add support for mips32r6 and mips64r6.
+	* configure: Regenerate.
+	* doc/c-mips.texi: Document the -mips32r6 and -mips64r6 command line
+	options.
+	* doc/as.texinfo: Likewise.
+
 2014-09-15  Matthew Fortune  <matthew.fortune@imgtec.com>
 
 	* tc-mips.c (check_fpabi): Move softfloat and singlefloat
diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c
index 2dabdf449b1..8d4a80bb182 100644
--- a/gas/config/tc-mips.c
+++ b/gas/config/tc-mips.c
@@ -267,8 +267,11 @@ struct mips_set_options
 /* Specifies whether module level options have been checked yet.  */
 static bfd_boolean file_mips_opts_checked = FALSE;
 
-/* True if -mnan=2008, false if -mnan=legacy.  */
-static bfd_boolean mips_flag_nan2008 = FALSE;
+/* Do we support nan2008?  0 if we don't, 1 if we do, and -1 if the
+   value has not been initialized.  Changed by `.nan legacy' and
+   `.nan 2008', and the -mnan=legacy and -mnan=2008 command line
+   options, and the default CPU.  */
+static int mips_nan2008 = -1;
 
 /* This is the struct we use to hold the module level set of options.
    Note that we must set the isa field to ISA_UNKNOWN and the ASE, gp and
@@ -350,6 +353,10 @@ static int mips_32bitmode = 0;
    || (ABI) == N64_ABI			\
    || (ABI) == O64_ABI)
 
+#define ISA_IS_R6(ISA)			\
+  ((ISA) == ISA_MIPS32R6		\
+   || (ISA) == ISA_MIPS64R6)
+
 /*  Return true if ISA supports 64 bit wide gp registers.  */
 #define ISA_HAS_64BIT_REGS(ISA)		\
   ((ISA) == ISA_MIPS3			\
@@ -358,7 +365,8 @@ static int mips_32bitmode = 0;
    || (ISA) == ISA_MIPS64		\
    || (ISA) == ISA_MIPS64R2		\
    || (ISA) == ISA_MIPS64R3		\
-   || (ISA) == ISA_MIPS64R5)
+   || (ISA) == ISA_MIPS64R5		\
+   || (ISA) == ISA_MIPS64R6)
 
 /*  Return true if ISA supports 64 bit wide float registers.  */
 #define ISA_HAS_64BIT_FPRS(ISA)		\
@@ -368,10 +376,12 @@ static int mips_32bitmode = 0;
    || (ISA) == ISA_MIPS32R2		\
    || (ISA) == ISA_MIPS32R3		\
    || (ISA) == ISA_MIPS32R5		\
+   || (ISA) == ISA_MIPS32R6		\
    || (ISA) == ISA_MIPS64		\
    || (ISA) == ISA_MIPS64R2		\
    || (ISA) == ISA_MIPS64R3		\
-   || (ISA) == ISA_MIPS64R5		)
+   || (ISA) == ISA_MIPS64R5		\
+   || (ISA) == ISA_MIPS64R6)
 
 /* Return true if ISA supports 64-bit right rotate (dror et al.)
    instructions.  */
@@ -379,6 +389,7 @@ static int mips_32bitmode = 0;
   ((ISA) == ISA_MIPS64R2		\
    || (ISA) == ISA_MIPS64R3		\
    || (ISA) == ISA_MIPS64R5		\
+   || (ISA) == ISA_MIPS64R6		\
    || (mips_opts.micromips		\
        && ISA_HAS_64BIT_REGS (ISA))	\
    )
@@ -389,9 +400,11 @@ static int mips_32bitmode = 0;
   ((ISA) == ISA_MIPS32R2		\
    || (ISA) == ISA_MIPS32R3		\
    || (ISA) == ISA_MIPS32R5		\
+   || (ISA) == ISA_MIPS32R6		\
    || (ISA) == ISA_MIPS64R2		\
    || (ISA) == ISA_MIPS64R3		\
    || (ISA) == ISA_MIPS64R5		\
+   || (ISA) == ISA_MIPS64R6		\
    || (mips_opts.ase & ASE_SMARTMIPS)	\
    || mips_opts.micromips		\
    )
@@ -402,10 +415,12 @@ static int mips_32bitmode = 0;
     || (ISA) == ISA_MIPS32R2		\
     || (ISA) == ISA_MIPS32R3		\
     || (ISA) == ISA_MIPS32R5		\
+    || (ISA) == ISA_MIPS32R6		\
     || (ISA) == ISA_MIPS64		\
     || (ISA) == ISA_MIPS64R2		\
     || (ISA) == ISA_MIPS64R3		\
     || (ISA) == ISA_MIPS64R5		\
+    || (ISA) == ISA_MIPS64R6		\
     || (CPU) == CPU_R5900)		\
    && (CPU) != CPU_LOONGSON_3A)
 
@@ -415,6 +430,24 @@ static int mips_32bitmode = 0;
   ((ISA) == ISA_MIPS32R2		\
    || (ISA) == ISA_MIPS32R3		\
    || (ISA) == ISA_MIPS32R5		\
+   || (ISA) == ISA_MIPS32R6		\
+   || (ISA) == ISA_MIPS64R2		\
+   || (ISA) == ISA_MIPS64R3		\
+   || (ISA) == ISA_MIPS64R5		\
+   || (ISA) == ISA_MIPS64R6)
+
+/*  Return true if ISA supports legacy NAN.  */
+#define ISA_HAS_LEGACY_NAN(ISA)		\
+  ((ISA) == ISA_MIPS1			\
+   || (ISA) == ISA_MIPS2		\
+   || (ISA) == ISA_MIPS3		\
+   || (ISA) == ISA_MIPS4		\
+   || (ISA) == ISA_MIPS5		\
+   || (ISA) == ISA_MIPS32		\
+   || (ISA) == ISA_MIPS32R2		\
+   || (ISA) == ISA_MIPS32R3		\
+   || (ISA) == ISA_MIPS32R5		\
+   || (ISA) == ISA_MIPS64		\
    || (ISA) == ISA_MIPS64R2		\
    || (ISA) == ISA_MIPS64R3		\
    || (ISA) == ISA_MIPS64R5)
@@ -503,10 +536,12 @@ static int mips_32bitmode = 0;
    || mips_opts.isa == ISA_MIPS32R2                   \
    || mips_opts.isa == ISA_MIPS32R3                   \
    || mips_opts.isa == ISA_MIPS32R5                   \
+   || mips_opts.isa == ISA_MIPS32R6                   \
    || mips_opts.isa == ISA_MIPS64                     \
    || mips_opts.isa == ISA_MIPS64R2                   \
    || mips_opts.isa == ISA_MIPS64R3                   \
    || mips_opts.isa == ISA_MIPS64R5                   \
+   || mips_opts.isa == ISA_MIPS64R6                   \
    || mips_opts.arch == CPU_R4010                     \
    || mips_opts.arch == CPU_R5900                     \
    || mips_opts.arch == CPU_R10000                    \
@@ -1351,9 +1386,11 @@ enum options
     OPTION_MIPS32R2,
     OPTION_MIPS32R3,
     OPTION_MIPS32R5,
+    OPTION_MIPS32R6,
     OPTION_MIPS64R2,
     OPTION_MIPS64R3,
     OPTION_MIPS64R5,
+    OPTION_MIPS64R6,
     OPTION_MIPS16,
     OPTION_NO_MIPS16,
     OPTION_MIPS3D,
@@ -1463,9 +1500,11 @@ struct option md_longopts[] =
   {"mips32r2", no_argument, NULL, OPTION_MIPS32R2},
   {"mips32r3", no_argument, NULL, OPTION_MIPS32R3},
   {"mips32r5", no_argument, NULL, OPTION_MIPS32R5},
+  {"mips32r6", no_argument, NULL, OPTION_MIPS32R6},
   {"mips64r2", no_argument, NULL, OPTION_MIPS64R2},
   {"mips64r3", no_argument, NULL, OPTION_MIPS64R3},
   {"mips64r5", no_argument, NULL, OPTION_MIPS64R5},
+  {"mips64r6", no_argument, NULL, OPTION_MIPS64R6},
 
   /* Options which specify Application Specific Extensions (ASEs).  */
   {"mips16", no_argument, NULL, OPTION_MIPS16},
@@ -1605,55 +1644,70 @@ struct mips_ase
   int mips64_rev;
   int micromips32_rev;
   int micromips64_rev;
+
+  /* The architecture where the ASE was removed or -1 if the extension has not
+     been removed.  */
+  int rem_rev;
 };
 
 /* A table of all supported ASEs.  */
 static const struct mips_ase mips_ases[] = {
   { "dsp", ASE_DSP, ASE_DSP64,
     OPTION_DSP, OPTION_NO_DSP,
-    2, 2, 2, 2 },
+    2, 2, 2, 2,
+    -1 },
 
   { "dspr2", ASE_DSP | ASE_DSPR2, 0,
     OPTION_DSPR2, OPTION_NO_DSPR2,
-    2, 2, 2, 2 },
+    2, 2, 2, 2,
+    -1 },
 
   { "eva", ASE_EVA, 0,
     OPTION_EVA, OPTION_NO_EVA,
-    2, 2, 2, 2 },
+     2,  2,  2,  2,
+    -1 },
 
   { "mcu", ASE_MCU, 0,
     OPTION_MCU, OPTION_NO_MCU,
-    2, 2, 2, 2 },
+     2,  2,  2,  2,
+    -1 },
 
   /* Deprecated in MIPS64r5, but we don't implement that yet.  */
   { "mdmx", ASE_MDMX, 0,
     OPTION_MDMX, OPTION_NO_MDMX,
-    -1, 1, -1, -1 },
+    -1, 1, -1, -1,
+     6 },
 
   /* Requires 64-bit FPRs, so the minimum MIPS32 revision is 2.  */
   { "mips3d", ASE_MIPS3D, 0,
     OPTION_MIPS3D, OPTION_NO_MIPS3D,
-    2, 1, -1, -1 },
+    2, 1, -1, -1,
+    6 },
 
   { "mt", ASE_MT, 0,
     OPTION_MT, OPTION_NO_MT,
-    2, 2, -1, -1 },
+     2,  2, -1, -1,
+    -1 },
 
   { "smartmips", ASE_SMARTMIPS, 0,
     OPTION_SMARTMIPS, OPTION_NO_SMARTMIPS,
-    1, -1, -1, -1 },
+    1, -1, -1, -1,
+    6 },
 
   { "virt", ASE_VIRT, ASE_VIRT64,
     OPTION_VIRT, OPTION_NO_VIRT,
-    2, 2, 2, 2 },
+     2,  2,  2,  2,
+    -1 },
 
   { "msa", ASE_MSA, ASE_MSA64,
     OPTION_MSA, OPTION_NO_MSA,
-    2, 2, 2, 2 },
+     2,  2,  2,  2,
+    -1 },
 
   { "xpa", ASE_XPA, 0,
     OPTION_XPA, OPTION_NO_XPA,
-    2, 2, -1, -1 }
+     2,  2, -1, -1,
+    -1 },
 };
 
 /* The set of ASEs that require -mfp64.  */
@@ -1915,6 +1969,9 @@ mips_isa_rev (void)
   if (mips_opts.isa == ISA_MIPS32R5 || mips_opts.isa == ISA_MIPS64R5)
     return 5;
 
+  if (mips_opts.isa == ISA_MIPS32R6 || mips_opts.isa == ISA_MIPS64R6)
+    return 6;
+
   /* microMIPS implies revision 2 or above.  */
   if (mips_opts.micromips)
     return 2;
@@ -1966,6 +2023,16 @@ mips_check_isa_supports_ase (const struct mips_ase *ase)
 	as_warn (_("the `%s' extension requires %s%d revision %d or greater"),
 		 ase->name, base, size, min_rev);
     }
+  else if ((ase->rem_rev > 0 && mips_isa_rev () >= ase->rem_rev)
+	   && (warned_isa & ase->flags) != ase->flags)
+    {
+      warned_isa |= ase->flags;
+      base = mips_opts.micromips ? "microMIPS" : "MIPS";
+      size = ISA_HAS_64BIT_REGS (mips_opts.isa) ? 64 : 32;
+      as_warn (_("the `%s' extension was removed in %s%d revision %d"),
+	       ase->name, base, size, ase->rem_rev);
+    }
+
   if ((ase->flags & FP64_ASES)
       && mips_opts.fp != 64
       && (warned_fp32 & ase->flags) != ase->flags)
@@ -3294,7 +3361,7 @@ validate_mips_insn (const struct mips_opcode *opcode,
 	      used_bits &= ~(mask & 0x700);
 	  }
 	/* Skip prefix characters.  */
-	if (decode_operand && (*s == '+' || *s == 'm'))
+	if (decode_operand && (*s == '+' || *s == 'm' || *s == '-'))
 	  ++s;
 	opno += 1;
 	break;
@@ -3772,6 +3839,8 @@ mips_check_options (struct mips_set_options *opts, bfd_boolean abi_checks)
       if (abi_checks
 	  && ABI_NEEDS_64BIT_REGS (mips_abi))
 	as_warn (_("`fp=32' used with a 64-bit ABI"));
+      if (ISA_IS_R6 (mips_opts.isa) && opts->single_float == 0)
+	as_bad (_("`fp=32' used with a MIPS R6 cpu"));
       break;
     default:
       as_bad (_("Unknown size of floating point registers"));
@@ -3783,6 +3852,16 @@ mips_check_options (struct mips_set_options *opts, bfd_boolean abi_checks)
 
   if (opts->micromips == 1 && opts->mips16 == 1)
     as_bad (_("`mips16' cannot be used with `micromips'"));
+  else if (ISA_IS_R6 (mips_opts.isa)
+	   && (opts->micromips == 1
+	       || opts->mips16 == 1))
+    as_fatal (_("`%s' can not be used with `%s'"),
+	      opts->micromips ? "micromips" : "mips16",
+	      mips_cpu_info_from_isa (mips_opts.isa)->name);
+
+  if (ISA_IS_R6 (opts->isa) && mips_relax_branch)
+    as_fatal (_("branch relaxation is not supported in `%s'"),
+	      mips_cpu_info_from_isa (opts->isa)->name);
 }
 
 /* Perform consistency checks on the module level options exactly once.
@@ -3831,6 +3910,9 @@ file_mips_check_options (void)
 	       && ISA_HAS_64BIT_FPRS (file_mips_opts.isa))
 	/* Handle ASEs that require 64-bit float registers, if possible.  */
 	file_mips_opts.fp = 64;
+      else if (ISA_IS_R6 (mips_opts.isa))
+	/* R6 implies 64-bit float registers.  */
+	file_mips_opts.fp = 64;
       else
 	/* 32-bit float registers.  */
 	file_mips_opts.fp = 32;
@@ -3868,6 +3950,12 @@ file_mips_check_options (void)
     file_mips_opts.micromips = (CPU_HAS_MICROMIPS (file_mips_opts.arch))
 				? 1 : 0;
 
+  if (mips_nan2008 == -1)
+    mips_nan2008 = (ISA_HAS_LEGACY_NAN (file_mips_opts.isa)) ? 0 : 1;
+  else if (!ISA_HAS_LEGACY_NAN (file_mips_opts.isa) && mips_nan2008 == 0)
+    as_fatal (_("`%s' does not support legacy NaN"),
+	      mips_cpu_info_from_arch (file_mips_opts.arch)->name);
+
   /* Some ASEs require 64-bit FPRs, so -mfp32 should stop those ASEs from
      being selected implicitly.  */
   if (file_mips_opts.fp != 64)
@@ -4047,9 +4135,15 @@ limited_pcrel_reloc_p (bfd_reloc_code_real_type reloc)
     case BFD_RELOC_MICROMIPS_7_PCREL_S1:
     case BFD_RELOC_MICROMIPS_10_PCREL_S1:
     case BFD_RELOC_MICROMIPS_16_PCREL_S1:
+    case BFD_RELOC_MIPS_21_PCREL_S2:
+    case BFD_RELOC_MIPS_26_PCREL_S2:
+    case BFD_RELOC_MIPS_18_PCREL_S3:
+    case BFD_RELOC_MIPS_19_PCREL_S2:
       return TRUE;
 
     case BFD_RELOC_32_PCREL:
+    case BFD_RELOC_HI16_S_PCREL:
+    case BFD_RELOC_LO16_PCREL:
       return HAVE_64BIT_ADDRESSES;
 
     default:
@@ -4352,6 +4446,20 @@ operand_reg_mask (const struct mips_cl_insn *insn,
       uval = insn_extract_operand (insn, operand);
       return (1 << (uval & 31)) | (1 << (uval >> 5));
 
+    case OP_SAME_RS_RT:
+      if (!(type_mask & (1 << OP_REG_GP)))
+	return 0;
+      uval = insn_extract_operand (insn, operand);
+      gas_assert ((uval & 31) == (uval >> 5));
+      return 1 << (uval & 31);
+
+    case OP_CHECK_PREV:
+    case OP_NON_ZERO_REG:
+      if (!(type_mask & (1 << OP_REG_GP)))
+	return 0;
+      uval = insn_extract_operand (insn, operand);
+      return 1 << (uval & 31);
+
     case OP_LWM_SWM_LIST:
       abort ();
 
@@ -5144,6 +5252,58 @@ match_clo_clz_dest_operand (struct mips_arg_info *arg,
   return TRUE;
 }
 
+/* OP_CHECK_PREV matcher.  */
+
+static bfd_boolean
+match_check_prev_operand (struct mips_arg_info *arg,
+			  const struct mips_operand *operand_base)
+{
+  const struct mips_check_prev_operand *operand;
+  unsigned int regno;
+
+  operand = (const struct mips_check_prev_operand *) operand_base;
+
+  if (!match_reg (arg, OP_REG_GP, &regno))
+    return FALSE;
+
+  if (!operand->zero_ok && regno == 0)
+    return FALSE;
+
+  if ((operand->less_than_ok && regno < arg->last_regno)
+      || (operand->greater_than_ok && regno > arg->last_regno)
+      || (operand->equal_ok && regno == arg->last_regno))
+    {
+      arg->last_regno = regno;
+      insn_insert_operand (arg->insn, operand_base, regno);
+      return TRUE;
+    }
+
+  return FALSE;
+}
+
+/* OP_SAME_RS_RT matcher.  */
+
+static bfd_boolean
+match_same_rs_rt_operand (struct mips_arg_info *arg,
+			  const struct mips_operand *operand)
+{
+  unsigned int regno;
+
+  if (!match_reg (arg, OP_REG_GP, &regno))
+    return FALSE;
+
+  if (regno == 0)
+    {
+      set_insn_error (arg->argnum, _("the source register must not be $0"));
+      return FALSE;
+    }
+
+  arg->last_regno = regno;
+
+  insn_insert_operand (arg->insn, operand, regno | (regno << 5));
+  return TRUE;
+}
+
 /* OP_LWM_SWM_LIST matcher.  */
 
 static bfd_boolean
@@ -5537,6 +5697,25 @@ match_pc_operand (struct mips_arg_info *arg)
   return FALSE;
 }
 
+/* OP_NON_ZERO_REG matcher.  */
+
+static bfd_boolean
+match_non_zero_reg_operand (struct mips_arg_info *arg,
+			    const struct mips_operand *operand)
+{
+  unsigned int regno;
+
+  if (!match_reg (arg, OP_REG_GP, &regno))
+    return FALSE;
+
+  if (regno == 0)
+    return FALSE;
+
+  arg->last_regno = regno;
+  insn_insert_operand (arg->insn, operand, regno);
+  return TRUE;
+}
+
 /* OP_REPEAT_DEST_REG and OP_REPEAT_PREV_REG matcher.  OTHER_REGNO is the
    register that we need to match.  */
 
@@ -5813,6 +5992,15 @@ match_operand (struct mips_arg_info *arg,
 
     case OP_REG_INDEX:
       return match_reg_index_operand (arg, operand);
+
+    case OP_SAME_RS_RT:
+      return match_same_rs_rt_operand (arg, operand);
+
+    case OP_CHECK_PREV:
+      return match_check_prev_operand (arg, operand);
+
+    case OP_NON_ZERO_REG:
+      return match_non_zero_reg_operand (arg, operand);
     }
   abort ();
 }
@@ -6013,6 +6201,14 @@ insns_between (const struct mips_cl_insn *insn1,
 	return 1;
     }
 
+  /* Forbidden slots can not contain Control Transfer Instructions (CTIs)
+     CTIs include all branches and jumps, nal, eret, eretnc, deret, wait
+     and pause.  */
+  if ((insn1->insn_mo->pinfo2 & INSN2_FORBIDDEN_SLOT)
+      && ((pinfo2 & INSN_NO_DELAY_SLOT)
+	  || (insn2 && delayed_branch_p (insn2))))
+    return 1;
+
   return 0;
 }
 
@@ -6870,6 +7066,40 @@ append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
 	  }
 	  break;
 
+	case BFD_RELOC_MIPS_21_PCREL_S2:
+	  {
+	    int shift;
+
+	    shift = 2;
+	    if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0)
+	      as_bad (_("branch to misaligned address (0x%lx)"),
+		      (unsigned long) address_expr->X_add_number);
+	    if ((address_expr->X_add_number + (1 << (shift + 20)))
+		& ~((1 << (shift + 21)) - 1))
+	      as_bad (_("branch address range overflow (0x%lx)"),
+		      (unsigned long) address_expr->X_add_number);
+	    ip->insn_opcode |= ((address_expr->X_add_number >> shift)
+				& 0x1fffff);
+	  }
+	  break;
+
+	case BFD_RELOC_MIPS_26_PCREL_S2:
+	  {
+	    int shift;
+
+	    shift = 2;
+	    if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0)
+	      as_bad (_("branch to misaligned address (0x%lx)"),
+		      (unsigned long) address_expr->X_add_number);
+	    if ((address_expr->X_add_number + (1 << (shift + 25)))
+		& ~((1 << (shift + 26)) - 1))
+	      as_bad (_("branch address range overflow (0x%lx)"),
+		      (unsigned long) address_expr->X_add_number);
+	    ip->insn_opcode |= ((address_expr->X_add_number >> shift)
+				& 0x3ffffff);
+	  }
+	  break;
+
 	default:
 	  {
 	    offsetT value;
@@ -7534,12 +7764,33 @@ match_insn (struct mips_cl_insn *insn, const struct mips_opcode *opcode,
       arg.opnum += 1;
       switch (*args)
 	{
+	case '-':
+	  switch (args[1])
+	    {
+	    case 'A':
+	      *offset_reloc = BFD_RELOC_MIPS_19_PCREL_S2;
+	      break;
+
+	    case 'B':
+	      *offset_reloc = BFD_RELOC_MIPS_18_PCREL_S3;
+	      break;
+	    }
+	  break;
+
 	case '+':
 	  switch (args[1])
 	    {
 	    case 'i':
 	      *offset_reloc = BFD_RELOC_MIPS_JMP;
 	      break;
+
+	    case '\'':
+	      *offset_reloc = BFD_RELOC_MIPS_26_PCREL_S2;
+	      break;
+
+	    case '\"':
+	      *offset_reloc = BFD_RELOC_MIPS_21_PCREL_S2;
+	      break;
 	    }
 	  break;
 
@@ -7625,7 +7876,7 @@ match_insn (struct mips_cl_insn *insn, const struct mips_opcode *opcode,
 	abort ();
 
       /* Skip prefixes.  */
-      if (*args == '+' || *args == 'm')
+      if (*args == '+' || *args == 'm' || *args == '-')
 	args++;
 
       if (mips_optional_operand_p (operand)
@@ -8095,10 +8346,13 @@ static const char * const shft_fmt[2] = { "d,w,<", "t,r,<" };
 static const char * const trap_fmt[2] = { "s,t,q", "s,t,|" };
 
 #define BRK_FMT (brk_fmt[mips_opts.micromips][mips_opts.insn32])
-#define COP12_FMT (cop12_fmt[mips_opts.micromips])
+#define COP12_FMT (ISA_IS_R6 (mips_opts.isa) ? "E,+:(d)" \
+					     : cop12_fmt[mips_opts.micromips])
 #define JALR_FMT (jalr_fmt[mips_opts.micromips])
 #define LUI_FMT (lui_fmt[mips_opts.micromips])
 #define MEM12_FMT (mem12_fmt[mips_opts.micromips])
+#define LL_SC_FMT (ISA_IS_R6 (mips_opts.isa) ? "t,+j(b)" \
+					     : mem12_fmt[mips_opts.micromips])
 #define MFHL_FMT (mfhl_fmt[mips_opts.micromips][mips_opts.insn32])
 #define SHFT_FMT (shft_fmt[mips_opts.micromips])
 #define TRAP_FMT (trap_fmt[mips_opts.micromips])
@@ -8276,7 +8530,7 @@ macro_build (expressionS *ep, const char *name, const char *fmt, ...)
 	    uval |= (uval << 5);
 	  insn_insert_operand (&insn, operand, uval);
 
-	  if (*fmt == '+' || *fmt == 'm')
+	  if (*fmt == '+' || *fmt == 'm' || *fmt == '-')
 	    ++fmt;
 	  break;
 	}
@@ -11045,7 +11299,9 @@ macro (struct mips_cl_insn *ip, char *str)
     case M_LWC2_AB:
       s = "lwc2";
       fmt = COP12_FMT;
-      offbits = (mips_opts.micromips ? 12 : 16);
+      offbits = (mips_opts.micromips ? 12
+		 : ISA_IS_R6 (mips_opts.isa) ? 11
+		 : 16);
       /* Itbl support may require additional care here.  */
       coproc = 1;
       goto ld_st;
@@ -11075,7 +11331,9 @@ macro (struct mips_cl_insn *ip, char *str)
     case M_LDC2_AB:
       s = "ldc2";
       fmt = COP12_FMT;
-      offbits = (mips_opts.micromips ? 12 : 16);
+      offbits = (mips_opts.micromips ? 12
+		 : ISA_IS_R6 (mips_opts.isa) ? 11
+		 : 16);
       /* Itbl support may require additional care here.  */
       coproc = 1;
       goto ld_st;
@@ -11103,13 +11361,17 @@ macro (struct mips_cl_insn *ip, char *str)
       goto ld_st;
     case M_LL_AB:
       s = "ll";
-      fmt = MEM12_FMT;
-      offbits = (mips_opts.micromips ? 12 : 16);
+      fmt = LL_SC_FMT;
+      offbits = (mips_opts.micromips ? 12
+		 : ISA_IS_R6 (mips_opts.isa) ? 9
+		 : 16);
       goto ld;
     case M_LLD_AB:
       s = "lld";
-      fmt = MEM12_FMT;
-      offbits = (mips_opts.micromips ? 12 : 16);
+      fmt = LL_SC_FMT;
+      offbits = (mips_opts.micromips ? 12
+		 : ISA_IS_R6 (mips_opts.isa) ? 9
+		 : 16);
       goto ld;
     case M_LWU_AB:
       s = "lwu";
@@ -11179,7 +11441,9 @@ macro (struct mips_cl_insn *ip, char *str)
     case M_SWC2_AB:
       s = "swc2";
       fmt = COP12_FMT;
-      offbits = (mips_opts.micromips ? 12 : 16);
+      offbits = (mips_opts.micromips ? 12
+		 : ISA_IS_R6 (mips_opts.isa) ? 11
+		 : 16);
       /* Itbl support may require additional care here.  */
       coproc = 1;
       goto ld_st;
@@ -11202,18 +11466,26 @@ macro (struct mips_cl_insn *ip, char *str)
       goto ld_st;
     case M_SC_AB:
       s = "sc";
-      fmt = MEM12_FMT;
-      offbits = (mips_opts.micromips ? 12 : 16);
+      fmt = LL_SC_FMT;
+      offbits = (mips_opts.micromips ? 12
+		 : ISA_IS_R6 (mips_opts.isa) ? 9
+		 : 16);
       goto ld_st;
     case M_SCD_AB:
       s = "scd";
-      fmt = MEM12_FMT;
-      offbits = (mips_opts.micromips ? 12 : 16);
+      fmt = LL_SC_FMT;
+      offbits = (mips_opts.micromips ? 12
+		 : ISA_IS_R6 (mips_opts.isa) ? 9
+		 : 16);
       goto ld_st;
     case M_CACHE_AB:
       s = "cache";
-      fmt = mips_opts.micromips ? "k,~(b)" : "k,o(b)";
-      offbits = (mips_opts.micromips ? 12 : 16);
+      fmt = (mips_opts.micromips ? "k,~(b)"
+	     : ISA_IS_R6 (mips_opts.isa) ? "k,+j(b)"
+	     : "k,o(b)");
+      offbits = (mips_opts.micromips ? 12
+		 : ISA_IS_R6 (mips_opts.isa) ? 9
+		 : 16);
       goto ld_st;
     case M_CACHEE_AB:
       s = "cachee";
@@ -11222,8 +11494,12 @@ macro (struct mips_cl_insn *ip, char *str)
       goto ld_st;
     case M_PREF_AB:
       s = "pref";
-      fmt = !mips_opts.micromips ? "k,o(b)" : "k,~(b)";
-      offbits = (mips_opts.micromips ? 12 : 16);
+      fmt = (mips_opts.micromips ? "k,~(b)"
+	     : ISA_IS_R6 (mips_opts.isa) ? "k,+j(b)"
+	     : "k,o(b)");
+      offbits = (mips_opts.micromips ? 12
+		 : ISA_IS_R6 (mips_opts.isa) ? 9
+		 : 16);
       goto ld_st;
     case M_PREFE_AB:
       s = "prefe";
@@ -11239,7 +11515,9 @@ macro (struct mips_cl_insn *ip, char *str)
     case M_SDC2_AB:
       s = "sdc2";
       fmt = COP12_FMT;
-      offbits = (mips_opts.micromips ? 12 : 16);
+      offbits = (mips_opts.micromips ? 12
+		 : ISA_IS_R6 (mips_opts.isa) ? 11
+		 : 16);
       /* Itbl support may require additional care here.  */
       coproc = 1;
       goto ld_st;
@@ -13566,7 +13844,9 @@ static const struct percent_op_match mips_percent_op[] =
   {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16},
   {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16},
   {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL},
-  {"%hi", BFD_RELOC_HI16_S}
+  {"%hi", BFD_RELOC_HI16_S},
+  {"%pcrel_hi", BFD_RELOC_HI16_S_PCREL},
+  {"%pcrel_lo", BFD_RELOC_LO16_PCREL}
 };
 
 static const struct percent_op_match mips16_percent_op[] =
@@ -13844,6 +14124,10 @@ md_parse_option (int c, char *arg)
       file_mips_opts.isa = ISA_MIPS32R5;
       break;
 
+    case OPTION_MIPS32R6:
+      file_mips_opts.isa = ISA_MIPS32R6;
+      break;
+
     case OPTION_MIPS64R2:
       file_mips_opts.isa = ISA_MIPS64R2;
       break;
@@ -13856,6 +14140,10 @@ md_parse_option (int c, char *arg)
       file_mips_opts.isa = ISA_MIPS64R5;
       break;
 
+    case OPTION_MIPS64R6:
+      file_mips_opts.isa = ISA_MIPS64R6;
+      break;
+
     case OPTION_MIPS64:
       file_mips_opts.isa = ISA_MIPS64;
       break;
@@ -14161,9 +14449,9 @@ md_parse_option (int c, char *arg)
 
     case OPTION_NAN:
       if (strcmp (arg, "2008") == 0)
-	mips_flag_nan2008 = TRUE;
+	mips_nan2008 = 1;
       else if (strcmp (arg, "legacy") == 0)
-	mips_flag_nan2008 = FALSE;
+	mips_nan2008 = 0;
       else
 	{
 	  as_fatal (_("invalid NaN setting -mnan=%s"), arg);
@@ -14290,6 +14578,8 @@ md_pcrel_from (fixS *fixP)
     case BFD_RELOC_MICROMIPS_16_PCREL_S1:
     case BFD_RELOC_MICROMIPS_JMP:
     case BFD_RELOC_16_PCREL_S2:
+    case BFD_RELOC_MIPS_21_PCREL_S2:
+    case BFD_RELOC_MIPS_26_PCREL_S2:
     case BFD_RELOC_MIPS_JMP:
       /* Return the address of the delay slot.  */
       return addr + 4;
@@ -14455,6 +14745,17 @@ mips_force_relocation (fixS *fixp)
       || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1)
     return 1;
 
+  /* We want all PC-relative relocations to be kept for R6 relaxation.  */
+  if (ISA_IS_R6 (mips_opts.isa)
+      && (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2
+	  || fixp->fx_r_type == BFD_RELOC_MIPS_21_PCREL_S2
+	  || fixp->fx_r_type == BFD_RELOC_MIPS_26_PCREL_S2
+	  || fixp->fx_r_type == BFD_RELOC_MIPS_18_PCREL_S3
+	  || fixp->fx_r_type == BFD_RELOC_MIPS_19_PCREL_S2
+	  || fixp->fx_r_type == BFD_RELOC_HI16_S_PCREL
+	  || fixp->fx_r_type == BFD_RELOC_LO16_PCREL))
+    return 1;
+
   return 0;
 }
 
@@ -14499,6 +14800,12 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
       case BFD_RELOC_MICROMIPS_10_PCREL_S1:
       case BFD_RELOC_MICROMIPS_16_PCREL_S1:
       case BFD_RELOC_32_PCREL:
+      case BFD_RELOC_MIPS_21_PCREL_S2:
+      case BFD_RELOC_MIPS_26_PCREL_S2:
+      case BFD_RELOC_MIPS_18_PCREL_S3:
+      case BFD_RELOC_MIPS_19_PCREL_S2:
+      case BFD_RELOC_HI16_S_PCREL:
+      case BFD_RELOC_LO16_PCREL:
 	break;
 
       case BFD_RELOC_32:
@@ -14691,6 +14998,38 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
 	md_number_to_chars (buf, *valP, fixP->fx_size);
       break;
 
+    case BFD_RELOC_MIPS_21_PCREL_S2:
+    case BFD_RELOC_MIPS_26_PCREL_S2:
+      if ((*valP & 0x3) != 0)
+	as_bad_where (fixP->fx_file, fixP->fx_line,
+		      _("branch to misaligned address (%lx)"), (long) *valP);
+
+      gas_assert (!fixP->fx_done);
+      break;
+
+    case BFD_RELOC_MIPS_18_PCREL_S3:
+      if ((*valP & 0x7) != 0)
+	as_bad_where (fixP->fx_file, fixP->fx_line,
+		      _("PC-relative access to misaligned address (%lx)"),
+		      (long) *valP);
+
+      gas_assert (!fixP->fx_done);
+      break;
+
+    case BFD_RELOC_MIPS_19_PCREL_S2:
+      if ((*valP & 0x3) != 0)
+	as_bad_where (fixP->fx_file, fixP->fx_line,
+		      _("PC-relative access to misaligned address (%lx)"),
+		      (long) *valP);
+
+      gas_assert (!fixP->fx_done);
+      break;
+
+    case BFD_RELOC_HI16_S_PCREL:
+    case BFD_RELOC_LO16_PCREL:
+      gas_assert (!fixP->fx_done);
+      break;
+
     case BFD_RELOC_16_PCREL_S2:
       if ((*valP & 0x3) != 0)
 	as_bad_where (fixP->fx_file, fixP->fx_line,
@@ -15369,6 +15708,10 @@ s_mipsset (int x ATTRIBUTE_UNUSED)
 	  if (mips_opts.fp != 0)
 	    mips_opts.fp = 32;
 	  break;
+	case ISA_MIPS32R6:
+	  mips_opts.gp = 32;
+	  mips_opts.fp = 64;
+	  break;
 	case ISA_MIPS3:
 	case ISA_MIPS4:
 	case ISA_MIPS5:
@@ -15376,6 +15719,7 @@ s_mipsset (int x ATTRIBUTE_UNUSED)
 	case ISA_MIPS64R2:
 	case ISA_MIPS64R3:
 	case ISA_MIPS64R5:
+	case ISA_MIPS64R6:
 	  mips_opts.gp = 64;
 	  if (mips_opts.fp != 0)
 	    {
@@ -16018,10 +16362,16 @@ s_nan (int ignore ATTRIBUTE_UNUSED)
 
   if (i == sizeof (str_2008) - 1
       && memcmp (input_line_pointer, str_2008, i) == 0)
-    mips_flag_nan2008 = TRUE;
+    mips_nan2008 = 1;
   else if (i == sizeof (str_legacy) - 1
 	   && memcmp (input_line_pointer, str_legacy, i) == 0)
-    mips_flag_nan2008 = FALSE;
+    {
+      if (ISA_HAS_LEGACY_NAN (file_mips_opts.isa))
+	mips_nan2008 = 0;
+      else
+	as_bad (_("`%s' does not support legacy NaN"),
+	          mips_cpu_info_from_isa (file_mips_opts.isa)->name);
+    }
   else
     as_bad (_("bad .nan directive"));
 
@@ -16718,8 +17068,11 @@ mips_fix_adjustable (fixS *fixp)
   /* There is no place to store an in-place offset for JALR relocations.
      Likewise an in-range offset of limited PC-relative relocations may
      overflow the in-place relocatable field if recalculated against the
-     start address of the symbol's containing section.  */
-  if (HAVE_IN_PLACE_ADDENDS
+     start address of the symbol's containing section.
+
+     Also, PC relative relocations for MIPS R6 need to be symbol rather than
+     section relative to allow linker relaxations to be performed later on.  */
+  if ((HAVE_IN_PLACE_ADDENDS || ISA_IS_R6 (mips_opts.isa))
       && (limited_pcrel_reloc_p (fixp->fx_r_type)
 	  || jalr_reloc_p (fixp->fx_r_type)))
     return 0;
@@ -16799,7 +17152,13 @@ tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
 		  || fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1
 		  || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1
 		  || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1
-		  || fixp->fx_r_type == BFD_RELOC_32_PCREL);
+		  || fixp->fx_r_type == BFD_RELOC_32_PCREL
+		  || fixp->fx_r_type == BFD_RELOC_MIPS_21_PCREL_S2
+		  || fixp->fx_r_type == BFD_RELOC_MIPS_26_PCREL_S2
+		  || fixp->fx_r_type == BFD_RELOC_MIPS_18_PCREL_S3
+		  || fixp->fx_r_type == BFD_RELOC_MIPS_19_PCREL_S2
+		  || fixp->fx_r_type == BFD_RELOC_HI16_S_PCREL
+		  || fixp->fx_r_type == BFD_RELOC_LO16_PCREL);
 
       /* At this point, fx_addnumber is "symbol offset - pcrel address".
 	 Relocations want only the symbol offset.  */
@@ -17724,7 +18083,7 @@ mips_elf_final_processing (void)
   if (mips_32bitmode)
     elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE;
 
-  if (mips_flag_nan2008)
+  if (mips_nan2008 == 1)
     elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NAN2008;
 
   /* 32 bit code with 64 bit FP registers.  */
@@ -18170,10 +18529,12 @@ static const struct mips_cpu_info mips_cpu_info_table[] =
   { "mips32r2",       MIPS_CPU_IS_ISA, 0,	ISA_MIPS32R2, CPU_MIPS32R2 },
   { "mips32r3",       MIPS_CPU_IS_ISA, 0,	ISA_MIPS32R3, CPU_MIPS32R3 },
   { "mips32r5",       MIPS_CPU_IS_ISA, 0,	ISA_MIPS32R5, CPU_MIPS32R5 },
+  { "mips32r6",       MIPS_CPU_IS_ISA, 0,	ISA_MIPS32R6, CPU_MIPS32R6 },
   { "mips64",         MIPS_CPU_IS_ISA, 0,	ISA_MIPS64,   CPU_MIPS64 },
   { "mips64r2",       MIPS_CPU_IS_ISA, 0,	ISA_MIPS64R2, CPU_MIPS64R2 },
   { "mips64r3",       MIPS_CPU_IS_ISA, 0,	ISA_MIPS64R3, CPU_MIPS64R3 },
   { "mips64r5",       MIPS_CPU_IS_ISA, 0,	ISA_MIPS64R5, CPU_MIPS64R5 },
+  { "mips64r6",       MIPS_CPU_IS_ISA, 0,	ISA_MIPS64R6, CPU_MIPS64R6 },
 
   /* MIPS I */
   { "r3000",          0, 0,			ISA_MIPS1,    CPU_R3000 },
@@ -18489,10 +18850,12 @@ MIPS options:\n\
 -mips32r2               generate MIPS32 release 2 ISA instructions\n\
 -mips32r3               generate MIPS32 release 3 ISA instructions\n\
 -mips32r5               generate MIPS32 release 5 ISA instructions\n\
+-mips32r6               generate MIPS32 release 6 ISA instructions\n\
 -mips64                 generate MIPS64 ISA instructions\n\
 -mips64r2               generate MIPS64 release 2 ISA instructions\n\
 -mips64r3               generate MIPS64 release 3 ISA instructions\n\
 -mips64r5               generate MIPS64 release 5 ISA instructions\n\
+-mips64r6               generate MIPS64 release 6 ISA instructions\n\
 -march=CPU/-mtune=CPU	generate code/schedule for CPU, where CPU is one of:\n"));
 
   first = 1;
diff --git a/gas/configure b/gas/configure
index 6a1324e53c1..2c3c21a92b7 100755
--- a/gas/configure
+++ b/gas/configure
@@ -12135,6 +12135,9 @@ _ACEOF
 	  mipsisa32r5 | mipsisa32r5el)
 	    mips_cpu=mips32r5
 	    ;;
+	  mipsisa32r6 | mipsisa32r6el)
+	    mips_cpu=mips32r6
+	    ;;
 	  mipsisa64 | mipsisa64el)
 	    mips_cpu=mips64
 	    ;;
@@ -12147,6 +12150,9 @@ _ACEOF
 	  mipsisa64r5 | mipsisa64r5el)
 	    mips_cpu=mips64r5
 	    ;;
+	  mipsisa64r6 | mipsisa64r6el)
+	    mips_cpu=mips64r6
+	    ;;
 	  mipstx39 | mipstx39el)
 	    mips_cpu=r3900
 	    ;;
@@ -12156,6 +12162,9 @@ _ACEOF
 	  mipsisa32r2* | mipsisa64r2*)
 	    mips_cpu=`echo $target_cpu | sed -e 's/[a-z]*..r2//' -e 's/el$//'`
 	    ;;
+	  mipsisa32r6* | mipsisa64r6*)
+	    mips_cpu=`echo $target_cpu | sed -e 's/[a-z]*..r6//' -e 's/el$//'`
+	    ;;
 	  mips64* | mipsisa64* | mipsisa32*)
 	    mips_cpu=`echo $target_cpu | sed -e 's/[a-z]*..//' -e 's/el$//'`
 	    ;;
diff --git a/gas/configure.ac b/gas/configure.ac
index e2fc1b7cc64..371f7b387fc 100644
--- a/gas/configure.ac
+++ b/gas/configure.ac
@@ -217,6 +217,9 @@ changequote([,])dnl
 	  mipsisa32r5 | mipsisa32r5el)
 	    mips_cpu=mips32r5
 	    ;;
+	  mipsisa32r6 | mipsisa32r6el)
+	    mips_cpu=mips32r6
+	    ;;
 	  mipsisa64 | mipsisa64el)
 	    mips_cpu=mips64
 	    ;;
@@ -229,6 +232,9 @@ changequote([,])dnl
 	  mipsisa64r5 | mipsisa64r5el)
 	    mips_cpu=mips64r5
 	    ;;
+	  mipsisa64r6 | mipsisa64r6el)
+	    mips_cpu=mips64r6
+	    ;;
 	  mipstx39 | mipstx39el)
 	    mips_cpu=r3900
 	    ;;
@@ -240,6 +246,11 @@ changequote(,)dnl
 	    mips_cpu=`echo $target_cpu | sed -e 's/[a-z]*..r2//' -e 's/el$//'`
 changequote([,])dnl
 	    ;;
+	  mipsisa32r6* | mipsisa64r6*)
+changequote(,)dnl
+	    mips_cpu=`echo $target_cpu | sed -e 's/[a-z]*..r6//' -e 's/el$//'`
+changequote([,])dnl
+	    ;;
 	  mips64* | mipsisa64* | mipsisa32*)
 changequote(,)dnl
 	    mips_cpu=`echo $target_cpu | sed -e 's/[a-z]*..//' -e 's/el$//'`
diff --git a/gas/doc/as.texinfo b/gas/doc/as.texinfo
index 251b6d5a133..f93c0442905 100644
--- a/gas/doc/as.texinfo
+++ b/gas/doc/as.texinfo
@@ -403,8 +403,8 @@ gcc(1), ld(1), and the Info entries for @file{binutils} and @file{ld}.
    [@b{-modd-spreg}] [@b{-mno-odd-spreg}]
    [@b{-march}=@var{CPU}] [@b{-mtune}=@var{CPU}] [@b{-mips1}] [@b{-mips2}]
    [@b{-mips3}] [@b{-mips4}] [@b{-mips5}] [@b{-mips32}] [@b{-mips32r2}]
-   [@b{-mips32r3}] [@b{-mips32r5}] [@b{-mips64}] [@b{-mips64r2}]
-   [@b{-mips64r3}] [@b{-mips64r5}] 
+   [@b{-mips32r3}] [@b{-mips32r5}] [@b{-mips32r6}] [@b{-mips64}] [@b{-mips64r2}]
+   [@b{-mips64r3}] [@b{-mips64r5}] [@b{-mips64r6}]
    [@b{-construct-floats}] [@b{-no-construct-floats}]
    [@b{-mnan=@var{encoding}}]
    [@b{-trap}] [@b{-no-break}] [@b{-break}] [@b{-no-trap}]
@@ -1277,19 +1277,22 @@ Generate ``little endian'' format output.
 @itemx -mips32r2
 @itemx -mips32r3
 @itemx -mips32r5
+@itemx -mips32r6
 @itemx -mips64
 @itemx -mips64r2
 @itemx -mips64r3
 @itemx -mips64r5
+@itemx -mips64r6
 Generate code for a particular MIPS Instruction Set Architecture level.
 @samp{-mips1} is an alias for @samp{-march=r3000}, @samp{-mips2} is an
 alias for @samp{-march=r6000}, @samp{-mips3} is an alias for
 @samp{-march=r4000} and @samp{-mips4} is an alias for @samp{-march=r8000}.
 @samp{-mips5}, @samp{-mips32}, @samp{-mips32r2}, @samp{-mips32r3},
-@samp{-mips32r5}, @samp{-mips64}, @samp{-mips64r2}, @samp{-mips64r3}, and
-@samp{-mips64r5} correspond to generic MIPS V, MIPS32, MIPS32 Release 2,
-MIPS32 Release 3, MIPS32 Release 5, MIPS64, MIPS64 Release 2, 
-MIPS64 Release 3, and MIPS64 Release 5 ISA processors, respectively.
+@samp{-mips32r5}, @samp{-mips32r6}, @samp{-mips64}, @samp{-mips64r2},
+@samp{-mips64r3}, @samp{-mips64r5}, and @samp{-mips64r6} correspond to generic
+MIPS V, MIPS32, MIPS32 Release 2, MIPS32 Release 3, MIPS32 Release 5, MIPS32
+Release 6, MIPS64, MIPS64 Release 2, MIPS64 Release 3, MIPS64 Release 5, and
+MIPS64 Release 6 ISA processors, respectively.
 
 @item -march=@var{cpu}
 Generate code for a particular MIPS CPU.
diff --git a/gas/doc/c-mips.texi b/gas/doc/c-mips.texi
index 1e52e09a6cb..cafd832ecc0 100644
--- a/gas/doc/c-mips.texi
+++ b/gas/doc/c-mips.texi
@@ -84,21 +84,24 @@ VxWorks-style position-independent macro expansions.
 @itemx -mips32r2
 @itemx -mips32r3
 @itemx -mips32r5
+@itemx -mips32r6
 @itemx -mips64
 @itemx -mips64r2
 @itemx -mips64r3
 @itemx -mips64r5
+@itemx -mips64r6
 Generate code for a particular MIPS Instruction Set Architecture level.
 @samp{-mips1} corresponds to the R2000 and R3000 processors,
 @samp{-mips2} to the R6000 processor, @samp{-mips3} to the
 R4000 processor, and @samp{-mips4} to the R8000 and R10000 processors.
-@samp{-mips5}, @samp{-mips32}, @samp{-mips32r2}, @samp{-mips32r3}, 
-@samp{-mips32r5}, @samp{-mips64}, @samp{-mips64r2}, @samp{-mips64r3}, and
-@samp{-mips64r5} correspond to generic MIPS V, MIPS32, MIPS32 Release 2,
-MIPS32 Release 3, MIPS32 Release 5, MIPS64, and MIPS64 Release 2,
-MIPS64 Release 3, and MIPS64 Release 5 ISA processors, respectively.  You 
-can also switch instruction sets during the assembly; see @ref{MIPS ISA,
-Directives to override the ISA level}.
+@samp{-mips5}, @samp{-mips32}, @samp{-mips32r2}, @samp{-mips32r3},
+@samp{-mips32r5}, @samp{-mips32r6}, @samp{-mips64}, @samp{-mips64r2},
+@samp{-mips64r3}, @samp{-mips64r5}, and @samp{-mips64r6} correspond to
+generic MIPS V, MIPS32, MIPS32 Release 2, MIPS32 Release 3, MIPS32
+Release 5, MIPS32 Release 6, MIPS64, and MIPS64 Release 2, MIPS64
+Release 3, MIPS64 Release 5, and MIPS64 Release 6 ISA processors,
+respectively.  You can also switch instruction sets during the assembly;
+see @ref{MIPS ISA, Directives to override the ISA level}.
 
 @item -mgp32
 @itemx -mfp32
@@ -676,7 +679,7 @@ Small data is not supported for SVR4-style PIC.
 @sc{gnu} @code{@value{AS}} supports an additional directive to change
 the MIPS Instruction Set Architecture level on the fly: @code{.set
 mips@var{n}}.  @var{n} should be a number from 0 to 5, or 32, 32r2, 32r3,
-32r5, 64, 64r2, 64r3 or 64r5.
+32r5, 32r6, 64, 64r2, 64r3, 64r5 or 64r6.
 The values other than 0 make the assembler accept instructions
 for the corresponding ISA level, from that point on in the
 assembly.  @code{.set mips@var{n}} affects not only which instructions
diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 97d6d8322d3..9af5120dbcd 100644
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,91 @@
+2014-09-15  Andrew Bennett  <andrew.bennett@imgtec.com>
+	    Matthew Fortune  <matthew.fortune@imgtec.com>
+
+	* gas/mips/24k-triple-stores-1.s: If testing for r6 prevent
+	non-supported instructions from being tested.
+	* gas/mips/24k-triple-stores-2.s: Likewise.
+	* gas/mips/24k-triple-stores-3.s: Likewise.
+	* gas/mips/24k-triple-stores-6.s: Likewise.
+	* gas/mips/beq.s: Likewise.
+	* gas/mips/eva.s: Likewise.
+	* gas/mips/ld-zero-3.s: Likewise.
+	* gas/mips/mips32-cp2.s: Likewise.
+	* gas/mips/mips32.s: Likewise.
+	* gas/mips/mips4.s: Likewise.
+	* gas/mips/add.s: Don't test the add instructions if r6, and
+	add padding.
+	* gas/mips/add.d: Check for a triple dot not a nop at the end of the
+	disassembly output.
+	* gas/mips/micromips@add.d: Likewise.
+	* gas/mips/mipsr6@24k-branch-delay-1.d: New file.
+	* gas/mips/mipsr6@24k-triple-stores-1.d: New file.
+	* gas/mips/mipsr6@24k-triple-stores-2-llsc.d: New file.
+	* gas/mips/mipsr6@24k-triple-stores-2.d: New file.
+	* gas/mips/mipsr6@24k-triple-stores-3.d: New file.
+	* gas/mips/mipsr6@24k-triple-stores-6.d: New file.
+	* gas/mips/mipsr6@add.d: New file.
+	* gas/mips/mipsr6@attr-gnu-4-1-msingle-float.l: New file.
+	* gas/mips/mipsr6@attr-gnu-4-1-msingle-float.s: New file.
+	* gas/mips/mipsr6@attr-gnu-4-1-msoft-float.l: New file.
+	* gas/mips/mipsr6@attr-gnu-4-1-msoft-float.s: New file.
+	* gas/mips/mipsr6@attr-gnu-4-2-mdouble-float.l: New file.
+	* gas/mips/mipsr6@attr-gnu-4-2-mdouble-float.s: New file.
+	* gas/mips/mipsr6@beq.d: New file.
+	* gas/mips/mipsr6@bge.d: New file.
+	* gas/mips/mipsr6@bgeu.d: New file.
+	* gas/mips/mipsr6@blt.d: New file.
+	* gas/mips/mipsr6@bltu.d: New file.
+	* gas/mips/mipsr6@branch-misc-1.d: New file.
+	* gas/mips/mipsr6@branch-misc-2-64.d: New file.
+	* gas/mips/mipsr6@branch-misc-2pic-64.d: New file.
+	* gas/mips/mipsr6@branch-misc-4-64.d: New file.
+	* gas/mips/mipsr6@cache.d: New file.
+	* gas/mips/mipsr6@eva.d: New file.
+	* gas/mips/mipsr6@jal-svr4pic-noreorder.d: New file.
+	* gas/mips/mipsr6@jal-svr4pic.d: New file.
+	* gas/mips/mipsr6@ld-zero-2.d: New file.
+	* gas/mips/mipsr6@ld-zero-3.d: New file.
+	* gas/mips/mipsr6@loc-swap-dis.d: New file.
+	* gas/mips/mipsr6@mips32-cp2.d: New file.
+	* gas/mips/mipsr6@mips32-imm.d: New file.
+	* gas/mips/mipsr6@mips32.d: New file.
+	* gas/mips/mipsr6@mips32r2.d: New file.
+	* gas/mips/mipsr6@mips4-fp.d: New file.
+	* gas/mips/mipsr6@mips4-fp.l: New file.
+	* gas/mips/mipsr6@mips4-fp.s: New file.
+	* gas/mips/mipsr6@mips4.d: New file.
+	* gas/mips/mipsr6@mips5-fp.d: New file.
+	* gas/mips/mipsr6@mips5-fp.l: New file.
+	* gas/mips/mipsr6@mips5-fp.s: New file.
+	* gas/mips/mipsr6@mips64.d: New file.
+	* gas/mips/mipsr6@msa-branch.d: New file.
+	* gas/mips/mipsr6@msa.d: New file.
+	* gas/mips/mipsr6@pref.d: New file.
+	* gas/mips/mipsr6@relax-swap3.d: New file.
+	* gas/mips/r6-64-n32.d: New file.
+	* gas/mips/r6-64-n64.d: New file.
+	* gas/mips/r6-64-removed.l: New file.
+	* gas/mips/r6-64-removed.s: New file.
+	* gas/mips/r6-64.s: New file.
+	* gas/mips/r6-attr-none-double.d: New file.
+	* gas/mips/r6-n32.d: New file.
+	* gas/mips/r6-n64.d: New file.
+	* gas/mips/r6-removed.l: New file.
+	* gas/mips/r6-removed.s: New file.
+	* gas/mips/r6.d: New file.
+	* gas/mips/r6.s: New file.
+	* gas/mips/mipsr6@mips32-dsp.d: New file.
+	* gas/mips/mipsr6@mips32-dspr2.d: New file.
+	* gas/mips/mipsr6@mips32r2-ill.l: New file.
+	* gas/mips/mipsr6@mips32r2-ill.s: New file.
+	* gas/mips/cache.s: Add r6 instruction varients.
+	* gas/mips/mips.exp: Add support for the mips32r6 and mips64r6
+	architectures.  Also prevent non r6 supported tests from running.
+	Finally, add in support for running the new r6 tests.
+	(run_dump_test_arch): Add support for mipsr6 tests.
+	(run_list_test_arch): Add support for using files of the
+	form arch@testname.l .
+
 2014-09-15  Matthew Fortune  <matthew.fortune@imgtec.com>
 
 	* gas/mips/attr-gnu-4-5-msingle-float.l: New file.
diff --git a/gas/testsuite/gas/mips/24k-triple-stores-1.s b/gas/testsuite/gas/mips/24k-triple-stores-1.s
index 87c67a9bac7..8ce61a35128 100644
--- a/gas/testsuite/gas/mips/24k-triple-stores-1.s
+++ b/gas/testsuite/gas/mips/24k-triple-stores-1.s
@@ -19,6 +19,7 @@ foo:
 	sw      $5,24($sp)
 	sw      $6,32($sp)
 
+	.ifndef r6
 	swr     $2,0($sp)
 	swr     $3,8($sp)
 	swr     $4,16($sp)
@@ -30,6 +31,7 @@ foo:
 	swl     $4,16($sp)
 	swl     $5,24($sp)
 	swl     $6,32($sp)
+	.endif
 
 	sc      $2,0($sp)
 	sc      $3,8($sp)
@@ -63,6 +65,7 @@ foo:
 	sdc2    $5,24($sp)
 	sdc2    $6,32($sp)
 
+	.ifndef r6
 	swxc1   $f0,$9($8)
 	swxc1   $f1,$10($8)
 	swxc1   $f2,$11($8)
@@ -80,6 +83,7 @@ foo:
 	suxc1   $f4,$11($8)
 	suxc1   $f6,$12($8)
 	suxc1   $f8,$13($8)
+	.endif
 
 # Force at least 8 (non-delay-slot) zero bytes,to make 'objdump' print ...
 	.align	2
diff --git a/gas/testsuite/gas/mips/24k-triple-stores-2.s b/gas/testsuite/gas/mips/24k-triple-stores-2.s
index 13b9cd464db..9386d9cb2f2 100644
--- a/gas/testsuite/gas/mips/24k-triple-stores-2.s
+++ b/gas/testsuite/gas/mips/24k-triple-stores-2.s
@@ -16,6 +16,7 @@ foo:
 	sw      $4,8($sp)
 	break
 
+	.ifndef r6
 	swr      $2,0($sp)
 	swr      $3,-16($sp)
 	swr      $4,16($sp)
@@ -26,6 +27,7 @@ foo:
 	swl      $4,16($sp)
 	swl      $5,24($sp)
 	swl      $6,0($sp)
+	.endif
 
 # Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
 	.align	2
diff --git a/gas/testsuite/gas/mips/24k-triple-stores-3.s b/gas/testsuite/gas/mips/24k-triple-stores-3.s
index 1a54c643b70..32e1400c514 100644
--- a/gas/testsuite/gas/mips/24k-triple-stores-3.s
+++ b/gas/testsuite/gas/mips/24k-triple-stores-3.s
@@ -60,6 +60,7 @@ foo:
 	sw      $4,15($8)	
 	break
 
+	.ifndef r6
 	swl      $2,4($sp)
 	swl      $3,10($sp)
 	swl      $4,17($sp)
@@ -94,6 +95,7 @@ foo:
 	swl      $3,17($8)
 	swr      $4,28($8)
 	break		
+	.endif
 
 # Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
 	.align	2
diff --git a/gas/testsuite/gas/mips/24k-triple-stores-6.s b/gas/testsuite/gas/mips/24k-triple-stores-6.s
index eb087e17b0e..49e236b9bfc 100644
--- a/gas/testsuite/gas/mips/24k-triple-stores-6.s
+++ b/gas/testsuite/gas/mips/24k-triple-stores-6.s
@@ -1,6 +1,7 @@
 	# Store macros
 
 foo:
+	.ifndef r6
 	usw      $ra,80($sp)
 	usw      $s3,88($sp)
 	usw      $s8,96($sp)
@@ -10,6 +11,7 @@ foo:
 	ush      $s3,88($sp)
 	ush      $s8,96($sp)
 	break
+	.endif
 
 	# swc1 macro
 	s.s      $f0,80($sp)
diff --git a/gas/testsuite/gas/mips/add.d b/gas/testsuite/gas/mips/add.d
index 1eb538b97f6..e5247f2d627 100644
--- a/gas/testsuite/gas/mips/add.d
+++ b/gas/testsuite/gas/mips/add.d
@@ -18,4 +18,4 @@ Disassembly of section .text:
 0+0020 <[^>]*> ori	at,at,0xa5a5
 0+0024 <[^>]*> add	a0,a0,at
 0+0028 <[^>]*> addiu	a0,a0,1
-0+002c <[^>]*> nop
+	\.\.\.
diff --git a/gas/testsuite/gas/mips/add.s b/gas/testsuite/gas/mips/add.s
index 44e964bdd22..5702d921a7c 100644
--- a/gas/testsuite/gas/mips/add.s
+++ b/gas/testsuite/gas/mips/add.s
@@ -1,16 +1,18 @@
 # Source file used to test the add macro.
 	
 foo:
+	.ifndef r6
 	add	$4,$4,0
 	add	$4,$4,1
 	add	$4,$4,0x8000
 	add	$4,$4,-0x8000
 	add	$4,$4,0x10000
 	add	$4,$4,0x1a5a5
-	
+	.endif
+
 # addu is handled the same way add is; just confirm that it isn't
 # totally broken.
 	addu	$4,$4,1
 
-# Round to a 16 byte boundary, for ease in testing multiple targets.
-	nop
+	.align 2
+	.space 8
diff --git a/gas/testsuite/gas/mips/beq.s b/gas/testsuite/gas/mips/beq.s
index d9e4c606eb4..bed69165474 100644
--- a/gas/testsuite/gas/mips/beq.s
+++ b/gas/testsuite/gas/mips/beq.s
@@ -12,10 +12,12 @@ text_label:
 # bne is handled by the same code as beq.  Just sanity check.
 	bne	$4,0,text_label
 
+	.ifndef r6
 # Test that branches which overflow are converted to jumps.
 	.space	0x20000
 	b	text_label
 	bal	text_label
+	.endif
 
 # Branch to an external label.
 #	b	external_label
diff --git a/gas/testsuite/gas/mips/cache.s b/gas/testsuite/gas/mips/cache.s
index 5f66c4d77cc..6b8cc224f25 100644
--- a/gas/testsuite/gas/mips/cache.s
+++ b/gas/testsuite/gas/mips/cache.s
@@ -15,6 +15,10 @@
 	.text
 text_label:
 
+	.ifdef r6
+	cache	5, 255($2)
+	cache	5, -256($3)
+	.else
 	cache	5, 2047($2)
 	cache	5, -2048($3)
 
@@ -35,6 +39,7 @@ text_label:
 	cache	5, -32769($9)
 	cache	5, 36864($10)
 	cache	5, -36865($11)
+	.endif
 
 # Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
 	.align	2
diff --git a/gas/testsuite/gas/mips/eva.s b/gas/testsuite/gas/mips/eva.s
index f7bea002506..7865fb4945c 100644
--- a/gas/testsuite/gas/mips/eva.s
+++ b/gas/testsuite/gas/mips/eva.s
@@ -230,6 +230,7 @@ test_eva:
 	lwe	$29,2147483647
 	lwe	$30,($31)
 	lwe	$0,MYDATA
+	.ifndef r6
 	lwle	$2,-256($3)
 	lwle	$4,-256
 	lwle	$5,255($6)
@@ -306,6 +307,7 @@ test_eva:
 	lwre	$19,2147483647
 	lwre	$20,($21)
 	lwre	$22,MYDATA
+	.endif
 	sbe	$23,-256($24)
 	sbe	$25,-256
 	sbe	$26,255($27)
@@ -458,6 +460,7 @@ test_eva:
 	swe	$30,2147483647
 	swe	$31,($0)
 	swe	$2,MYDATA
+	.ifndef r6
 	swle	$3,-256($4)
 	swle	$5,-256
 	swle	$6,255($7)
@@ -534,6 +537,7 @@ test_eva:
 	swre	$20,2147483647
 	swre	$21,($22)
 	swre	$23,MYDATA
+	.endif
 	cachee	24,-256($25)
 	cachee	26,-256
 	cachee	27,255($28)
diff --git a/gas/testsuite/gas/mips/micromips@add.d b/gas/testsuite/gas/mips/micromips@add.d
index ea36af51752..61c6cda1519 100644
--- a/gas/testsuite/gas/mips/micromips@add.d
+++ b/gas/testsuite/gas/mips/micromips@add.d
@@ -19,5 +19,4 @@ Disassembly of section \.text:
 [0-9a-f]+ <[^>]*> 5021 a5a5 	ori	at,at,0xa5a5
 [0-9a-f]+ <[^>]*> 0024 2110 	add	a0,a0,at
 [0-9a-f]+ <[^>]*> 3084 0001 	addiu	a0,a0,1
-[0-9a-f]+ <[^>]*> 0c00      	nop
-[0-9a-f]+ <[^>]*> 0c00      	nop
+	\.\.\.
diff --git a/gas/testsuite/gas/mips/mips.exp b/gas/testsuite/gas/mips/mips.exp
index 4cf6e7db8b2..4afd367b271 100644
--- a/gas/testsuite/gas/mips/mips.exp
+++ b/gas/testsuite/gas/mips/mips.exp
@@ -327,6 +327,9 @@ proc run_dump_test_arch { name opts arch } {
     if { [ string match "octeon*" $proparch ] && $proparch != "octeon" } {
 	lappend prefixes octeon@
     }
+    if { [ string match "mips*r6" $proparch ]} {
+	lappend prefixes mipsr6@
+    }
     foreach prefix ${prefixes} {
 	set archname ${prefix}${name}
 	if { [file exists "$srcdir/$subdir/${archname}.d"] } {
@@ -366,9 +369,25 @@ proc run_dump_test_arches { name args } {
 # Invoke "run_list_test" for test NAME with additional assembler options OPTS.
 # Add the assembler flags that are associated with architecture ARCH.
 proc run_list_test_arch { name opts arch } {
-    global subdir
+    global subdir srcdir
 
     set testname "MIPS $name ([concat $opts [mips_arch_displayname $arch]])"
+    set proparch [lindex [mips_arch_properties $arch 0] 0]
+    set prefixes [list ${proparch}@ ]
+    if { [ string match "octeon*" $proparch ] && $proparch != "octeon" } {
+	lappend prefixes octeon@
+    }
+    if { [ string match "mips*r6" $proparch ]} {
+	lappend prefixes mipsr6@
+    }
+    foreach prefix ${prefixes} {
+	set archname ${prefix}${name}
+	if { [file exists "$srcdir/$subdir/${archname}.l"] } {
+	    set name $archname
+	    break
+	}
+    }
+
     if [catch {run_list_test \
 		   $name \
 		   [concat $opts [mips_arch_as_flags $arch]] \
@@ -428,6 +447,10 @@ mips_arch_create mips32r5 32	mips32r3 { fpisa3 fpisa4 fpisa5 ror } \
 			{ -march=mips32r5 -mtune=mips32r5 } \
 			{ -mmips:isa32r5 } \
 			{ mipsisa32r5-*-* mipsisa32r5el-*-* }
+mips_arch_create mips32r6 32	mips32r5 { fpisa3 fpisa4 fpisa5 ror } \
+			{ -march=mips32r6 -mtune=mips32r6 --defsym r6=} \
+			{ -mmips:isa32r6 } \
+			{ mipsisa32r6-*-* mipsisa32r6el-*-* }
 mips_arch_create mips64	64	mips5	{ mips32 } \
 			{ -march=mips64 -mtune=mips64 } { -mmips:isa64 } \
 			{ mipsisa64-*-* mipsisa64el-*-* }
@@ -443,6 +466,10 @@ mips_arch_create mips64r5 64	mips64r3 { mips32r5 ror } \
 			{ -march=mips64r5 -mtune=mips64r5 } \
 			{ -mmips:isa64r5 } \
 			{ mipsisa64r5-*-* mipsisa64r5el-*-* }
+mips_arch_create mips64r6 64	mips64r5 { mips32r6 ror } \
+			{ -march=mips64r6 -mtune=mips64r6 --defsym r6=} \
+			{ -mmips:isa64r6 } \
+			{ mipsisa64r6-*-* mipsisa64r6el-*-* }
 mips_arch_create mips16	32	{}	{} \
 			{ -march=mips1 -mips16 } { -mmips:16 }
 mips_arch_create micromips 64	mips64r2 {} \
@@ -520,7 +547,7 @@ if { [istarget mips*-*-vxworks*] } {
     run_dump_test_arches "bgeu"		[mips_arch_list_matching mips1]
     run_dump_test_arches "blt"		[mips_arch_list_matching mips1]
     run_dump_test_arches "bltu"		[mips_arch_list_matching mips1]
-    run_dump_test_arches "branch-likely" [mips_arch_list_matching mips2]
+    run_dump_test_arches "branch-likely" [mips_arch_list_matching mips2 !mips32r6]
     run_dump_test_arches "branch-misc-1" [mips_arch_list_matching mips1]
     run_dump_test_arches "branch-misc-2" [mips_arch_list_matching mips1]
     run_dump_test_arches "branch-misc-2pic" [mips_arch_list_matching mips1]
@@ -554,9 +581,11 @@ if { [istarget mips*-*-vxworks*] } {
     run_dump_test "eret-2"
     run_dump_test "eret-3"
     run_dump_test_arches "fix-rm7000-1" \
-					[mips_arch_list_matching mips3 !singlefloat]
+					[mips_arch_list_matching mips3 !singlefloat \
+						!mips64r6]
     run_dump_test_arches "fix-rm7000-2" \
-					[mips_arch_list_matching mips3 !singlefloat]
+					[mips_arch_list_matching mips3 !singlefloat \
+						!mips64r6]
     run_dump_test_arches "24k-branch-delay-1" \
 					[mips_arch_list_matching mips1]
     run_dump_test_arches "24k-triple-stores-1" \
@@ -676,9 +705,9 @@ if { [istarget mips*-*-vxworks*] } {
     run_list_test_arches "mips4-fp" "-32 -msoft-float" \
 					[mips_arch_list_matching fpisa4]
     run_dump_test_arches "mips4-branch-likely" \
-					[mips_arch_list_matching mips4]
+					[mips_arch_list_matching mips4 !mips32r6]
     run_list_test_arches "mips4-branch-likely" "-32 -msoft-float" \
-					[mips_arch_list_matching mips4]
+					[mips_arch_list_matching mips4 !mips32r6]
     run_dump_test_arches "mips5-fp" "-32" \
 					[mips_arch_list_matching fpisa5]
     run_dump_test_arches "mips5-fp" "-mabi=o64" \
@@ -694,8 +723,8 @@ if { [istarget mips*-*-vxworks*] } {
     run_dump_test "sb"
     run_dump_test "trunc"
     run_dump_test "ulh"
-    run_dump_test_arches "ulh2-eb"	[mips_arch_list_matching mips1]
-    run_dump_test_arches "ulh2-el"	[mips_arch_list_matching mips1]
+    run_dump_test_arches "ulh2-eb"	[mips_arch_list_matching mips1 !mips32r6]
+    run_dump_test_arches "ulh2-el"	[mips_arch_list_matching mips1 !mips32r6]
     run_dump_test "ulh-svr4pic"
     run_dump_test "ulh-xgot"
     run_dump_test "ulw"
@@ -703,19 +732,24 @@ if { [istarget mips*-*-vxworks*] } {
     run_dump_test "ush"
     run_dump_test "usw"
     run_dump_test "usd"
-    run_dump_test_arches "ulw2-eb" [mips_arch_list_matching mips1 !gpr_ilocks]
-    run_dump_test_arches "ulw2-eb-ilocks" [mips_arch_list_matching gpr_ilocks]
-    run_dump_test_arches "ulw2-el" [mips_arch_list_matching mips1 !gpr_ilocks]
-    run_dump_test_arches "ulw2-el-ilocks" [mips_arch_list_matching gpr_ilocks]
-
-    run_dump_test_arches "uld2-eb" [mips_arch_list_matching mips3]
-    run_dump_test_arches "uld2-el" [mips_arch_list_matching mips3]
+    run_dump_test_arches "ulw2-eb" [mips_arch_list_matching mips1 !gpr_ilocks \
+					!mips32r6]
+    run_dump_test_arches "ulw2-eb-ilocks" [mips_arch_list_matching gpr_ilocks \
+					!mips32r6]
+    run_dump_test_arches "ulw2-el" [mips_arch_list_matching mips1 !gpr_ilocks \
+					!mips32r6]
+    run_dump_test_arches "ulw2-el-ilocks" [mips_arch_list_matching gpr_ilocks \
+					!mips32r6]
+
+    run_dump_test_arches "uld2-eb" [mips_arch_list_matching mips3 !mips32r6]
+    run_dump_test_arches "uld2-el" [mips_arch_list_matching mips3 !mips32r6]
 
     run_dump_test "mips16"
     run_dump_test "mips16-64"
     run_dump_test "mips16-macro"
     # Check MIPS16e extensions
-    run_dump_test_arches "mips16e" [mips_arch_list_matching mips32 !micromips]
+    run_dump_test_arches "mips16e" [mips_arch_list_matching mips32 !micromips \
+					!mips32r6]
     # Check jalx handling
     run_dump_test "mips16-jalx"
     run_dump_test "mips-jalx"
@@ -788,18 +822,18 @@ if { [istarget mips*-*-vxworks*] } {
 	run_dump_test "xlr-ext"
     }
 
-    run_dump_test_arches "relax"	[mips_arch_list_matching mips2]
-    run_dump_test_arches "relax-at"	[mips_arch_list_matching mips2]
+    run_dump_test_arches "relax"	[mips_arch_list_matching mips2 !mips32r6]
+    run_dump_test_arches "relax-at"	[mips_arch_list_matching mips2 !mips32r6]
     run_dump_test "relax-swap1-mips1"
     run_dump_test "relax-swap1-mips2"
     run_dump_test "relax-swap2"
     run_dump_test_arches "relax-swap3"	[mips_arch_list_all]
     run_list_test_arches "relax-bc1any" "-mips3d -mabi=o64 -relax-branch" \
 					[mips_arch_list_matching mips64 \
-					    !micromips]
+					    !micromips !mips32r6]
     run_list_test_arches "relax-bposge" "-mdsp -relax-branch" \
 					[mips_arch_list_matching mips64r2 \
-					    !micromips]
+					    !micromips !mips32r6]
 
     run_dump_test_arches "eva"		[mips_arch_list_matching mips32r2 !octeon]
 
@@ -1118,11 +1152,13 @@ if { [istarget mips*-*-vxworks*] } {
     run_dump_test "mips32-sync"
     run_dump_test_arches "mips32r2-sync" \
 					[mips_arch_list_matching mips32r2]
-    run_dump_test_arches "alnv_ps-swap" [mips_arch_list_matching fpisa5]
+    run_dump_test_arches "alnv_ps-swap" [mips_arch_list_matching fpisa5 \
+						!mips32r6]
     run_dump_test_arches "cache" [lsort -dictionary -unique [concat \
 					[mips_arch_list_matching mips3] \
 					[mips_arch_list_matching mips32] ] ]
-    run_dump_test_arches "daddi"	[mips_arch_list_matching mips3]
+    run_dump_test_arches "daddi"	[mips_arch_list_matching mips3 \
+						!mips32r6]
     run_dump_test_arches "pref" [lsort -dictionary -unique [concat \
 					[mips_arch_list_matching mips4] \
 					[mips_arch_list_matching mips32] ] ]
@@ -1186,15 +1222,15 @@ if { [istarget mips*-*-vxworks*] } {
 
     # Start with MIPS II to avoid load delay nops.
     run_dump_test_arches "ld-reloc"	[mips_arch_list_matching mips2]
-    run_dump_test_arches "ulw-reloc"	[mips_arch_list_matching mips2]
-    run_dump_test_arches "ulh-reloc"	[mips_arch_list_matching mips2]
+    run_dump_test_arches "ulw-reloc"	[mips_arch_list_matching mips2 !mips32r6]
+    run_dump_test_arches "ulh-reloc"	[mips_arch_list_matching mips2 !mips32r6]
 
     run_dump_test "l_d-reloc"
     run_list_test "bltzal"
 
     run_dump_test_arches "msa"		[mips_arch_list_matching mips32r2]
     run_dump_test_arches "msa64"	[mips_arch_list_matching mips64r2]
-    run_dump_test_arches "msa-relax"	[mips_arch_list_matching mips32r2]
+    run_dump_test_arches "msa-relax"	[mips_arch_list_matching mips32r2 !mips32r6]
     run_dump_test_arches "msa-branch"	[mips_arch_list_matching mips32r2]
 
     run_dump_test_arches "xpa"		[mips_arch_list_matching mips32r2 !micromips]
@@ -1214,7 +1250,7 @@ if { [istarget mips*-*-vxworks*] } {
     run_dump_test_arches "attr-gnu-4-0" "-64" \
 				    [mips_arch_list_matching mips3]
     run_dump_test_arches "attr-gnu-4-0" "-mfp32 -32" \
-				    [mips_arch_list_matching mips1]
+				    [mips_arch_list_matching mips1 !mips32r6]
     run_dump_test_arches "attr-gnu-4-0" "-mfpxx -32" \
 				    [mips_arch_list_matching mips2 !r5900]
     run_dump_test_arches "attr-gnu-4-0" "-mfp64 -32" \
@@ -1232,7 +1268,9 @@ if { [istarget mips*-*-vxworks*] } {
     run_dump_test_arches "attr-gnu-4-0" "-msoft-float -64" \
 				    [mips_arch_list_matching mips3]
     run_dump_test_arches "attr-none-double" "-32" \
-				    [mips_arch_list_matching mips1]
+				    [mips_arch_list_matching mips1 !mips32r6]
+    run_dump_test_arches "r6-attr-none-double" "-32" \
+				    [mips_arch_list_matching mips32r6]
     run_dump_test_arches "attr-none-double" "-64" \
 				    [mips_arch_list_matching mips3]
     run_dump_test_arches "attr-none-o32-fpxx" \
@@ -1256,7 +1294,7 @@ if { [istarget mips*-*-vxworks*] } {
     run_list_test_arches "attr-gnu-4-1-mfp64" "-32 -mfp64" \
 				    [mips_arch_list_matching mips32r2]
     run_list_test_arches "attr-gnu-4-1-mfp32" "-64 -mfp32" \
-				    [mips_arch_list_matching mips3]
+				    [mips_arch_list_matching mips3 !mips64r6]
     run_list_test_arches "attr-gnu-4-1-msingle-float" "-32 -msingle-float" \
 				    [mips_arch_list_matching mips1]
     run_list_test_arches "attr-gnu-4-1-msoft-float" "-32 -msoft-float" \
@@ -1264,12 +1302,12 @@ if { [istarget mips*-*-vxworks*] } {
     run_dump_test_arches "attr-gnu-4-1" "-32 -mfpxx" \
 				    [mips_arch_list_matching mips2 !r5900]
     run_dump_test_arches "attr-gnu-4-1" "-32 -mfp32" \
-				    [mips_arch_list_matching mips1]
+				    [mips_arch_list_matching mips1 !mips32r6]
     run_dump_test_arches "attr-gnu-4-1" "-64 -mfp64" \
 				    [mips_arch_list_matching mips3]
 
     run_list_test_arches "attr-gnu-4-2-mdouble-float" "-32 -mfp32" \
-				    [mips_arch_list_matching mips1]
+				    [mips_arch_list_matching mips1 !mips32r6]
     run_list_test_arches "attr-gnu-4-2-mdouble-float" "-32 -mfpxx" \
 				    [mips_arch_list_matching mips2 !r5900]
     run_list_test_arches "attr-gnu-4-2-mdouble-float" "-32 -mfp64" \
@@ -1287,7 +1325,7 @@ if { [istarget mips*-*-vxworks*] } {
 				    [mips_arch_list_matching mips3]
 
     run_list_test_arches "attr-gnu-4-3-mhard-float" "-32 -mfp32" \
-				    [mips_arch_list_matching mips1]
+				    [mips_arch_list_matching mips1 !mips32r6]
     run_list_test_arches "attr-gnu-4-3-mhard-float" "-32 -mfpxx" \
 				    [mips_arch_list_matching mips2 !r5900]
     run_list_test_arches "attr-gnu-4-3-mhard-float" "-32 -mfp64" \
@@ -1305,7 +1343,7 @@ if { [istarget mips*-*-vxworks*] } {
 				    [mips_arch_list_matching mips3]
  
     run_list_test_arches "attr-gnu-4-4" "-32 -mfp32" \
-				    [mips_arch_list_matching mips1]
+				    [mips_arch_list_matching mips1 !mips32r6]
     run_list_test_arches "attr-gnu-4-4" "-32 -mfpxx" \
 				    [mips_arch_list_matching mips2 !r5900]
     run_list_test_arches "attr-gnu-4-4" "-32 -mfp64" \
@@ -1320,7 +1358,7 @@ if { [istarget mips*-*-vxworks*] } {
 				    [mips_arch_list_matching mips1]
 
     run_list_test_arches "attr-gnu-4-5" "-32 -mfp32" \
-				    [mips_arch_list_matching mips1]
+				    [mips_arch_list_matching mips1 !mips32r6]
     run_list_test_arches "attr-gnu-4-5" "-32 -mfp64" \
 				    [mips_arch_list_matching mips32r2]
     run_list_test_arches "attr-gnu-4-5" "-32 -mfp64 -mno-odd-spreg" \
@@ -1335,7 +1373,7 @@ if { [istarget mips*-*-vxworks*] } {
 				    [mips_arch_list_matching mips2 !r5900]
 
     run_list_test_arches "attr-gnu-4-6" "-32 -mfp32" \
-				    [mips_arch_list_matching mips1]
+				    [mips_arch_list_matching mips1 !mips32r6]
     run_list_test_arches "attr-gnu-4-6-noodd" "-32 -mfp64 -mno-odd-spreg" \
 				    [mips_arch_list_matching mips32r2]
     run_list_test_arches "attr-gnu-4-6-64" "-64 -mfp64" \
@@ -1350,7 +1388,7 @@ if { [istarget mips*-*-vxworks*] } {
 				    [mips_arch_list_matching mips32r2]
 
     run_list_test_arches "attr-gnu-4-7" "-32 -mfp32" \
-				    [mips_arch_list_matching mips1]
+				    [mips_arch_list_matching mips1 !mips32r6]
     run_list_test_arches "attr-gnu-4-7-odd" "-32 -mfp64" \
 				    [mips_arch_list_matching mips32r2]
     run_list_test_arches "attr-gnu-4-7-64" "-64 -mfp64" \
@@ -1390,11 +1428,22 @@ if { [istarget mips*-*-vxworks*] } {
     run_dump_test_arches "odd-spreg" "-mfp32" [mips_arch_list_matching oddspreg]
     run_dump_test_arches "odd-spreg" "-mfpxx" [mips_arch_list_matching oddspreg]
     run_dump_test_arches "odd-spreg" "-mfp64" [mips_arch_list_matching mips32r2]
-    run_dump_test_arches "no-odd-spreg" "-mfp32" [mips_arch_list_matching mips1]
+    run_dump_test_arches "no-odd-spreg" "-mfp32" [mips_arch_list_matching mips1 \
+							!mips32r6]
     run_dump_test_arches "no-odd-spreg" "-mfpxx" [mips_arch_list_matching mips2 !r5900]
     run_dump_test_arches "no-odd-spreg" "-mfp64" [mips_arch_list_matching mips32r2]
     run_dump_test "module-check"
     run_list_test "module-check-warn" "-32"
 
     run_dump_test "li-d"
+
+    run_dump_test_arches "r6"		[mips_arch_list_matching mips32r6]
+    if $has_newabi {
+	run_dump_test_arches "r6-n32"	[mips_arch_list_matching mips64r6]
+	run_dump_test_arches "r6-n64"	[mips_arch_list_matching mips64r6]
+	run_dump_test_arches "r6-64-n32"	[mips_arch_list_matching mips64r6]
+	run_dump_test_arches "r6-64-n64"	[mips_arch_list_matching mips64r6]
+    }
+    run_list_test_arches "r6-removed"	"-32" [mips_arch_list_matching mips32r6]
+    run_list_test_arches "r6-64-removed"	[mips_arch_list_matching mips64r6]
 }
diff --git a/gas/testsuite/gas/mips/mips32-cp2.s b/gas/testsuite/gas/mips/mips32-cp2.s
index 182ba872e28..22e0c74c6b0 100644
--- a/gas/testsuite/gas/mips/mips32-cp2.s
+++ b/gas/testsuite/gas/mips/mips32-cp2.s
@@ -8,6 +8,7 @@ text_label:
       # unprivileged coprocessor instructions.
       # these tests use cp2 to avoid other (cp0, fpu, prefetch) opcodes.
 
+	.ifndef r6
       bc2f    text_label
       nop
       bc2fl   text_label
@@ -16,6 +17,7 @@ text_label:
       nop
       bc2tl   text_label
       nop
+	.endif
       # XXX other BCzCond encodings not currently expressable
       cfc2    $1, $2
       cop2    0x1234567               # disassembles as c2 ...
@@ -28,6 +30,7 @@ text_label:
       mtc2    $8, $9, 7
 
 
+	.ifndef r6
       # Cop2 branches with cond code number, like bc1t/f
       bc2f    $cc0,text_label
       nop
@@ -37,3 +40,4 @@ text_label:
       nop
       bc2tl   $cc7,text_label
       nop
+	.endif
diff --git a/gas/testsuite/gas/mips/mips32.s b/gas/testsuite/gas/mips/mips32.s
index 5051d5a480c..35f7d424488 100644
--- a/gas/testsuite/gas/mips/mips32.s
+++ b/gas/testsuite/gas/mips/mips32.s
@@ -10,20 +10,25 @@ text_label:
 
       clo     $1, $2
       clz     $3, $4
+	.ifndef r6
       madd    $5, $6
       maddu   $7, $8
       msub    $9, $10
       msubu   $11, $12
+	.endif
       mul     $13, $14, $15
       pref    4, ($16)
+	.ifndef r6
       pref    4, 2047($17)
       pref    4, -2048($18)
+	.endif
       ssnop
 
 
       # privileged instructions
 
       cache   5, ($1)
+	.ifndef r6
       cache   5, 2047($2)
       cache   5, -2048($3)
       .set at
@@ -32,6 +37,7 @@ text_label:
       cache   5, 32768
       cache   5, -32769
       .set noat
+	.endif
       eret
       tlbp
       tlbr
diff --git a/gas/testsuite/gas/mips/mips4.s b/gas/testsuite/gas/mips/mips4.s
index 7f5457c9501..1f4cdc7bd88 100644
--- a/gas/testsuite/gas/mips/mips4.s
+++ b/gas/testsuite/gas/mips/mips4.s
@@ -1,8 +1,10 @@
 # Source file used to test -mips4 *non-fp* instructions.
 
 text_label:	
+	.ifndef r6
 	movn	$4,$6,$6
 	movz	$4,$6,$6
+	.endif
 	# It used to be disabled due to a clash with lwc3.
 	pref	4,0($4)
 
diff --git a/gas/testsuite/gas/mips/mipsr6@24k-branch-delay-1.d b/gas/testsuite/gas/mips/mipsr6@24k-branch-delay-1.d
new file mode 100644
index 00000000000..928eae92dfe
--- /dev/null
+++ b/gas/testsuite/gas/mips/mipsr6@24k-branch-delay-1.d
@@ -0,0 +1,23 @@
+#objdump: -dr
+#as: -mfix-24k -32
+#source: 24k-branch-delay-1.s
+#name: 24K: Delay slot filling
+
+.*: +file format .*mips.*
+
+Disassembly of section .text:
+0+ <.*>:
+   0:	24620005 	addiu	v0,v1,5
+   4:	8c440000 	lw	a0,0\(v0\)
+   8:	ac430000 	sw	v1,0\(v0\)
+   c:	ac430008 	sw	v1,8\(v0\)
+  10:	00000000 	nop
+  14:	ac430010 	sw	v1,16\(v0\)
+  18:	1060ffff 	beqz	v1,18 <.*>
+[	]*18: .*R_MIPS_PC16	.L1
+  1c:	00000000 	nop
+  20:	8c430008 	lw	v1,8\(v0\)
+
+0+24 <.L1>:
+  24:	8c450010 	lw	a1,16\(v0\)
+	...
diff --git a/gas/testsuite/gas/mips/mipsr6@24k-triple-stores-1.d b/gas/testsuite/gas/mips/mipsr6@24k-triple-stores-1.d
new file mode 100644
index 00000000000..ca334a6bfa1
--- /dev/null
+++ b/gas/testsuite/gas/mips/mipsr6@24k-triple-stores-1.d
@@ -0,0 +1,68 @@
+#objdump: -dr
+#as: -mfix-24k -32
+#source: 24k-triple-stores-1.s
+#name: 24K: Triple Store (Opcode Check)
+
+.*: +file format .*mips.*
+
+Disassembly of section .text:
+0+ <.*>:
+   0:	a3a20000 	sb	v0,0\(sp\)
+   4:	a3a30008 	sb	v1,8\(sp\)
+   8:	00000000 	nop
+   c:	a3a40010 	sb	a0,16\(sp\)
+  10:	a3a50018 	sb	a1,24\(sp\)
+  14:	00000000 	nop
+  18:	a3a60020 	sb	a2,32\(sp\)
+  1c:	a7a20000 	sh	v0,0\(sp\)
+  20:	a7a30008 	sh	v1,8\(sp\)
+  24:	00000000 	nop
+  28:	a7a40010 	sh	a0,16\(sp\)
+  2c:	a7a50018 	sh	a1,24\(sp\)
+  30:	00000000 	nop
+  34:	a7a60020 	sh	a2,32\(sp\)
+  38:	afa20000 	sw	v0,0\(sp\)
+  3c:	afa30008 	sw	v1,8\(sp\)
+  40:	00000000 	nop
+  44:	afa40010 	sw	a0,16\(sp\)
+  48:	afa50018 	sw	a1,24\(sp\)
+  4c:	00000000 	nop
+  50:	afa60020 	sw	a2,32\(sp\)
+  54:	7fa20026 	sc	v0,0\(sp\)
+  58:	00000000 	nop
+  5c:	7fa30426 	sc	v1,8\(sp\)
+  60:	7fa40826 	sc	a0,16\(sp\)
+  64:	00000000 	nop
+  68:	7fa50c26 	sc	a1,24\(sp\)
+  6c:	7fa61026 	sc	a2,32\(sp\)
+  70:	00000000 	nop
+  74:	e7a20000 	swc1	\$f2,0\(sp\)
+  78:	e7a30008 	swc1	\$f3,8\(sp\)
+  7c:	00000000 	nop
+  80:	e7a40010 	swc1	\$f4,16\(sp\)
+  84:	e7a50018 	swc1	\$f5,24\(sp\)
+  88:	00000000 	nop
+  8c:	e7a60020 	swc1	\$f6,32\(sp\)
+  90:	4962e800 	swc2	\$2,0\(sp\)
+  94:	00000000 	nop
+  98:	4963e808 	swc2	\$3,8\(sp\)
+  9c:	4964e810 	swc2	\$4,16\(sp\)
+  a0:	00000000 	nop
+  a4:	4965e818 	swc2	\$5,24\(sp\)
+  a8:	4966e820 	swc2	\$6,32\(sp\)
+  ac:	00000000 	nop
+  b0:	f7a20000 	sdc1	\$f2,0\(sp\)
+  b4:	f7a30008 	sdc1	\$f3,8\(sp\)
+  b8:	00000000 	nop
+  bc:	f7a40010 	sdc1	\$f4,16\(sp\)
+  c0:	f7a50018 	sdc1	\$f5,24\(sp\)
+  c4:	00000000 	nop
+  c8:	f7a60020 	sdc1	\$f6,32\(sp\)
+  cc:	49e2e800 	sdc2	\$2,0\(sp\)
+  d0:	00000000 	nop
+  d4:	49e3e808 	sdc2	\$3,8\(sp\)
+  d8:	49e4e810 	sdc2	\$4,16\(sp\)
+  dc:	00000000 	nop
+  e0:	49e5e818 	sdc2	\$5,24\(sp\)
+  e4:	49e6e820 	sdc2	\$6,32\(sp\)
+	...
diff --git a/gas/testsuite/gas/mips/mipsr6@24k-triple-stores-2-llsc.d b/gas/testsuite/gas/mips/mipsr6@24k-triple-stores-2-llsc.d
new file mode 100644
index 00000000000..8119bce2c84
--- /dev/null
+++ b/gas/testsuite/gas/mips/mipsr6@24k-triple-stores-2-llsc.d
@@ -0,0 +1,17 @@
+#objdump: -dr
+#as: -mfix-24k -32
+#source: 24k-triple-stores-2-llsc.s
+#name: 24K: Triple Store (Range Check, sc)
+
+.*: +file format .*mips.*
+
+Disassembly of section .text:
+0+ <.*>:
+   0:	7fa21026 	sc	v0,32\(sp\)
+   4:	7fa30426 	sc	v1,8\(sp\)
+   8:	00000000 	nop
+   c:	7fa4fc26 	sc	a0,-8\(sp\)
+  10:	7fa50026 	sc	a1,0\(sp\)
+  14:	00000000 	nop
+  18:	7fa61026 	sc	a2,32\(sp\)
+	\.\.\.
diff --git a/gas/testsuite/gas/mips/mipsr6@24k-triple-stores-2.d b/gas/testsuite/gas/mips/mipsr6@24k-triple-stores-2.d
new file mode 100644
index 00000000000..eb3ee9656c0
--- /dev/null
+++ b/gas/testsuite/gas/mips/mipsr6@24k-triple-stores-2.d
@@ -0,0 +1,24 @@
+#objdump: -dr
+#as: -mfix-24k -32
+#source: 24k-triple-stores-2.s
+#name: 24K: Triple Store (Range Check)
+
+.*: +file format .*mips.*
+
+Disassembly of section .text:
+0+ <.*>:
+   0:	a3a20000 	sb	v0,0\(sp\)
+   4:	a3a3000a 	sb	v1,10\(sp\)
+   8:	00000000 	nop
+   c:	a3a4001f 	sb	a0,31\(sp\)
+  10:	0000000d 	break
+  14:	a7a20000 	sh	v0,0\(sp\)
+  18:	a7a3fff0 	sh	v1,-16\(sp\)
+  1c:	a7a4ffe0 	sh	a0,-32\(sp\)
+  20:	0000000d 	break
+  24:	afa20000 	sw	v0,0\(sp\)
+  28:	afa3fff8 	sw	v1,-8\(sp\)
+  2c:	00000000 	nop
+  30:	afa40008 	sw	a0,8\(sp\)
+  34:	0000000d 	break
+	\.\.\.
diff --git a/gas/testsuite/gas/mips/mipsr6@24k-triple-stores-3.d b/gas/testsuite/gas/mips/mipsr6@24k-triple-stores-3.d
new file mode 100644
index 00000000000..7e5e4158e81
--- /dev/null
+++ b/gas/testsuite/gas/mips/mipsr6@24k-triple-stores-3.d
@@ -0,0 +1,57 @@
+#objdump: -dr
+#as: -mfix-24k -32
+#name: 24K: Triple Store (Double-word Check)
+#source: 24k-triple-stores-3.s
+
+.*: +file format .*mips.*
+
+Disassembly of section .text:
+
+0+ <.*>:
+   0:	a3a2000b 	sb	v0,11\(sp\)
+   4:	a3a3000b 	sb	v1,11\(sp\)
+   8:	a3a40004 	sb	a0,4\(sp\)
+   c:	0000000d 	break
+  10:	a3a20000 	sb	v0,0\(sp\)
+  14:	a3a3000b 	sb	v1,11\(sp\)
+  18:	a3a40005 	sb	a0,5\(sp\)
+  1c:	0000000d 	break
+  20:	a3a20007 	sb	v0,7\(sp\)
+  24:	a3a3000b 	sb	v1,11\(sp\)
+  28:	00000000 	nop
+  2c:	a3a40010 	sb	a0,16\(sp\)
+  30:	0000000d 	break
+  34:	a1020000 	sb	v0,0\(t0\)
+  38:	a1030008 	sb	v1,8\(t0\)
+  3c:	00000000 	nop
+  40:	a1040009 	sb	a0,9\(t0\)
+  44:	0000000d 	break
+  48:	a7a20000 	sh	v0,0\(sp\)
+  4c:	a7a3ffe1 	sh	v1,-31\(sp\)
+  50:	a7a4ffe2 	sh	a0,-30\(sp\)
+  54:	0000000d 	break
+  58:	a7a20006 	sh	v0,6\(sp\)
+  5c:	a7a30008 	sh	v1,8\(sp\)
+  60:	00000000 	nop
+  64:	a7a40010 	sh	a0,16\(sp\)
+  68:	0000000d 	break
+  6c:	a5020001 	sh	v0,1\(t0\)
+  70:	a5030003 	sh	v1,3\(t0\)
+  74:	00000000 	nop
+  78:	a504000b 	sh	a0,11\(t0\)
+  7c:	0000000d 	break
+  80:	afa20008 	sw	v0,8\(sp\)
+  84:	afa3fff8 	sw	v1,-8\(sp\)
+  88:	afa40008 	sw	a0,8\(sp\)
+  8c:	0000000d 	break
+  90:	afa20004 	sw	v0,4\(sp\)
+  94:	afa30008 	sw	v1,8\(sp\)
+  98:	00000000 	nop
+  9c:	afa40010 	sw	a0,16\(sp\)
+  a0:	0000000d 	break
+  a4:	ad020003 	sw	v0,3\(t0\)
+  a8:	ad030007 	sw	v1,7\(t0\)
+  ac:	00000000 	nop
+  b0:	ad04000f 	sw	a0,15\(t0\)
+  b4:	0000000d 	break
+	\.\.\.
diff --git a/gas/testsuite/gas/mips/mipsr6@24k-triple-stores-6.d b/gas/testsuite/gas/mips/mipsr6@24k-triple-stores-6.d
new file mode 100644
index 00000000000..271f9475758
--- /dev/null
+++ b/gas/testsuite/gas/mips/mipsr6@24k-triple-stores-6.d
@@ -0,0 +1,20 @@
+#objdump: -dr
+#as: -mfix-24k -32 -EB
+#name: 24K: Triple Store (Store Macro Check)
+#source: 24k-triple-stores-6.s
+
+.*: +file format .*mips.*
+
+Disassembly of section .text:
+0+ <.*>:
+   0:	e7a00050 	swc1	\$f0,80\(sp\)
+   4:	e7a20058 	swc1	\$f2,88\(sp\)
+   8:	00000000 	nop
+   c:	e7a40060 	swc1	\$f4,96\(sp\)
+  10:	0000000d 	break
+  14:	f7a00050 	sdc1	\$f0,80\(sp\)
+  18:	f7a20058 	sdc1	\$f2,88\(sp\)
+  1c:	00000000 	nop
+  20:	f7a40060 	sdc1	\$f4,96\(sp\)
+  24:	0000000d 	break
+	\.\.\.
diff --git a/gas/testsuite/gas/mips/mipsr6@add.d b/gas/testsuite/gas/mips/mipsr6@add.d
new file mode 100644
index 00000000000..65a5214459f
--- /dev/null
+++ b/gas/testsuite/gas/mips/mipsr6@add.d
@@ -0,0 +1,12 @@
+#objdump: -dr --prefix-addresses
+#name: MIPS add
+#source: add.s
+#as: -32
+
+# Test the add macro.
+
+.*: +file format .*mips.*
+
+Disassembly of section .text:
+0+0000 <[^>]*> addiu	a0,a0,1
+	\.\.\.
diff --git a/gas/testsuite/gas/mips/mipsr6@attr-gnu-4-1-msingle-float.l b/gas/testsuite/gas/mips/mipsr6@attr-gnu-4-1-msingle-float.l
new file mode 100644
index 00000000000..2f3b6f80efa
--- /dev/null
+++ b/gas/testsuite/gas/mips/mipsr6@attr-gnu-4-1-msingle-float.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Warning: .gnu_attribute 4,1 is incompatible with `singlefloat'
+.*: Warning: .gnu_attribute 4,1 is incompatible with `gp=32 fp=64'
diff --git a/gas/testsuite/gas/mips/mipsr6@attr-gnu-4-1-msingle-float.s b/gas/testsuite/gas/mips/mipsr6@attr-gnu-4-1-msingle-float.s
new file mode 100644
index 00000000000..e985a56f6b1
--- /dev/null
+++ b/gas/testsuite/gas/mips/mipsr6@attr-gnu-4-1-msingle-float.s
@@ -0,0 +1 @@
+.gnu_attribute 4,1
diff --git a/gas/testsuite/gas/mips/mipsr6@attr-gnu-4-1-msoft-float.l b/gas/testsuite/gas/mips/mipsr6@attr-gnu-4-1-msoft-float.l
new file mode 100644
index 00000000000..7e372d1a168
--- /dev/null
+++ b/gas/testsuite/gas/mips/mipsr6@attr-gnu-4-1-msoft-float.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Warning: .gnu_attribute 4,1 is incompatible with `softfloat'
+.*: Warning: .gnu_attribute 4,1 is incompatible with `gp=32 fp=64'
diff --git a/gas/testsuite/gas/mips/mipsr6@attr-gnu-4-1-msoft-float.s b/gas/testsuite/gas/mips/mipsr6@attr-gnu-4-1-msoft-float.s
new file mode 100644
index 00000000000..e985a56f6b1
--- /dev/null
+++ b/gas/testsuite/gas/mips/mipsr6@attr-gnu-4-1-msoft-float.s
@@ -0,0 +1 @@
+.gnu_attribute 4,1
diff --git a/gas/testsuite/gas/mips/mipsr6@attr-gnu-4-2-mdouble-float.l b/gas/testsuite/gas/mips/mipsr6@attr-gnu-4-2-mdouble-float.l
new file mode 100644
index 00000000000..b138323aeed
--- /dev/null
+++ b/gas/testsuite/gas/mips/mipsr6@attr-gnu-4-2-mdouble-float.l
@@ -0,0 +1,2 @@
+.*: Assembler messages:
+.*: Warning: .gnu_attribute 4,2 requires `singlefloat'
diff --git a/gas/testsuite/gas/mips/mipsr6@attr-gnu-4-2-mdouble-float.s b/gas/testsuite/gas/mips/mipsr6@attr-gnu-4-2-mdouble-float.s
new file mode 100644
index 00000000000..54ebf4ed8dd
--- /dev/null
+++ b/gas/testsuite/gas/mips/mipsr6@attr-gnu-4-2-mdouble-float.s
@@ -0,0 +1 @@
+.gnu_attribute 4,2
diff --git a/gas/testsuite/gas/mips/mipsr6@beq.d b/gas/testsuite/gas/mips/mipsr6@beq.d
new file mode 100644
index 00000000000..b5fec4c0c9d
--- /dev/null
+++ b/gas/testsuite/gas/mips/mipsr6@beq.d
@@ -0,0 +1,41 @@
+#objdump: -dr --prefix-addresses -mmips:4000
+#name: MIPS beq
+#as: -32
+#source: beq.s
+
+# Test the beq macro.
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> beq	a0,a1,0+0000 <.*>
+[	]*0: .*R_MIPS_PC16	text_label
+[0-9a-f]+ <[^>]*> nop
+[0-9a-f]+ <[^>]*> beqz	a0,0+0008 <.*>
+[	]*8: .*R_MIPS_PC16	text_label
+[0-9a-f]+ <[^>]*> nop
+[0-9a-f]+ <[^>]*> li	at,1
+[0-9a-f]+ <[^>]*> beq	a0,at,0+0014 <.*>
+[	]*14: .*R_MIPS_PC16	text_label
+[0-9a-f]+ <[^>]*> nop
+[0-9a-f]+ <[^>]*> li	at,0x8000
+[0-9a-f]+ <[^>]*> beq	a0,at,0+0020 <.*>
+[	]*20: .*R_MIPS_PC16	text_label
+[0-9a-f]+ <[^>]*> nop
+[0-9a-f]+ <[^>]*> li	at,-32768
+[0-9a-f]+ <[^>]*> beq	a0,at,0+002c <.*>
+[	]*2c: .*R_MIPS_PC16	text_label
+[0-9a-f]+ <[^>]*> nop
+[0-9a-f]+ <[^>]*> lui	at,0x1
+[0-9a-f]+ <[^>]*> beq	a0,at,0+0038 <.*>
+[	]*38: .*R_MIPS_PC16	text_label
+[0-9a-f]+ <[^>]*> nop
+[0-9a-f]+ <[^>]*> lui	at,0x1
+[0-9a-f]+ <[^>]*> ori	at,at,0xa5a5
+[0-9a-f]+ <[^>]*> beq	a0,at,0+0048 <.*>
+[	]*48: .*R_MIPS_PC16	text_label
+[0-9a-f]+ <[^>]*> nop
+[0-9a-f]+ <[^>]*> bnez	a0,0+0050 <.*>
+[	]*50: .*R_MIPS_PC16	text_label
+[0-9a-f]+ <[^>]*> nop
+	\.\.\.
diff --git a/gas/testsuite/gas/mips/mipsr6@bge.d b/gas/testsuite/gas/mips/mipsr6@bge.d
new file mode 100644
index 00000000000..050bc1b03e9
--- /dev/null
+++ b/gas/testsuite/gas/mips/mipsr6@bge.d
@@ -0,0 +1,72 @@
+#objdump: -dr --prefix-addresses -mmips:4000
+#name: MIPS bge
+#as: -32
+#source: bge.s
+
+# Test the bge macro.
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> slt	at,a0,a1
+[0-9a-f]+ <[^>]*> beqz	at,0+0004 <.*>
+[	]*4: .*R_MIPS_PC16	text_label
+[0-9a-f]+ <[^>]*> nop
+[0-9a-f]+ <[^>]*> bgez	a0,0+000c <.*>
+[	]*c: .*R_MIPS_PC16	text_label
+[0-9a-f]+ <[^>]*> nop
+[0-9a-f]+ <[^>]*> blez	a1,0+0014 <.*>
+[	]*14: .*R_MIPS_PC16	text_label
+[0-9a-f]+ <[^>]*> nop
+[0-9a-f]+ <[^>]*> bgez	a0,0+001c <.*>
+[	]*1c: .*R_MIPS_PC16	text_label
+[0-9a-f]+ <[^>]*> nop
+[0-9a-f]+ <[^>]*> bgtz	a0,0+0024 <.*>
+[	]*24: .*R_MIPS_PC16	text_label
+[0-9a-f]+ <[^>]*> nop
+[0-9a-f]+ <[^>]*> slti	at,a0,2
+[0-9a-f]+ <[^>]*> beqz	at,0+0030 <.*>
+[	]*30: .*R_MIPS_PC16	text_label
+[0-9a-f]+ <[^>]*> nop
+[0-9a-f]+ <[^>]*> li	at,0x8000
+[0-9a-f]+ <[^>]*> slt	at,a0,at
+[0-9a-f]+ <[^>]*> beqz	at,0+0040 <.*>
+[	]*40: .*R_MIPS_PC16	text_label
+[0-9a-f]+ <[^>]*> nop
+[0-9a-f]+ <[^>]*> slti	at,a0,-32768
+[0-9a-f]+ <[^>]*> beqz	at,0+004c <.*>
+[	]*4c: .*R_MIPS_PC16	text_label
+[0-9a-f]+ <[^>]*> nop
+[0-9a-f]+ <[^>]*> lui	at,0x1
+[0-9a-f]+ <[^>]*> slt	at,a0,at
+[0-9a-f]+ <[^>]*> beqz	at,0+005c <.*>
+[	]*5c: .*R_MIPS_PC16	text_label
+[0-9a-f]+ <[^>]*> nop
+[0-9a-f]+ <[^>]*> lui	at,0x1
+[0-9a-f]+ <[^>]*> ori	at,at,0xa5a5
+[0-9a-f]+ <[^>]*> slt	at,a0,at
+[0-9a-f]+ <[^>]*> beqz	at,0+0070 <.*>
+[	]*70: .*R_MIPS_PC16	text_label
+[0-9a-f]+ <[^>]*> nop
+[0-9a-f]+ <[^>]*> slt	at,a1,a0
+[0-9a-f]+ <[^>]*> bnez	at,0+007c <.*>
+[	]*7c: .*R_MIPS_PC16	text_label
+[0-9a-f]+ <[^>]*> nop
+[0-9a-f]+ <[^>]*> bgtz	a0,0+0084 <.*>
+[	]*84: .*R_MIPS_PC16	text_label
+[0-9a-f]+ <[^>]*> nop
+[0-9a-f]+ <[^>]*> bltz	a1,0+008c <.*>
+[	]*8c: .*R_MIPS_PC16	text_label
+[0-9a-f]+ <[^>]*> nop
+[0-9a-f]+ <[^>]*> bgtz	a0,0+0094 <.*>
+[	]*94: .*R_MIPS_PC16	text_label
+[0-9a-f]+ <[^>]*> nop
+[0-9a-f]+ <[^>]*> slt	at,a0,a1
+[0-9a-f]+ <[^>]*> beqz	at,0+00a0 <.*\+0xa0>
+[ 	]*a0: .*16	external_label
+[0-9a-f]+ <[^>]*> nop
+[0-9a-f]+ <[^>]*> slt	at,a1,a0
+[0-9a-f]+ <[^>]*> bnez	at,0+00ac <.*\+0xac>
+[ 	]*ac: .*16	external_label
+[0-9a-f]+ <[^>]*> nop
+	\.\.\.
diff --git a/gas/testsuite/gas/mips/mipsr6@bgeu.d b/gas/testsuite/gas/mips/mipsr6@bgeu.d
new file mode 100644
index 00000000000..38bdfb19e28
--- /dev/null
+++ b/gas/testsuite/gas/mips/mipsr6@bgeu.d
@@ -0,0 +1,63 @@
+#objdump: -dr --prefix-addresses -mmips:4000
+#name: MIPS bgeu
+#as: -32
+#source: bgeu.s
+
+# Test the bgeu macro.
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> sltu	at,a0,a1
+[0-9a-f]+ <[^>]*> beqz	at,0+0004 <.*>
+[	]*4: .*R_MIPS_PC16	text_label
+[0-9a-f]+ <[^>]*> nop
+[0-9a-f]+ <[^>]*> beq	zero,a1,0+000c <.*>
+[	]*c: .*R_MIPS_PC16	text_label
+[0-9a-f]+ <[^>]*> nop
+[0-9a-f]+ <[^>]*> bnez	a0,0+0014 <.*>
+[	]*14: .*R_MIPS_PC16	text_label
+[0-9a-f]+ <[^>]*> nop
+[0-9a-f]+ <[^>]*> sltiu	at,a0,2
+[0-9a-f]+ <[^>]*> beqz	at,0+0020 <.*>
+[	]*20: .*R_MIPS_PC16	text_label
+[0-9a-f]+ <[^>]*> nop
+[0-9a-f]+ <[^>]*> li	at,0x8000
+[0-9a-f]+ <[^>]*> sltu	at,a0,at
+[0-9a-f]+ <[^>]*> beqz	at,0+0030 <.*>
+[	]*30: .*R_MIPS_PC16	text_label
+[0-9a-f]+ <[^>]*> nop
+[0-9a-f]+ <[^>]*> sltiu	at,a0,-32768
+[0-9a-f]+ <[^>]*> beqz	at,0+003c <.*>
+[	]*3c: .*R_MIPS_PC16	text_label
+[0-9a-f]+ <[^>]*> nop
+[0-9a-f]+ <[^>]*> lui	at,0x1
+[0-9a-f]+ <[^>]*> sltu	at,a0,at
+[0-9a-f]+ <[^>]*> beqz	at,0+004c <.*>
+[	]*4c: .*R_MIPS_PC16	text_label
+[0-9a-f]+ <[^>]*> nop
+[0-9a-f]+ <[^>]*> lui	at,0x1
+[0-9a-f]+ <[^>]*> ori	at,at,0xa5a5
+[0-9a-f]+ <[^>]*> sltu	at,a0,at
+[0-9a-f]+ <[^>]*> beqz	at,0+0060 <.*>
+[	]*60: .*R_MIPS_PC16	text_label
+[0-9a-f]+ <[^>]*> nop
+[0-9a-f]+ <[^>]*> sltu	at,a1,a0
+[0-9a-f]+ <[^>]*> bnez	at,0+006c <.*>
+[	]*6c: .*R_MIPS_PC16	text_label
+[0-9a-f]+ <[^>]*> nop
+[0-9a-f]+ <[^>]*> bnez	a0,0+0074 <.*>
+[	]*74: .*R_MIPS_PC16	text_label
+[0-9a-f]+ <[^>]*> nop
+[0-9a-f]+ <[^>]*> bnez	a0,0+007c <.*>
+[	]*7c: .*R_MIPS_PC16	text_label
+[0-9a-f]+ <[^>]*> nop
+[0-9a-f]+ <[^>]*> sltu	at,a0,a1
+[0-9a-f]+ <[^>]*> beqz	at,0+0088 <.*\+0x88>
+[ 	]*88: .*16	external_label
+[0-9a-f]+ <[^>]*> nop
+[0-9a-f]+ <[^>]*> sltu	at,a1,a0
+[0-9a-f]+ <[^>]*> bnez	at,0+0094 <.*\+0x94>
+[ 	]*94: .*16	external_label
+[0-9a-f]+ <[^>]*> nop
+	\.\.\.
diff --git a/gas/testsuite/gas/mips/mipsr6@blt.d b/gas/testsuite/gas/mips/mipsr6@blt.d
new file mode 100644
index 00000000000..0f056f6ccad
--- /dev/null
+++ b/gas/testsuite/gas/mips/mipsr6@blt.d
@@ -0,0 +1,72 @@
+#objdump: -dr --prefix-addresses -mmips:4000
+#name: MIPS blt
+#as: -32
+#source: blt.s
+
+# Test the blt macro.
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> slt	at,a0,a1
+[0-9a-f]+ <[^>]*> bnez	at,0+0004 <.*>
+[	]*4: .*R_MIPS_PC16	text_label
+[0-9a-f]+ <[^>]*> nop
+[0-9a-f]+ <[^>]*> bltz	a0,0+000c <.*>
+[	]*c: .*R_MIPS_PC16	text_label
+[0-9a-f]+ <[^>]*> nop
+[0-9a-f]+ <[^>]*> bgtz	a1,0+0014 <.*>
+[	]*14: .*R_MIPS_PC16	text_label
+[0-9a-f]+ <[^>]*> nop
+[0-9a-f]+ <[^>]*> bltz	a0,0+001c <.*>
+[	]*1c: .*R_MIPS_PC16	text_label
+[0-9a-f]+ <[^>]*> nop
+[0-9a-f]+ <[^>]*> blez	a0,0+0024 <.*>
+[	]*24: .*R_MIPS_PC16	text_label
+[0-9a-f]+ <[^>]*> nop
+[0-9a-f]+ <[^>]*> slti	at,a0,2
+[0-9a-f]+ <[^>]*> bnez	at,0+0030 <.*>
+[	]*30: .*R_MIPS_PC16	text_label
+[0-9a-f]+ <[^>]*> nop
+[0-9a-f]+ <[^>]*> li	at,0x8000
+[0-9a-f]+ <[^>]*> slt	at,a0,at
+[0-9a-f]+ <[^>]*> bnez	at,0+0040 <.*>
+[	]*40: .*R_MIPS_PC16	text_label
+[0-9a-f]+ <[^>]*> nop
+[0-9a-f]+ <[^>]*> slti	at,a0,-32768
+[0-9a-f]+ <[^>]*> bnez	at,0+004c <.*>
+[	]*4c: .*R_MIPS_PC16	text_label
+[0-9a-f]+ <[^>]*> nop
+[0-9a-f]+ <[^>]*> lui	at,0x1
+[0-9a-f]+ <[^>]*> slt	at,a0,at
+[0-9a-f]+ <[^>]*> bnez	at,0+005c <.*>
+[	]*5c: .*R_MIPS_PC16	text_label
+[0-9a-f]+ <[^>]*> nop
+[0-9a-f]+ <[^>]*> lui	at,0x1
+[0-9a-f]+ <[^>]*> ori	at,at,0xa5a5
+[0-9a-f]+ <[^>]*> slt	at,a0,at
+[0-9a-f]+ <[^>]*> bnez	at,0+0070 <.*>
+[	]*70: .*R_MIPS_PC16	text_label
+[0-9a-f]+ <[^>]*> nop
+[0-9a-f]+ <[^>]*> slt	at,a1,a0
+[0-9a-f]+ <[^>]*> beqz	at,0+007c <.*>
+[	]*7c: .*R_MIPS_PC16	text_label
+[0-9a-f]+ <[^>]*> nop
+[0-9a-f]+ <[^>]*> blez	a0,0+0084 <.*>
+[	]*84: .*R_MIPS_PC16	text_label
+[0-9a-f]+ <[^>]*> nop
+[0-9a-f]+ <[^>]*> bgez	a1,0+008c <.*>
+[	]*8c: .*R_MIPS_PC16	text_label
+[0-9a-f]+ <[^>]*> nop
+[0-9a-f]+ <[^>]*> blez	a0,0+0094 <.*>
+[	]*94: .*R_MIPS_PC16	text_label
+[0-9a-f]+ <[^>]*> nop
+[0-9a-f]+ <[^>]*> slt	at,a0,a1
+[0-9a-f]+ <[^>]*> bnez	at,0+00a0 <.*\+0xa0>
+[ 	]*a0: .*16	external_label
+[0-9a-f]+ <[^>]*> nop
+[0-9a-f]+ <[^>]*> slt	at,a1,a0
+[0-9a-f]+ <[^>]*> beqz	at,0+00ac <.*\+0xac>
+[ 	]*ac: .*16	external_label
+[0-9a-f]+ <[^>]*> nop
+	\.\.\.
diff --git a/gas/testsuite/gas/mips/mipsr6@bltu.d b/gas/testsuite/gas/mips/mipsr6@bltu.d
new file mode 100644
index 00000000000..24ac4e2ee19
--- /dev/null
+++ b/gas/testsuite/gas/mips/mipsr6@bltu.d
@@ -0,0 +1,63 @@
+#objdump: -dr --prefix-addresses -mmips:4000
+#name: MIPS bltu
+#as: -32
+#source: bltu.s
+
+# Test the bltu macro.
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> sltu	at,a0,a1
+[0-9a-f]+ <[^>]*> bnez	at,0+0004 <.*>
+[	]*4: .*R_MIPS_PC16	text_label
+[0-9a-f]+ <[^>]*> nop
+[0-9a-f]+ <[^>]*> bne	zero,a1,0+000c <.*>
+[	]*c: .*R_MIPS_PC16	text_label
+[0-9a-f]+ <[^>]*> nop
+[0-9a-f]+ <[^>]*> beqz	a0,0+0014 <.*>
+[	]*14: .*R_MIPS_PC16	text_label
+[0-9a-f]+ <[^>]*> nop
+[0-9a-f]+ <[^>]*> sltiu	at,a0,2
+[0-9a-f]+ <[^>]*> bnez	at,0+0020 <.*>
+[	]*20: .*R_MIPS_PC16	text_label
+[0-9a-f]+ <[^>]*> nop
+[0-9a-f]+ <[^>]*> li	at,0x8000
+[0-9a-f]+ <[^>]*> sltu	at,a0,at
+[0-9a-f]+ <[^>]*> bnez	at,0+0030 <.*>
+[	]*30: .*R_MIPS_PC16	text_label
+[0-9a-f]+ <[^>]*> nop
+[0-9a-f]+ <[^>]*> sltiu	at,a0,-32768
+[0-9a-f]+ <[^>]*> bnez	at,0+003c <.*>
+[	]*3c: .*R_MIPS_PC16	text_label
+[0-9a-f]+ <[^>]*> nop
+[0-9a-f]+ <[^>]*> lui	at,0x1
+[0-9a-f]+ <[^>]*> sltu	at,a0,at
+[0-9a-f]+ <[^>]*> bnez	at,0+004c <.*>
+[	]*4c: .*R_MIPS_PC16	text_label
+[0-9a-f]+ <[^>]*> nop
+[0-9a-f]+ <[^>]*> lui	at,0x1
+[0-9a-f]+ <[^>]*> ori	at,at,0xa5a5
+[0-9a-f]+ <[^>]*> sltu	at,a0,at
+[0-9a-f]+ <[^>]*> bnez	at,0+0060 <.*>
+[	]*60: .*R_MIPS_PC16	text_label
+[0-9a-f]+ <[^>]*> nop
+[0-9a-f]+ <[^>]*> sltu	at,a1,a0
+[0-9a-f]+ <[^>]*> beqz	at,0+006c <.*>
+[	]*6c: .*R_MIPS_PC16	text_label
+[0-9a-f]+ <[^>]*> nop
+[0-9a-f]+ <[^>]*> beqz	a0,0+0074 <.*>
+[	]*74: .*R_MIPS_PC16	text_label
+[0-9a-f]+ <[^>]*> nop
+[0-9a-f]+ <[^>]*> beqz	a0,0+007c <.*>
+[	]*7c: .*R_MIPS_PC16	text_label
+[0-9a-f]+ <[^>]*> nop
+[0-9a-f]+ <[^>]*> sltu	at,a0,a1
+[0-9a-f]+ <[^>]*> bnez	at,0+0088 <.*\+0x88>
+[ 	]*88: .*16	external_label
+[0-9a-f]+ <[^>]*> nop
+[0-9a-f]+ <[^>]*> sltu	at,a1,a0
+[0-9a-f]+ <[^>]*> beqz	at,0+0094 <.*\+0x94>
+[ 	]*94: .*16	external_label
+[0-9a-f]+ <[^>]*> nop
+	\.\.\.
diff --git a/gas/testsuite/gas/mips/mipsr6@branch-misc-1.d b/gas/testsuite/gas/mips/mipsr6@branch-misc-1.d
new file mode 100644
index 00000000000..11f2b719486
--- /dev/null
+++ b/gas/testsuite/gas/mips/mipsr6@branch-misc-1.d
@@ -0,0 +1,35 @@
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS branch-misc-1
+#as: -32
+#source: branch-misc-1.s
+
+# Test the branches to local symbols in current file.
+
+.*: +file format .*mips.*
+
+Disassembly of section .text:
+	\.\.\.
+	\.\.\.
+	\.\.\.
+0+003c <[^>]*> 0411ffff 	bal	0000003c <[^>]*>
+[	]*3c: .*R_MIPS_PC16	l1
+0+0040 <[^>]*> 00000000 	nop
+0+0044 <[^>]*> 0411ffff 	bal	00000044 <[^>]*>
+[	]*44: .*R_MIPS_PC16	l2
+0+0048 <[^>]*> 00000000 	nop
+0+004c <[^>]*> 0411ffff 	bal	0000004c <[^>]*>
+[	]*4c: .*R_MIPS_PC16	l3
+0+0050 <[^>]*> 00000000 	nop
+0+0054 <[^>]*> 0411ffff 	bal	00000054 <[^>]*>
+[	]*54: .*R_MIPS_PC16	l4
+0+0058 <[^>]*> 00000000 	nop
+0+005c <[^>]*> 0411ffff 	bal	0000005c <[^>]*>
+[	]*5c: .*R_MIPS_PC16	l5
+0+0060 <[^>]*> 00000000 	nop
+0+0064 <[^>]*> 0411ffff 	bal	00000064 <[^>]*>
+[	]*64: .*R_MIPS_PC16	l6
+0+0068 <[^>]*> 00000000 	nop
+	\.\.\.
+	\.\.\.
+	\.\.\.
+	\.\.\.
diff --git a/gas/testsuite/gas/mips/mipsr6@branch-misc-2-64.d b/gas/testsuite/gas/mips/mipsr6@branch-misc-2-64.d
new file mode 100644
index 00000000000..44ffa7ca696
--- /dev/null
+++ b/gas/testsuite/gas/mips/mipsr6@branch-misc-2-64.d
@@ -0,0 +1,62 @@
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS branch-misc-2-64
+#source: branch-misc-2.s
+#as: -64 -non_shared
+
+# Test the backward branches to globals symbols in current file.
+
+.*: +file format .*mips.*
+
+Disassembly of section .text:
+	\.\.\.
+	\.\.\.
+	\.\.\.
+0+003c <[^>]*> 04110000 	bal	0000000000000040 <x\+0x4>
+[ 	]*3c: R_MIPS_PC16	g1-0x4
+[ 	]*3c: R_MIPS_NONE	\*ABS\*-0x4
+[ 	]*3c: R_MIPS_NONE	\*ABS\*-0x4
+0+0040 <[^>]*> 00000000 	nop
+0+0044 <[^>]*> 04110000 	bal	0000000000000048 <x\+0xc>
+[ 	]*44: R_MIPS_PC16	g2-0x4
+[ 	]*44: R_MIPS_NONE	\*ABS\*-0x4
+[ 	]*44: R_MIPS_NONE	\*ABS\*-0x4
+0+0048 <[^>]*> 00000000 	nop
+0+004c <[^>]*> 04110000 	bal	0000000000000050 <x\+0x14>
+[ 	]*4c: R_MIPS_PC16	g3-0x4
+[ 	]*4c: R_MIPS_NONE	\*ABS\*-0x4
+[ 	]*4c: R_MIPS_NONE	\*ABS\*-0x4
+0+0050 <[^>]*> 00000000 	nop
+0+0054 <[^>]*> 04110000 	bal	0000000000000058 <x\+0x1c>
+[ 	]*54: R_MIPS_PC16	g4-0x4
+[ 	]*54: R_MIPS_NONE	\*ABS\*-0x4
+[ 	]*54: R_MIPS_NONE	\*ABS\*-0x4
+0+0058 <[^>]*> 00000000 	nop
+0+005c <[^>]*> 04110000 	bal	0000000000000060 <x\+0x24>
+[ 	]*5c: R_MIPS_PC16	g5-0x4
+[ 	]*5c: R_MIPS_NONE	\*ABS\*-0x4
+[ 	]*5c: R_MIPS_NONE	\*ABS\*-0x4
+0+0060 <[^>]*> 00000000 	nop
+0+0064 <[^>]*> 04110000 	bal	0000000000000068 <x\+0x2c>
+[ 	]*64: R_MIPS_PC16	g6-0x4
+[ 	]*64: R_MIPS_NONE	\*ABS\*-0x4
+[ 	]*64: R_MIPS_NONE	\*ABS\*-0x4
+0+0068 <[^>]*> 00000000 	nop
+	\.\.\.
+	\.\.\.
+	\.\.\.
+0+00a8 <[^>]*> 10000000 	b	00000000000000ac <g6\+0x4>
+[ 	]*a8: R_MIPS_PC16	x1-0x4
+[ 	]*a8: R_MIPS_NONE	\*ABS\*-0x4
+[ 	]*a8: R_MIPS_NONE	\*ABS\*-0x4
+0+00ac <[^>]*> 00000000 	nop
+0+00b0 <[^>]*> 10000000 	b	00000000000000b4 <g6\+0xc>
+[ 	]*b0: R_MIPS_PC16	x2-0x4
+[ 	]*b0: R_MIPS_NONE	\*ABS\*-0x4
+[ 	]*b0: R_MIPS_NONE	\*ABS\*-0x4
+0+00b4 <[^>]*> 00000000 	nop
+0+00b8 <[^>]*> 10000000 	b	00000000000000bc <g6\+0x14>
+[ 	]*b8: R_MIPS_PC16	\.Ldata-0x4
+[ 	]*b8: R_MIPS_NONE	\*ABS\*-0x4
+[ 	]*b8: R_MIPS_NONE	\*ABS\*-0x4
+0+00bc <[^>]*> 00000000 	nop
+	\.\.\.
diff --git a/gas/testsuite/gas/mips/mipsr6@branch-misc-2pic-64.d b/gas/testsuite/gas/mips/mipsr6@branch-misc-2pic-64.d
new file mode 100644
index 00000000000..5ff980e776f
--- /dev/null
+++ b/gas/testsuite/gas/mips/mipsr6@branch-misc-2pic-64.d
@@ -0,0 +1,62 @@
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS branch-misc-2pic-64
+#source: branch-misc-2.s
+#as: -64 -call_shared
+
+# Test the backward branches to globals symbols in current file.
+
+.*: +file format .*mips.*
+
+Disassembly of section .text:
+	\.\.\.
+	\.\.\.
+	\.\.\.
+0+003c <[^>]*> 04110000 	bal	0000000000000040 <x\+0x4>
+[ 	]*3c: R_MIPS_PC16	g1-0x4
+[ 	]*3c: R_MIPS_NONE	\*ABS\*-0x4
+[ 	]*3c: R_MIPS_NONE	\*ABS\*-0x4
+0+0040 <[^>]*> 00000000 	nop
+0+0044 <[^>]*> 04110000 	bal	0000000000000048 <x\+0xc>
+[ 	]*44: R_MIPS_PC16	g2-0x4
+[ 	]*44: R_MIPS_NONE	\*ABS\*-0x4
+[ 	]*44: R_MIPS_NONE	\*ABS\*-0x4
+0+0048 <[^>]*> 00000000 	nop
+0+004c <[^>]*> 04110000 	bal	0000000000000050 <x\+0x14>
+[ 	]*4c: R_MIPS_PC16	g3-0x4
+[ 	]*4c: R_MIPS_NONE	\*ABS\*-0x4
+[ 	]*4c: R_MIPS_NONE	\*ABS\*-0x4
+0+0050 <[^>]*> 00000000 	nop
+0+0054 <[^>]*> 04110000 	bal	0000000000000058 <x\+0x1c>
+[ 	]*54: R_MIPS_PC16	g4-0x4
+[ 	]*54: R_MIPS_NONE	\*ABS\*-0x4
+[ 	]*54: R_MIPS_NONE	\*ABS\*-0x4
+0+0058 <[^>]*> 00000000 	nop
+0+005c <[^>]*> 04110000 	bal	0000000000000060 <x\+0x24>
+[ 	]*5c: R_MIPS_PC16	g5-0x4
+[ 	]*5c: R_MIPS_NONE	\*ABS\*-0x4
+[ 	]*5c: R_MIPS_NONE	\*ABS\*-0x4
+0+0060 <[^>]*> 00000000 	nop
+0+0064 <[^>]*> 04110000 	bal	0000000000000068 <x\+0x2c>
+[ 	]*64: R_MIPS_PC16	g6-0x4
+[ 	]*64: R_MIPS_NONE	\*ABS\*-0x4
+[ 	]*64: R_MIPS_NONE	\*ABS\*-0x4
+0+0068 <[^>]*> 00000000 	nop
+	\.\.\.
+	\.\.\.
+	\.\.\.
+0+00a8 <[^>]*> 10000000 	b	00000000000000ac <g6\+0x4>
+[ 	]*a8: R_MIPS_PC16	x1-0x4
+[ 	]*a8: R_MIPS_NONE	\*ABS\*-0x4
+[ 	]*a8: R_MIPS_NONE	\*ABS\*-0x4
+0+00ac <[^>]*> 00000000 	nop
+0+00b0 <[^>]*> 10000000 	b	00000000000000b4 <g6\+0xc>
+[ 	]*b0: R_MIPS_PC16	x2-0x4
+[ 	]*b0: R_MIPS_NONE	\*ABS\*-0x4
+[ 	]*b0: R_MIPS_NONE	\*ABS\*-0x4
+0+00b4 <[^>]*> 00000000 	nop
+0+00b8 <[^>]*> 10000000 	b	00000000000000bc <g6\+0x14>
+[ 	]*b8: R_MIPS_PC16	\.Ldata-0x4
+[ 	]*b8: R_MIPS_NONE	\*ABS\*-0x4
+[ 	]*b8: R_MIPS_NONE	\*ABS\*-0x4
+0+00bc <[^>]*> 00000000 	nop
+	\.\.\.
diff --git a/gas/testsuite/gas/mips/mipsr6@branch-misc-4-64.d b/gas/testsuite/gas/mips/mipsr6@branch-misc-4-64.d
new file mode 100644
index 00000000000..e3cd75cab6f
--- /dev/null
+++ b/gas/testsuite/gas/mips/mipsr6@branch-misc-4-64.d
@@ -0,0 +1,35 @@
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS branch-misc-4-64
+#as: -64
+#source: branch-misc-4.s
+
+# Verify PC-relative relocations do not overflow.
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+	\.\.\.
+[0-9a-f]+ <[^>]*> 10000000 	b	[0-9a-f]+ <foo\+0x[0-9a-f]+>
+[ 	]*[0-9a-f]+: R_MIPS_PC16	bar\-0x4
+[ 	]*[0-9a-f]+: R_MIPS_NONE	\*ABS\*\-0x4
+[ 	]*[0-9a-f]+: R_MIPS_NONE	\*ABS\*\-0x4
+[0-9a-f]+ <[^>]*> 00000000 	nop
+[0-9a-f]+ <[^>]*> 10000000 	b	[0-9a-f]+ <\.Lfoo\+0x[0-9a-f]+>
+[ 	]*[0-9a-f]+: R_MIPS_PC16	\.Lbar-0x4
+[ 	]*[0-9a-f]+: R_MIPS_NONE	\*ABS\*-0x4
+[ 	]*[0-9a-f]+: R_MIPS_NONE	\*ABS\*-0x4
+[0-9a-f]+ <[^>]*> 00000000 	nop
+	\.\.\.
+
+Disassembly of section \.init:
+[0-9a-f]+ <[^>]*> 10000000 	b	[0-9a-f]+ <bar\+0x[0-9a-f]+>
+[ 	]*[0-9a-f]+: R_MIPS_PC16	foo\-0x4
+[ 	]*[0-9a-f]+: R_MIPS_NONE	\*ABS\*\-0x4
+[ 	]*[0-9a-f]+: R_MIPS_NONE	\*ABS\*\-0x4
+[0-9a-f]+ <[^>]*> 00000000 	nop
+[0-9a-f]+ <[^>]*> 10000000 	b	[0-9a-f]+ <\.Lbar\+0x[0-9a-f]+>
+[ 	]*[0-9a-f]+: R_MIPS_PC16	\.Lfoo-0x4
+[ 	]*[0-9a-f]+: R_MIPS_NONE	\*ABS\*-0x4
+[ 	]*[0-9a-f]+: R_MIPS_NONE	\*ABS\*-0x4
+[0-9a-f]+ <[^>]*> 00000000 	nop
+	\.\.\.
diff --git a/gas/testsuite/gas/mips/mipsr6@cache.d b/gas/testsuite/gas/mips/mipsr6@cache.d
new file mode 100644
index 00000000000..803f5de05f0
--- /dev/null
+++ b/gas/testsuite/gas/mips/mipsr6@cache.d
@@ -0,0 +1,13 @@
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS CACHE instruction
+#source: cache.s
+#as: -32
+
+# Check MIPS CACHE instruction assembly.
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 7c457fa5 	cache	0x5,255\(v0\)
+[0-9a-f]+ <[^>]*> 7c658025 	cache	0x5,-256\(v1\)
+	\.\.\.
diff --git a/gas/testsuite/gas/mips/mipsr6@eva.d b/gas/testsuite/gas/mips/mipsr6@eva.d
new file mode 100644
index 00000000000..79b60300fff
--- /dev/null
+++ b/gas/testsuite/gas/mips/mipsr6@eva.d
@@ -0,0 +1,952 @@
+#objdump: -dr -Mgpr-names=numeric --show-raw-insn
+#name: MIPS EVA
+#source: eva.s
+#as: -meva -32
+
+# Test the EVA instructions
+
+.*: +file format .*mips.*
+
+
+Disassembly of section \.text:
+
+[ 0-9a-f]+ <test_eva>:
+[ 0-9a-f]+:	7c408028 	lbue	\$0,-256\(\$2\)
+[ 0-9a-f]+:	7c038028 	lbue	\$3,-256\(\$0\)
+[ 0-9a-f]+:	7ca47fa8 	lbue	\$4,255\(\$5\)
+[ 0-9a-f]+:	7c067fa8 	lbue	\$6,255\(\$0\)
+[ 0-9a-f]+:	2501feff 	addiu	\$1,\$8,-257
+[ 0-9a-f]+:	7c270028 	lbue	\$7,0\(\$1\)
+[ 0-9a-f]+:	2401feff 	li	\$1,-257
+[ 0-9a-f]+:	7c290028 	lbue	\$9,0\(\$1\)
+[ 0-9a-f]+:	25610100 	addiu	\$1,\$11,256
+[ 0-9a-f]+:	7c2a0028 	lbue	\$10,0\(\$1\)
+[ 0-9a-f]+:	24010100 	li	\$1,256
+[ 0-9a-f]+:	7c2c0028 	lbue	\$12,0\(\$1\)
+[ 0-9a-f]+:	25c1fe00 	addiu	\$1,\$14,-512
+[ 0-9a-f]+:	7c2d0028 	lbue	\$13,0\(\$1\)
+[ 0-9a-f]+:	2401fe00 	li	\$1,-512
+[ 0-9a-f]+:	7c2f0028 	lbue	\$15,0\(\$1\)
+[ 0-9a-f]+:	262101ff 	addiu	\$1,\$17,511
+[ 0-9a-f]+:	7c300028 	lbue	\$16,0\(\$1\)
+[ 0-9a-f]+:	240101ff 	li	\$1,511
+[ 0-9a-f]+:	7c320028 	lbue	\$18,0\(\$1\)
+[ 0-9a-f]+:	2681fc00 	addiu	\$1,\$20,-1024
+[ 0-9a-f]+:	7c330028 	lbue	\$19,0\(\$1\)
+[ 0-9a-f]+:	2401fc00 	li	\$1,-1024
+[ 0-9a-f]+:	7c350028 	lbue	\$21,0\(\$1\)
+[ 0-9a-f]+:	26e103ff 	addiu	\$1,\$23,1023
+[ 0-9a-f]+:	7c360028 	lbue	\$22,0\(\$1\)
+[ 0-9a-f]+:	240103ff 	li	\$1,1023
+[ 0-9a-f]+:	7c380028 	lbue	\$24,0\(\$1\)
+[ 0-9a-f]+:	2741f800 	addiu	\$1,\$26,-2048
+[ 0-9a-f]+:	7c390028 	lbue	\$25,0\(\$1\)
+[ 0-9a-f]+:	2401f800 	li	\$1,-2048
+[ 0-9a-f]+:	7c3b0028 	lbue	\$27,0\(\$1\)
+[ 0-9a-f]+:	27a107ff 	addiu	\$1,\$29,2047
+[ 0-9a-f]+:	7c3c0028 	lbue	\$28,0\(\$1\)
+[ 0-9a-f]+:	240107ff 	li	\$1,2047
+[ 0-9a-f]+:	7c3e0028 	lbue	\$30,0\(\$1\)
+[ 0-9a-f]+:	2401f000 	li	\$1,-4096
+[ 0-9a-f]+:	7c3f0028 	lbue	\$31,0\(\$1\)
+[ 0-9a-f]+:	2401f000 	li	\$1,-4096
+[ 0-9a-f]+:	7c220028 	lbue	\$2,0\(\$1\)
+[ 0-9a-f]+:	24810fff 	addiu	\$1,\$4,4095
+[ 0-9a-f]+:	7c230028 	lbue	\$3,0\(\$1\)
+[ 0-9a-f]+:	24010fff 	li	\$1,4095
+[ 0-9a-f]+:	7c250028 	lbue	\$5,0\(\$1\)
+[ 0-9a-f]+:	24e18000 	addiu	\$1,\$7,-32768
+[ 0-9a-f]+:	7c260028 	lbue	\$6,0\(\$1\)
+[ 0-9a-f]+:	24018000 	li	\$1,-32768
+[ 0-9a-f]+:	7c280028 	lbue	\$8,0\(\$1\)
+[ 0-9a-f]+:	25417fff 	addiu	\$1,\$10,32767
+[ 0-9a-f]+:	7c290028 	lbue	\$9,0\(\$1\)
+[ 0-9a-f]+:	24017fff 	li	\$1,32767
+[ 0-9a-f]+:	7c2b0028 	lbue	\$11,0\(\$1\)
+[ 0-9a-f]+:	24018000 	li	\$1,-32768
+[ 0-9a-f]+:	002d0821 	addu	\$1,\$1,\$13
+[ 0-9a-f]+:	7c2cffa8 	lbue	\$12,-1\(\$1\)
+[ 0-9a-f]+:	24018000 	li	\$1,-32768
+[ 0-9a-f]+:	7c2effa8 	lbue	\$14,-1\(\$1\)
+[ 0-9a-f]+:	34018000 	li	\$1,0x8000
+[ 0-9a-f]+:	00300821 	addu	\$1,\$1,\$16
+[ 0-9a-f]+:	7c2f0028 	lbue	\$15,0\(\$1\)
+[ 0-9a-f]+:	34018000 	li	\$1,0x8000
+[ 0-9a-f]+:	7c310028 	lbue	\$17,0\(\$1\)
+[ 0-9a-f]+:	3c018000 	lui	\$1,0x8000
+[ 0-9a-f]+:	00330821 	addu	\$1,\$1,\$19
+[ 0-9a-f]+:	7c320028 	lbue	\$18,0\(\$1\)
+[ 0-9a-f]+:	3c018000 	lui	\$1,0x8000
+[ 0-9a-f]+:	7c340028 	lbue	\$20,0\(\$1\)
+[ 0-9a-f]+:	3c018000 	lui	\$1,0x8000
+[ 0-9a-f]+:	00360821 	addu	\$1,\$1,\$22
+[ 0-9a-f]+:	7c35ffa8 	lbue	\$21,-1\(\$1\)
+[ 0-9a-f]+:	3c018000 	lui	\$1,0x8000
+[ 0-9a-f]+:	7c37ffa8 	lbue	\$23,-1\(\$1\)
+[ 0-9a-f]+:	7f380028 	lbue	\$24,0\(\$25\)
+[ 0-9a-f]+:	3c010000 	lui	\$1,0x0
+			[ 0-9a-f]+: R_MIPS_HI16	MYDATA
+[ 0-9a-f]+:	24210000 	addiu	\$1,\$1,0
+			[ 0-9a-f]+: R_MIPS_LO16	MYDATA
+[ 0-9a-f]+:	7c3a0028 	lbue	\$26,0\(\$1\)
+[ 0-9a-f]+:	7f9b8029 	lhue	\$27,-256\(\$28\)
+[ 0-9a-f]+:	7c1d8029 	lhue	\$29,-256\(\$0\)
+[ 0-9a-f]+:	7ffe7fa9 	lhue	\$30,255\(\$31\)
+[ 0-9a-f]+:	7c007fa9 	lhue	\$0,255\(\$0\)
+[ 0-9a-f]+:	2461feff 	addiu	\$1,\$3,-257
+[ 0-9a-f]+:	7c220029 	lhue	\$2,0\(\$1\)
+[ 0-9a-f]+:	2401feff 	li	\$1,-257
+[ 0-9a-f]+:	7c240029 	lhue	\$4,0\(\$1\)
+[ 0-9a-f]+:	24c10100 	addiu	\$1,\$6,256
+[ 0-9a-f]+:	7c250029 	lhue	\$5,0\(\$1\)
+[ 0-9a-f]+:	24010100 	li	\$1,256
+[ 0-9a-f]+:	7c270029 	lhue	\$7,0\(\$1\)
+[ 0-9a-f]+:	2521fe00 	addiu	\$1,\$9,-512
+[ 0-9a-f]+:	7c280029 	lhue	\$8,0\(\$1\)
+[ 0-9a-f]+:	2401fe00 	li	\$1,-512
+[ 0-9a-f]+:	7c2a0029 	lhue	\$10,0\(\$1\)
+[ 0-9a-f]+:	258101ff 	addiu	\$1,\$12,511
+[ 0-9a-f]+:	7c2b0029 	lhue	\$11,0\(\$1\)
+[ 0-9a-f]+:	240101ff 	li	\$1,511
+[ 0-9a-f]+:	7c2d0029 	lhue	\$13,0\(\$1\)
+[ 0-9a-f]+:	25e1fc00 	addiu	\$1,\$15,-1024
+[ 0-9a-f]+:	7c2e0029 	lhue	\$14,0\(\$1\)
+[ 0-9a-f]+:	2401fc00 	li	\$1,-1024
+[ 0-9a-f]+:	7c300029 	lhue	\$16,0\(\$1\)
+[ 0-9a-f]+:	264103ff 	addiu	\$1,\$18,1023
+[ 0-9a-f]+:	7c310029 	lhue	\$17,0\(\$1\)
+[ 0-9a-f]+:	240103ff 	li	\$1,1023
+[ 0-9a-f]+:	7c330029 	lhue	\$19,0\(\$1\)
+[ 0-9a-f]+:	26a1f800 	addiu	\$1,\$21,-2048
+[ 0-9a-f]+:	7c340029 	lhue	\$20,0\(\$1\)
+[ 0-9a-f]+:	2401f800 	li	\$1,-2048
+[ 0-9a-f]+:	7c360029 	lhue	\$22,0\(\$1\)
+[ 0-9a-f]+:	270107ff 	addiu	\$1,\$24,2047
+[ 0-9a-f]+:	7c370029 	lhue	\$23,0\(\$1\)
+[ 0-9a-f]+:	240107ff 	li	\$1,2047
+[ 0-9a-f]+:	7c390029 	lhue	\$25,0\(\$1\)
+[ 0-9a-f]+:	2761f000 	addiu	\$1,\$27,-4096
+[ 0-9a-f]+:	7c3a0029 	lhue	\$26,0\(\$1\)
+[ 0-9a-f]+:	2401f000 	li	\$1,-4096
+[ 0-9a-f]+:	7c3c0029 	lhue	\$28,0\(\$1\)
+[ 0-9a-f]+:	27c10fff 	addiu	\$1,\$30,4095
+[ 0-9a-f]+:	7c3d0029 	lhue	\$29,0\(\$1\)
+[ 0-9a-f]+:	24010fff 	li	\$1,4095
+[ 0-9a-f]+:	7c3f0029 	lhue	\$31,0\(\$1\)
+[ 0-9a-f]+:	24418000 	addiu	\$1,\$2,-32768
+[ 0-9a-f]+:	7c200029 	lhue	\$0,0\(\$1\)
+[ 0-9a-f]+:	24018000 	li	\$1,-32768
+[ 0-9a-f]+:	7c230029 	lhue	\$3,0\(\$1\)
+[ 0-9a-f]+:	24a17fff 	addiu	\$1,\$5,32767
+[ 0-9a-f]+:	7c240029 	lhue	\$4,0\(\$1\)
+[ 0-9a-f]+:	24017fff 	li	\$1,32767
+[ 0-9a-f]+:	7c260029 	lhue	\$6,0\(\$1\)
+[ 0-9a-f]+:	24018000 	li	\$1,-32768
+[ 0-9a-f]+:	00280821 	addu	\$1,\$1,\$8
+[ 0-9a-f]+:	7c27ffa9 	lhue	\$7,-1\(\$1\)
+[ 0-9a-f]+:	24018000 	li	\$1,-32768
+[ 0-9a-f]+:	7c29ffa9 	lhue	\$9,-1\(\$1\)
+[ 0-9a-f]+:	34018000 	li	\$1,0x8000
+[ 0-9a-f]+:	002b0821 	addu	\$1,\$1,\$11
+[ 0-9a-f]+:	7c2a0029 	lhue	\$10,0\(\$1\)
+[ 0-9a-f]+:	34018000 	li	\$1,0x8000
+[ 0-9a-f]+:	7c2c0029 	lhue	\$12,0\(\$1\)
+[ 0-9a-f]+:	3c018000 	lui	\$1,0x8000
+[ 0-9a-f]+:	002e0821 	addu	\$1,\$1,\$14
+[ 0-9a-f]+:	7c2d0029 	lhue	\$13,0\(\$1\)
+[ 0-9a-f]+:	3c018000 	lui	\$1,0x8000
+[ 0-9a-f]+:	7c2f0029 	lhue	\$15,0\(\$1\)
+[ 0-9a-f]+:	3c018000 	lui	\$1,0x8000
+[ 0-9a-f]+:	00310821 	addu	\$1,\$1,\$17
+[ 0-9a-f]+:	7c30ffa9 	lhue	\$16,-1\(\$1\)
+[ 0-9a-f]+:	3c018000 	lui	\$1,0x8000
+[ 0-9a-f]+:	7c32ffa9 	lhue	\$18,-1\(\$1\)
+[ 0-9a-f]+:	7e930029 	lhue	\$19,0\(\$20\)
+[ 0-9a-f]+:	3c010000 	lui	\$1,0x0
+			[ 0-9a-f]+: R_MIPS_HI16	MYDATA
+[ 0-9a-f]+:	24210000 	addiu	\$1,\$1,0
+			[ 0-9a-f]+: R_MIPS_LO16	MYDATA
+[ 0-9a-f]+:	7c350029 	lhue	\$21,0\(\$1\)
+[ 0-9a-f]+:	7ef6802c 	lbe	\$22,-256\(\$23\)
+[ 0-9a-f]+:	7c18802c 	lbe	\$24,-256\(\$0\)
+[ 0-9a-f]+:	7f597fac 	lbe	\$25,255\(\$26\)
+[ 0-9a-f]+:	7c1b7fac 	lbe	\$27,255\(\$0\)
+[ 0-9a-f]+:	27a1feff 	addiu	\$1,\$29,-257
+[ 0-9a-f]+:	7c3c002c 	lbe	\$28,0\(\$1\)
+[ 0-9a-f]+:	2401feff 	li	\$1,-257
+[ 0-9a-f]+:	7c3e002c 	lbe	\$30,0\(\$1\)
+[ 0-9a-f]+:	24010100 	li	\$1,256
+[ 0-9a-f]+:	7c3f002c 	lbe	\$31,0\(\$1\)
+[ 0-9a-f]+:	24010100 	li	\$1,256
+[ 0-9a-f]+:	7c22002c 	lbe	\$2,0\(\$1\)
+[ 0-9a-f]+:	2481fe00 	addiu	\$1,\$4,-512
+[ 0-9a-f]+:	7c23002c 	lbe	\$3,0\(\$1\)
+[ 0-9a-f]+:	2401fe00 	li	\$1,-512
+[ 0-9a-f]+:	7c25002c 	lbe	\$5,0\(\$1\)
+[ 0-9a-f]+:	24e101ff 	addiu	\$1,\$7,511
+[ 0-9a-f]+:	7c26002c 	lbe	\$6,0\(\$1\)
+[ 0-9a-f]+:	240101ff 	li	\$1,511
+[ 0-9a-f]+:	7c28002c 	lbe	\$8,0\(\$1\)
+[ 0-9a-f]+:	2541fc00 	addiu	\$1,\$10,-1024
+[ 0-9a-f]+:	7c29002c 	lbe	\$9,0\(\$1\)
+[ 0-9a-f]+:	2401fc00 	li	\$1,-1024
+[ 0-9a-f]+:	7c2b002c 	lbe	\$11,0\(\$1\)
+[ 0-9a-f]+:	25a103ff 	addiu	\$1,\$13,1023
+[ 0-9a-f]+:	7c2c002c 	lbe	\$12,0\(\$1\)
+[ 0-9a-f]+:	240103ff 	li	\$1,1023
+[ 0-9a-f]+:	7c2e002c 	lbe	\$14,0\(\$1\)
+[ 0-9a-f]+:	2601f800 	addiu	\$1,\$16,-2048
+[ 0-9a-f]+:	7c2f002c 	lbe	\$15,0\(\$1\)
+[ 0-9a-f]+:	2401f800 	li	\$1,-2048
+[ 0-9a-f]+:	7c31002c 	lbe	\$17,0\(\$1\)
+[ 0-9a-f]+:	266107ff 	addiu	\$1,\$19,2047
+[ 0-9a-f]+:	7c32002c 	lbe	\$18,0\(\$1\)
+[ 0-9a-f]+:	240107ff 	li	\$1,2047
+[ 0-9a-f]+:	7c34002c 	lbe	\$20,0\(\$1\)
+[ 0-9a-f]+:	26c1f000 	addiu	\$1,\$22,-4096
+[ 0-9a-f]+:	7c35002c 	lbe	\$21,0\(\$1\)
+[ 0-9a-f]+:	2401f000 	li	\$1,-4096
+[ 0-9a-f]+:	7c37002c 	lbe	\$23,0\(\$1\)
+[ 0-9a-f]+:	27210fff 	addiu	\$1,\$25,4095
+[ 0-9a-f]+:	7c38002c 	lbe	\$24,0\(\$1\)
+[ 0-9a-f]+:	24010fff 	li	\$1,4095
+[ 0-9a-f]+:	7c3a002c 	lbe	\$26,0\(\$1\)
+[ 0-9a-f]+:	27818000 	addiu	\$1,\$28,-32768
+[ 0-9a-f]+:	7c3b002c 	lbe	\$27,0\(\$1\)
+[ 0-9a-f]+:	24018000 	li	\$1,-32768
+[ 0-9a-f]+:	7c3d002c 	lbe	\$29,0\(\$1\)
+[ 0-9a-f]+:	27e17fff 	addiu	\$1,\$31,32767
+[ 0-9a-f]+:	7c3e002c 	lbe	\$30,0\(\$1\)
+[ 0-9a-f]+:	24017fff 	li	\$1,32767
+[ 0-9a-f]+:	7c20002c 	lbe	\$0,0\(\$1\)
+[ 0-9a-f]+:	24018000 	li	\$1,-32768
+[ 0-9a-f]+:	00230821 	addu	\$1,\$1,\$3
+[ 0-9a-f]+:	7c22ffac 	lbe	\$2,-1\(\$1\)
+[ 0-9a-f]+:	24018000 	li	\$1,-32768
+[ 0-9a-f]+:	7c24ffac 	lbe	\$4,-1\(\$1\)
+[ 0-9a-f]+:	34018000 	li	\$1,0x8000
+[ 0-9a-f]+:	00260821 	addu	\$1,\$1,\$6
+[ 0-9a-f]+:	7c25002c 	lbe	\$5,0\(\$1\)
+[ 0-9a-f]+:	34018000 	li	\$1,0x8000
+[ 0-9a-f]+:	7c27002c 	lbe	\$7,0\(\$1\)
+[ 0-9a-f]+:	3c018000 	lui	\$1,0x8000
+[ 0-9a-f]+:	00290821 	addu	\$1,\$1,\$9
+[ 0-9a-f]+:	7c28002c 	lbe	\$8,0\(\$1\)
+[ 0-9a-f]+:	3c018000 	lui	\$1,0x8000
+[ 0-9a-f]+:	7c2a002c 	lbe	\$10,0\(\$1\)
+[ 0-9a-f]+:	3c018000 	lui	\$1,0x8000
+[ 0-9a-f]+:	002c0821 	addu	\$1,\$1,\$12
+[ 0-9a-f]+:	7c2bffac 	lbe	\$11,-1\(\$1\)
+[ 0-9a-f]+:	3c018000 	lui	\$1,0x8000
+[ 0-9a-f]+:	7c2dffac 	lbe	\$13,-1\(\$1\)
+[ 0-9a-f]+:	7dee002c 	lbe	\$14,0\(\$15\)
+[ 0-9a-f]+:	3c010000 	lui	\$1,0x0
+			[ 0-9a-f]+: R_MIPS_HI16	MYDATA
+[ 0-9a-f]+:	24210000 	addiu	\$1,\$1,0
+			[ 0-9a-f]+: R_MIPS_LO16	MYDATA
+[ 0-9a-f]+:	7c30002c 	lbe	\$16,0\(\$1\)
+[ 0-9a-f]+:	7e51802d 	lhe	\$17,-256\(\$18\)
+[ 0-9a-f]+:	7c13802d 	lhe	\$19,-256\(\$0\)
+[ 0-9a-f]+:	7eb47fad 	lhe	\$20,255\(\$21\)
+[ 0-9a-f]+:	7c167fad 	lhe	\$22,255\(\$0\)
+[ 0-9a-f]+:	2701feff 	addiu	\$1,\$24,-257
+[ 0-9a-f]+:	7c37002d 	lhe	\$23,0\(\$1\)
+[ 0-9a-f]+:	2401feff 	li	\$1,-257
+[ 0-9a-f]+:	7c39002d 	lhe	\$25,0\(\$1\)
+[ 0-9a-f]+:	27610100 	addiu	\$1,\$27,256
+[ 0-9a-f]+:	7c3a002d 	lhe	\$26,0\(\$1\)
+[ 0-9a-f]+:	24010100 	li	\$1,256
+[ 0-9a-f]+:	7c3c002d 	lhe	\$28,0\(\$1\)
+[ 0-9a-f]+:	27c1fe00 	addiu	\$1,\$30,-512
+[ 0-9a-f]+:	7c3d002d 	lhe	\$29,0\(\$1\)
+[ 0-9a-f]+:	2401fe00 	li	\$1,-512
+[ 0-9a-f]+:	7c3f002d 	lhe	\$31,0\(\$1\)
+[ 0-9a-f]+:	244101ff 	addiu	\$1,\$2,511
+[ 0-9a-f]+:	7c20002d 	lhe	\$0,0\(\$1\)
+[ 0-9a-f]+:	240101ff 	li	\$1,511
+[ 0-9a-f]+:	7c23002d 	lhe	\$3,0\(\$1\)
+[ 0-9a-f]+:	24a1fc00 	addiu	\$1,\$5,-1024
+[ 0-9a-f]+:	7c24002d 	lhe	\$4,0\(\$1\)
+[ 0-9a-f]+:	2401fc00 	li	\$1,-1024
+[ 0-9a-f]+:	7c26002d 	lhe	\$6,0\(\$1\)
+[ 0-9a-f]+:	250103ff 	addiu	\$1,\$8,1023
+[ 0-9a-f]+:	7c27002d 	lhe	\$7,0\(\$1\)
+[ 0-9a-f]+:	240103ff 	li	\$1,1023
+[ 0-9a-f]+:	7c29002d 	lhe	\$9,0\(\$1\)
+[ 0-9a-f]+:	2561f800 	addiu	\$1,\$11,-2048
+[ 0-9a-f]+:	7c2a002d 	lhe	\$10,0\(\$1\)
+[ 0-9a-f]+:	2401f800 	li	\$1,-2048
+[ 0-9a-f]+:	7c2c002d 	lhe	\$12,0\(\$1\)
+[ 0-9a-f]+:	25c107ff 	addiu	\$1,\$14,2047
+[ 0-9a-f]+:	7c2d002d 	lhe	\$13,0\(\$1\)
+[ 0-9a-f]+:	240107ff 	li	\$1,2047
+[ 0-9a-f]+:	7c2f002d 	lhe	\$15,0\(\$1\)
+[ 0-9a-f]+:	2621f000 	addiu	\$1,\$17,-4096
+[ 0-9a-f]+:	7c30002d 	lhe	\$16,0\(\$1\)
+[ 0-9a-f]+:	2401f000 	li	\$1,-4096
+[ 0-9a-f]+:	7c32002d 	lhe	\$18,0\(\$1\)
+[ 0-9a-f]+:	26810fff 	addiu	\$1,\$20,4095
+[ 0-9a-f]+:	7c33002d 	lhe	\$19,0\(\$1\)
+[ 0-9a-f]+:	24010fff 	li	\$1,4095
+[ 0-9a-f]+:	7c35002d 	lhe	\$21,0\(\$1\)
+[ 0-9a-f]+:	26e18000 	addiu	\$1,\$23,-32768
+[ 0-9a-f]+:	7c36002d 	lhe	\$22,0\(\$1\)
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+[ 0-9a-f]+:	3c010000 	lui	\$1,0x0
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+			[ 0-9a-f]+: R_MIPS_LO16	MYDATA
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+[ 0-9a-f]+:	3c018000 	lui	\$1,0x8000
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+[ 0-9a-f]+:	3c010000 	lui	\$1,0x0
+			[ 0-9a-f]+: R_MIPS_HI16	MYDATA
+[ 0-9a-f]+:	24210000 	addiu	\$1,\$1,0
+			[ 0-9a-f]+: R_MIPS_LO16	MYDATA
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+[ 0-9a-f]+:	3c010000 	lui	\$1,0x0
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+			[ 0-9a-f]+: R_MIPS_LO16	MYDATA
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+[ 0-9a-f]+:	7c3b001e 	sce	\$27,0\(\$1\)
+[ 0-9a-f]+:	24010100 	li	\$1,256
+[ 0-9a-f]+:	7c3d001e 	sce	\$29,0\(\$1\)
+[ 0-9a-f]+:	27e1fe00 	addiu	\$1,\$31,-512
+[ 0-9a-f]+:	7c3e001e 	sce	\$30,0\(\$1\)
+[ 0-9a-f]+:	2401fe00 	li	\$1,-512
+[ 0-9a-f]+:	7c20001e 	sce	\$0,0\(\$1\)
+[ 0-9a-f]+:	246101ff 	addiu	\$1,\$3,511
+[ 0-9a-f]+:	7c22001e 	sce	\$2,0\(\$1\)
+[ 0-9a-f]+:	240101ff 	li	\$1,511
+[ 0-9a-f]+:	7c24001e 	sce	\$4,0\(\$1\)
+[ 0-9a-f]+:	24c1fc00 	addiu	\$1,\$6,-1024
+[ 0-9a-f]+:	7c25001e 	sce	\$5,0\(\$1\)
+[ 0-9a-f]+:	2401fc00 	li	\$1,-1024
+[ 0-9a-f]+:	7c27001e 	sce	\$7,0\(\$1\)
+[ 0-9a-f]+:	252103ff 	addiu	\$1,\$9,1023
+[ 0-9a-f]+:	7c28001e 	sce	\$8,0\(\$1\)
+[ 0-9a-f]+:	240103ff 	li	\$1,1023
+[ 0-9a-f]+:	7c2a001e 	sce	\$10,0\(\$1\)
+[ 0-9a-f]+:	2581f800 	addiu	\$1,\$12,-2048
+[ 0-9a-f]+:	7c2b001e 	sce	\$11,0\(\$1\)
+[ 0-9a-f]+:	2401f800 	li	\$1,-2048
+[ 0-9a-f]+:	7c2d001e 	sce	\$13,0\(\$1\)
+[ 0-9a-f]+:	25e107ff 	addiu	\$1,\$15,2047
+[ 0-9a-f]+:	7c2e001e 	sce	\$14,0\(\$1\)
+[ 0-9a-f]+:	240107ff 	li	\$1,2047
+[ 0-9a-f]+:	7c30001e 	sce	\$16,0\(\$1\)
+[ 0-9a-f]+:	2641f000 	addiu	\$1,\$18,-4096
+[ 0-9a-f]+:	7c31001e 	sce	\$17,0\(\$1\)
+[ 0-9a-f]+:	2401f000 	li	\$1,-4096
+[ 0-9a-f]+:	7c33001e 	sce	\$19,0\(\$1\)
+[ 0-9a-f]+:	26a10fff 	addiu	\$1,\$21,4095
+[ 0-9a-f]+:	7c34001e 	sce	\$20,0\(\$1\)
+[ 0-9a-f]+:	24010fff 	li	\$1,4095
+[ 0-9a-f]+:	7c36001e 	sce	\$22,0\(\$1\)
+[ 0-9a-f]+:	27018000 	addiu	\$1,\$24,-32768
+[ 0-9a-f]+:	7c37001e 	sce	\$23,0\(\$1\)
+[ 0-9a-f]+:	24018000 	li	\$1,-32768
+[ 0-9a-f]+:	7c39001e 	sce	\$25,0\(\$1\)
+[ 0-9a-f]+:	27617fff 	addiu	\$1,\$27,32767
+[ 0-9a-f]+:	7c3a001e 	sce	\$26,0\(\$1\)
+[ 0-9a-f]+:	24017fff 	li	\$1,32767
+[ 0-9a-f]+:	7c3c001e 	sce	\$28,0\(\$1\)
+[ 0-9a-f]+:	24018000 	li	\$1,-32768
+[ 0-9a-f]+:	003e0821 	addu	\$1,\$1,\$30
+[ 0-9a-f]+:	7c3dff9e 	sce	\$29,-1\(\$1\)
+[ 0-9a-f]+:	24018000 	li	\$1,-32768
+[ 0-9a-f]+:	7c3fff9e 	sce	\$31,-1\(\$1\)
+[ 0-9a-f]+:	34018000 	li	\$1,0x8000
+[ 0-9a-f]+:	00220821 	addu	\$1,\$1,\$2
+[ 0-9a-f]+:	7c20001e 	sce	\$0,0\(\$1\)
+[ 0-9a-f]+:	34018000 	li	\$1,0x8000
+[ 0-9a-f]+:	7c23001e 	sce	\$3,0\(\$1\)
+[ 0-9a-f]+:	3c018000 	lui	\$1,0x8000
+[ 0-9a-f]+:	00250821 	addu	\$1,\$1,\$5
+[ 0-9a-f]+:	7c24001e 	sce	\$4,0\(\$1\)
+[ 0-9a-f]+:	3c018000 	lui	\$1,0x8000
+[ 0-9a-f]+:	7c26001e 	sce	\$6,0\(\$1\)
+[ 0-9a-f]+:	3c018000 	lui	\$1,0x8000
+[ 0-9a-f]+:	00280821 	addu	\$1,\$1,\$8
+[ 0-9a-f]+:	7c27ff9e 	sce	\$7,-1\(\$1\)
+[ 0-9a-f]+:	3c018000 	lui	\$1,0x8000
+[ 0-9a-f]+:	7c29ff9e 	sce	\$9,-1\(\$1\)
+[ 0-9a-f]+:	7d6a001e 	sce	\$10,0\(\$11\)
+[ 0-9a-f]+:	3c010000 	lui	\$1,0x0
+			[ 0-9a-f]+: R_MIPS_HI16	MYDATA
+[ 0-9a-f]+:	24210000 	addiu	\$1,\$1,0
+			[ 0-9a-f]+: R_MIPS_LO16	MYDATA
+[ 0-9a-f]+:	7c2c001e 	sce	\$12,0\(\$1\)
+[ 0-9a-f]+:	7dcd801d 	she	\$13,-256\(\$14\)
+[ 0-9a-f]+:	7c0f801d 	she	\$15,-256\(\$0\)
+[ 0-9a-f]+:	7e307f9d 	she	\$16,255\(\$17\)
+[ 0-9a-f]+:	7c127f9d 	she	\$18,255\(\$0\)
+[ 0-9a-f]+:	2681feff 	addiu	\$1,\$20,-257
+[ 0-9a-f]+:	7c33001d 	she	\$19,0\(\$1\)
+[ 0-9a-f]+:	2401feff 	li	\$1,-257
+[ 0-9a-f]+:	7c35001d 	she	\$21,0\(\$1\)
+[ 0-9a-f]+:	26e10100 	addiu	\$1,\$23,256
+[ 0-9a-f]+:	7c36001d 	she	\$22,0\(\$1\)
+[ 0-9a-f]+:	24010100 	li	\$1,256
+[ 0-9a-f]+:	7c38001d 	she	\$24,0\(\$1\)
+[ 0-9a-f]+:	2741fe00 	addiu	\$1,\$26,-512
+[ 0-9a-f]+:	7c39001d 	she	\$25,0\(\$1\)
+[ 0-9a-f]+:	2401fe00 	li	\$1,-512
+[ 0-9a-f]+:	7c3b001d 	she	\$27,0\(\$1\)
+[ 0-9a-f]+:	27a101ff 	addiu	\$1,\$29,511
+[ 0-9a-f]+:	7c3c001d 	she	\$28,0\(\$1\)
+[ 0-9a-f]+:	240101ff 	li	\$1,511
+[ 0-9a-f]+:	7c3e001d 	she	\$30,0\(\$1\)
+[ 0-9a-f]+:	2401fc00 	li	\$1,-1024
+[ 0-9a-f]+:	7c3f001d 	she	\$31,0\(\$1\)
+[ 0-9a-f]+:	2401fc00 	li	\$1,-1024
+[ 0-9a-f]+:	7c22001d 	she	\$2,0\(\$1\)
+[ 0-9a-f]+:	248103ff 	addiu	\$1,\$4,1023
+[ 0-9a-f]+:	7c23001d 	she	\$3,0\(\$1\)
+[ 0-9a-f]+:	240103ff 	li	\$1,1023
+[ 0-9a-f]+:	7c25001d 	she	\$5,0\(\$1\)
+[ 0-9a-f]+:	24e1f800 	addiu	\$1,\$7,-2048
+[ 0-9a-f]+:	7c26001d 	she	\$6,0\(\$1\)
+[ 0-9a-f]+:	2401f800 	li	\$1,-2048
+[ 0-9a-f]+:	7c28001d 	she	\$8,0\(\$1\)
+[ 0-9a-f]+:	254107ff 	addiu	\$1,\$10,2047
+[ 0-9a-f]+:	7c29001d 	she	\$9,0\(\$1\)
+[ 0-9a-f]+:	240107ff 	li	\$1,2047
+[ 0-9a-f]+:	7c2b001d 	she	\$11,0\(\$1\)
+[ 0-9a-f]+:	25a1f000 	addiu	\$1,\$13,-4096
+[ 0-9a-f]+:	7c2c001d 	she	\$12,0\(\$1\)
+[ 0-9a-f]+:	2401f000 	li	\$1,-4096
+[ 0-9a-f]+:	7c2e001d 	she	\$14,0\(\$1\)
+[ 0-9a-f]+:	26010fff 	addiu	\$1,\$16,4095
+[ 0-9a-f]+:	7c2f001d 	she	\$15,0\(\$1\)
+[ 0-9a-f]+:	24010fff 	li	\$1,4095
+[ 0-9a-f]+:	7c31001d 	she	\$17,0\(\$1\)
+[ 0-9a-f]+:	26618000 	addiu	\$1,\$19,-32768
+[ 0-9a-f]+:	7c32001d 	she	\$18,0\(\$1\)
+[ 0-9a-f]+:	24018000 	li	\$1,-32768
+[ 0-9a-f]+:	7c34001d 	she	\$20,0\(\$1\)
+[ 0-9a-f]+:	26c17fff 	addiu	\$1,\$22,32767
+[ 0-9a-f]+:	7c35001d 	she	\$21,0\(\$1\)
+[ 0-9a-f]+:	24017fff 	li	\$1,32767
+[ 0-9a-f]+:	7c37001d 	she	\$23,0\(\$1\)
+[ 0-9a-f]+:	24018000 	li	\$1,-32768
+[ 0-9a-f]+:	00390821 	addu	\$1,\$1,\$25
+[ 0-9a-f]+:	7c38ff9d 	she	\$24,-1\(\$1\)
+[ 0-9a-f]+:	24018000 	li	\$1,-32768
+[ 0-9a-f]+:	7c3aff9d 	she	\$26,-1\(\$1\)
+[ 0-9a-f]+:	34018000 	li	\$1,0x8000
+[ 0-9a-f]+:	003c0821 	addu	\$1,\$1,\$28
+[ 0-9a-f]+:	7c3b001d 	she	\$27,0\(\$1\)
+[ 0-9a-f]+:	34018000 	li	\$1,0x8000
+[ 0-9a-f]+:	7c3d001d 	she	\$29,0\(\$1\)
+[ 0-9a-f]+:	3c018000 	lui	\$1,0x8000
+[ 0-9a-f]+:	003f0821 	addu	\$1,\$1,\$31
+[ 0-9a-f]+:	7c3e001d 	she	\$30,0\(\$1\)
+[ 0-9a-f]+:	3c018000 	lui	\$1,0x8000
+[ 0-9a-f]+:	7c20001d 	she	\$0,0\(\$1\)
+[ 0-9a-f]+:	3c018000 	lui	\$1,0x8000
+[ 0-9a-f]+:	00230821 	addu	\$1,\$1,\$3
+[ 0-9a-f]+:	7c22ff9d 	she	\$2,-1\(\$1\)
+[ 0-9a-f]+:	3c018000 	lui	\$1,0x8000
+[ 0-9a-f]+:	7c24ff9d 	she	\$4,-1\(\$1\)
+[ 0-9a-f]+:	7cc5001d 	she	\$5,0\(\$6\)
+[ 0-9a-f]+:	3c010000 	lui	\$1,0x0
+			[ 0-9a-f]+: R_MIPS_HI16	MYDATA
+[ 0-9a-f]+:	24210000 	addiu	\$1,\$1,0
+			[ 0-9a-f]+: R_MIPS_LO16	MYDATA
+[ 0-9a-f]+:	7c27001d 	she	\$7,0\(\$1\)
+[ 0-9a-f]+:	7d28801f 	swe	\$8,-256\(\$9\)
+[ 0-9a-f]+:	7c0a801f 	swe	\$10,-256\(\$0\)
+[ 0-9a-f]+:	7d8b7f9f 	swe	\$11,255\(\$12\)
+[ 0-9a-f]+:	7c0d7f9f 	swe	\$13,255\(\$0\)
+[ 0-9a-f]+:	25e1feff 	addiu	\$1,\$15,-257
+[ 0-9a-f]+:	7c2e001f 	swe	\$14,0\(\$1\)
+[ 0-9a-f]+:	2401feff 	li	\$1,-257
+[ 0-9a-f]+:	7c30001f 	swe	\$16,0\(\$1\)
+[ 0-9a-f]+:	26410100 	addiu	\$1,\$18,256
+[ 0-9a-f]+:	7c31001f 	swe	\$17,0\(\$1\)
+[ 0-9a-f]+:	24010100 	li	\$1,256
+[ 0-9a-f]+:	7c33001f 	swe	\$19,0\(\$1\)
+[ 0-9a-f]+:	26a1fe00 	addiu	\$1,\$21,-512
+[ 0-9a-f]+:	7c34001f 	swe	\$20,0\(\$1\)
+[ 0-9a-f]+:	2401fe00 	li	\$1,-512
+[ 0-9a-f]+:	7c36001f 	swe	\$22,0\(\$1\)
+[ 0-9a-f]+:	270101ff 	addiu	\$1,\$24,511
+[ 0-9a-f]+:	7c37001f 	swe	\$23,0\(\$1\)
+[ 0-9a-f]+:	240101ff 	li	\$1,511
+[ 0-9a-f]+:	7c39001f 	swe	\$25,0\(\$1\)
+[ 0-9a-f]+:	2761fc00 	addiu	\$1,\$27,-1024
+[ 0-9a-f]+:	7c3a001f 	swe	\$26,0\(\$1\)
+[ 0-9a-f]+:	2401fc00 	li	\$1,-1024
+[ 0-9a-f]+:	7c3c001f 	swe	\$28,0\(\$1\)
+[ 0-9a-f]+:	27c103ff 	addiu	\$1,\$30,1023
+[ 0-9a-f]+:	7c3d001f 	swe	\$29,0\(\$1\)
+[ 0-9a-f]+:	240103ff 	li	\$1,1023
+[ 0-9a-f]+:	7c3f001f 	swe	\$31,0\(\$1\)
+[ 0-9a-f]+:	2441f800 	addiu	\$1,\$2,-2048
+[ 0-9a-f]+:	7c20001f 	swe	\$0,0\(\$1\)
+[ 0-9a-f]+:	2401f800 	li	\$1,-2048
+[ 0-9a-f]+:	7c23001f 	swe	\$3,0\(\$1\)
+[ 0-9a-f]+:	24a107ff 	addiu	\$1,\$5,2047
+[ 0-9a-f]+:	7c24001f 	swe	\$4,0\(\$1\)
+[ 0-9a-f]+:	240107ff 	li	\$1,2047
+[ 0-9a-f]+:	7c26001f 	swe	\$6,0\(\$1\)
+[ 0-9a-f]+:	2501f000 	addiu	\$1,\$8,-4096
+[ 0-9a-f]+:	7c27001f 	swe	\$7,0\(\$1\)
+[ 0-9a-f]+:	2401f000 	li	\$1,-4096
+[ 0-9a-f]+:	7c29001f 	swe	\$9,0\(\$1\)
+[ 0-9a-f]+:	25610fff 	addiu	\$1,\$11,4095
+[ 0-9a-f]+:	7c2a001f 	swe	\$10,0\(\$1\)
+[ 0-9a-f]+:	24010fff 	li	\$1,4095
+[ 0-9a-f]+:	7c2c001f 	swe	\$12,0\(\$1\)
+[ 0-9a-f]+:	25c18000 	addiu	\$1,\$14,-32768
+[ 0-9a-f]+:	7c2d001f 	swe	\$13,0\(\$1\)
+[ 0-9a-f]+:	24018000 	li	\$1,-32768
+[ 0-9a-f]+:	7c2f001f 	swe	\$15,0\(\$1\)
+[ 0-9a-f]+:	26217fff 	addiu	\$1,\$17,32767
+[ 0-9a-f]+:	7c30001f 	swe	\$16,0\(\$1\)
+[ 0-9a-f]+:	24017fff 	li	\$1,32767
+[ 0-9a-f]+:	7c32001f 	swe	\$18,0\(\$1\)
+[ 0-9a-f]+:	24018000 	li	\$1,-32768
+[ 0-9a-f]+:	00340821 	addu	\$1,\$1,\$20
+[ 0-9a-f]+:	7c33ff9f 	swe	\$19,-1\(\$1\)
+[ 0-9a-f]+:	24018000 	li	\$1,-32768
+[ 0-9a-f]+:	7c35ff9f 	swe	\$21,-1\(\$1\)
+[ 0-9a-f]+:	34018000 	li	\$1,0x8000
+[ 0-9a-f]+:	00370821 	addu	\$1,\$1,\$23
+[ 0-9a-f]+:	7c36001f 	swe	\$22,0\(\$1\)
+[ 0-9a-f]+:	34018000 	li	\$1,0x8000
+[ 0-9a-f]+:	7c38001f 	swe	\$24,0\(\$1\)
+[ 0-9a-f]+:	3c018000 	lui	\$1,0x8000
+[ 0-9a-f]+:	003a0821 	addu	\$1,\$1,\$26
+[ 0-9a-f]+:	7c39001f 	swe	\$25,0\(\$1\)
+[ 0-9a-f]+:	3c018000 	lui	\$1,0x8000
+[ 0-9a-f]+:	7c3b001f 	swe	\$27,0\(\$1\)
+[ 0-9a-f]+:	3c018000 	lui	\$1,0x8000
+[ 0-9a-f]+:	003d0821 	addu	\$1,\$1,\$29
+[ 0-9a-f]+:	7c3cff9f 	swe	\$28,-1\(\$1\)
+[ 0-9a-f]+:	3c018000 	lui	\$1,0x8000
+[ 0-9a-f]+:	7c3eff9f 	swe	\$30,-1\(\$1\)
+[ 0-9a-f]+:	7c1f001f 	swe	\$31,0\(\$0\)
+[ 0-9a-f]+:	3c010000 	lui	\$1,0x0
+			[ 0-9a-f]+: R_MIPS_HI16	MYDATA
+[ 0-9a-f]+:	24210000 	addiu	\$1,\$1,0
+			[ 0-9a-f]+: R_MIPS_LO16	MYDATA
+[ 0-9a-f]+:	7c22001f 	swe	\$2,0\(\$1\)
+[ 0-9a-f]+:	7f38801b 	cachee	0x18,-256\(\$25\)
+[ 0-9a-f]+:	7c1a801b 	cachee	0x1a,-256\(\$0\)
+[ 0-9a-f]+:	7f9b7f9b 	cachee	0x1b,255\(\$28\)
+[ 0-9a-f]+:	7c1d7f9b 	cachee	0x1d,255\(\$0\)
+[ 0-9a-f]+:	27e1feff 	addiu	\$1,\$31,-257
+[ 0-9a-f]+:	7c3e001b 	cachee	0x1e,0\(\$1\)
+[ 0-9a-f]+:	2401feff 	li	\$1,-257
+[ 0-9a-f]+:	7c20001b 	cachee	0x0,0\(\$1\)
+[ 0-9a-f]+:	24610100 	addiu	\$1,\$3,256
+[ 0-9a-f]+:	7c22001b 	cachee	0x2,0\(\$1\)
+[ 0-9a-f]+:	24010100 	li	\$1,256
+[ 0-9a-f]+:	7c24001b 	cachee	0x4,0\(\$1\)
+[ 0-9a-f]+:	24c1fe00 	addiu	\$1,\$6,-512
+[ 0-9a-f]+:	7c25001b 	cachee	0x5,0\(\$1\)
+[ 0-9a-f]+:	2401fe00 	li	\$1,-512
+[ 0-9a-f]+:	7c27001b 	cachee	0x7,0\(\$1\)
+[ 0-9a-f]+:	252101ff 	addiu	\$1,\$9,511
+[ 0-9a-f]+:	7c28001b 	cachee	0x8,0\(\$1\)
+[ 0-9a-f]+:	240101ff 	li	\$1,511
+[ 0-9a-f]+:	7c2a001b 	cachee	0xa,0\(\$1\)
+[ 0-9a-f]+:	2581fc00 	addiu	\$1,\$12,-1024
+[ 0-9a-f]+:	7c2b001b 	cachee	0xb,0\(\$1\)
+[ 0-9a-f]+:	2401fc00 	li	\$1,-1024
+[ 0-9a-f]+:	7c2d001b 	cachee	0xd,0\(\$1\)
+[ 0-9a-f]+:	25e103ff 	addiu	\$1,\$15,1023
+[ 0-9a-f]+:	7c2e001b 	cachee	0xe,0\(\$1\)
+[ 0-9a-f]+:	240103ff 	li	\$1,1023
+[ 0-9a-f]+:	7c30001b 	cachee	0x10,0\(\$1\)
+[ 0-9a-f]+:	2641f800 	addiu	\$1,\$18,-2048
+[ 0-9a-f]+:	7c31001b 	cachee	0x11,0\(\$1\)
+[ 0-9a-f]+:	2401f800 	li	\$1,-2048
+[ 0-9a-f]+:	7c33001b 	cachee	0x13,0\(\$1\)
+[ 0-9a-f]+:	26a107ff 	addiu	\$1,\$21,2047
+[ 0-9a-f]+:	7c34001b 	cachee	0x14,0\(\$1\)
+[ 0-9a-f]+:	240107ff 	li	\$1,2047
+[ 0-9a-f]+:	7c36001b 	cachee	0x16,0\(\$1\)
+[ 0-9a-f]+:	2701f000 	addiu	\$1,\$24,-4096
+[ 0-9a-f]+:	7c37001b 	cachee	0x17,0\(\$1\)
+[ 0-9a-f]+:	2401f000 	li	\$1,-4096
+[ 0-9a-f]+:	7c39001b 	cachee	0x19,0\(\$1\)
+[ 0-9a-f]+:	27610fff 	addiu	\$1,\$27,4095
+[ 0-9a-f]+:	7c3a001b 	cachee	0x1a,0\(\$1\)
+[ 0-9a-f]+:	24010fff 	li	\$1,4095
+[ 0-9a-f]+:	7c3c001b 	cachee	0x1c,0\(\$1\)
+[ 0-9a-f]+:	27c18000 	addiu	\$1,\$30,-32768
+[ 0-9a-f]+:	7c3d001b 	cachee	0x1d,0\(\$1\)
+[ 0-9a-f]+:	24018000 	li	\$1,-32768
+[ 0-9a-f]+:	7c3f001b 	cachee	0x1f,0\(\$1\)
+[ 0-9a-f]+:	24417fff 	addiu	\$1,\$2,32767
+[ 0-9a-f]+:	7c20001b 	cachee	0x0,0\(\$1\)
+[ 0-9a-f]+:	24017fff 	li	\$1,32767
+[ 0-9a-f]+:	7c23001b 	cachee	0x3,0\(\$1\)
+[ 0-9a-f]+:	24018000 	li	\$1,-32768
+[ 0-9a-f]+:	00250821 	addu	\$1,\$1,\$5
+[ 0-9a-f]+:	7c24ff9b 	cachee	0x4,-1\(\$1\)
+[ 0-9a-f]+:	24018000 	li	\$1,-32768
+[ 0-9a-f]+:	7c26ff9b 	cachee	0x6,-1\(\$1\)
+[ 0-9a-f]+:	34018000 	li	\$1,0x8000
+[ 0-9a-f]+:	00280821 	addu	\$1,\$1,\$8
+[ 0-9a-f]+:	7c27001b 	cachee	0x7,0\(\$1\)
+[ 0-9a-f]+:	34018000 	li	\$1,0x8000
+[ 0-9a-f]+:	7c29001b 	cachee	0x9,0\(\$1\)
+[ 0-9a-f]+:	3c018000 	lui	\$1,0x8000
+[ 0-9a-f]+:	002b0821 	addu	\$1,\$1,\$11
+[ 0-9a-f]+:	7c2a001b 	cachee	0xa,0\(\$1\)
+[ 0-9a-f]+:	3c018000 	lui	\$1,0x8000
+[ 0-9a-f]+:	7c2c001b 	cachee	0xc,0\(\$1\)
+[ 0-9a-f]+:	3c018000 	lui	\$1,0x8000
+[ 0-9a-f]+:	002e0821 	addu	\$1,\$1,\$14
+[ 0-9a-f]+:	7c2dff9b 	cachee	0xd,-1\(\$1\)
+[ 0-9a-f]+:	3c018000 	lui	\$1,0x8000
+[ 0-9a-f]+:	7c2fff9b 	cachee	0xf,-1\(\$1\)
+[ 0-9a-f]+:	7e30001b 	cachee	0x10,0\(\$17\)
+[ 0-9a-f]+:	3c010000 	lui	\$1,0x0
+			[ 0-9a-f]+: R_MIPS_HI16	MYDATA
+[ 0-9a-f]+:	24210000 	addiu	\$1,\$1,0
+			[ 0-9a-f]+: R_MIPS_LO16	MYDATA
+[ 0-9a-f]+:	7c32001b 	cachee	0x12,0\(\$1\)
+[ 0-9a-f]+:	7e938023 	prefe	0x13,-256\(\$20\)
+[ 0-9a-f]+:	7c158023 	prefe	0x15,-256\(\$0\)
+[ 0-9a-f]+:	7ef67fa3 	prefe	0x16,255\(\$23\)
+[ 0-9a-f]+:	7c187fa3 	prefe	0x18,255\(\$0\)
+[ 0-9a-f]+:	2741feff 	addiu	\$1,\$26,-257
+[ 0-9a-f]+:	7c390023 	prefe	0x19,0\(\$1\)
+[ 0-9a-f]+:	2401feff 	li	\$1,-257
+[ 0-9a-f]+:	7c3b0023 	prefe	0x1b,0\(\$1\)
+[ 0-9a-f]+:	27a10100 	addiu	\$1,\$29,256
+[ 0-9a-f]+:	7c3c0023 	prefe	0x1c,0\(\$1\)
+[ 0-9a-f]+:	24010100 	li	\$1,256
+[ 0-9a-f]+:	7c3e0023 	prefe	0x1e,0\(\$1\)
+[ 0-9a-f]+:	2401fe00 	li	\$1,-512
+[ 0-9a-f]+:	7c3f0023 	prefe	0x1f,0\(\$1\)
+[ 0-9a-f]+:	2401fe00 	li	\$1,-512
+[ 0-9a-f]+:	7c220023 	prefe	0x2,0\(\$1\)
+[ 0-9a-f]+:	248101ff 	addiu	\$1,\$4,511
+[ 0-9a-f]+:	7c230023 	prefe	0x3,0\(\$1\)
+[ 0-9a-f]+:	240101ff 	li	\$1,511
+[ 0-9a-f]+:	7c250023 	prefe	0x5,0\(\$1\)
+[ 0-9a-f]+:	24e1fc00 	addiu	\$1,\$7,-1024
+[ 0-9a-f]+:	7c260023 	prefe	0x6,0\(\$1\)
+[ 0-9a-f]+:	2401fc00 	li	\$1,-1024
+[ 0-9a-f]+:	7c280023 	prefe	0x8,0\(\$1\)
+[ 0-9a-f]+:	254103ff 	addiu	\$1,\$10,1023
+[ 0-9a-f]+:	7c290023 	prefe	0x9,0\(\$1\)
+[ 0-9a-f]+:	240103ff 	li	\$1,1023
+[ 0-9a-f]+:	7c2b0023 	prefe	0xb,0\(\$1\)
+[ 0-9a-f]+:	25a1f800 	addiu	\$1,\$13,-2048
+[ 0-9a-f]+:	7c2c0023 	prefe	0xc,0\(\$1\)
+[ 0-9a-f]+:	2401f800 	li	\$1,-2048
+[ 0-9a-f]+:	7c2e0023 	prefe	0xe,0\(\$1\)
+[ 0-9a-f]+:	260107ff 	addiu	\$1,\$16,2047
+[ 0-9a-f]+:	7c2f0023 	prefe	0xf,0\(\$1\)
+[ 0-9a-f]+:	240107ff 	li	\$1,2047
+[ 0-9a-f]+:	7c310023 	prefe	0x11,0\(\$1\)
+[ 0-9a-f]+:	2661f000 	addiu	\$1,\$19,-4096
+[ 0-9a-f]+:	7c320023 	prefe	0x12,0\(\$1\)
+[ 0-9a-f]+:	2401f000 	li	\$1,-4096
+[ 0-9a-f]+:	7c340023 	prefe	0x14,0\(\$1\)
+[ 0-9a-f]+:	26c10fff 	addiu	\$1,\$22,4095
+[ 0-9a-f]+:	7c350023 	prefe	0x15,0\(\$1\)
+[ 0-9a-f]+:	24010fff 	li	\$1,4095
+[ 0-9a-f]+:	7c370023 	prefe	0x17,0\(\$1\)
+[ 0-9a-f]+:	27218000 	addiu	\$1,\$25,-32768
+[ 0-9a-f]+:	7c380023 	prefe	0x18,0\(\$1\)
+[ 0-9a-f]+:	24018000 	li	\$1,-32768
+[ 0-9a-f]+:	7c3a0023 	prefe	0x1a,0\(\$1\)
+[ 0-9a-f]+:	27817fff 	addiu	\$1,\$28,32767
+[ 0-9a-f]+:	7c3b0023 	prefe	0x1b,0\(\$1\)
+[ 0-9a-f]+:	24017fff 	li	\$1,32767
+[ 0-9a-f]+:	7c3d0023 	prefe	0x1d,0\(\$1\)
+[ 0-9a-f]+:	24018000 	li	\$1,-32768
+[ 0-9a-f]+:	003f0821 	addu	\$1,\$1,\$31
+[ 0-9a-f]+:	7c3effa3 	prefe	0x1e,-1\(\$1\)
+[ 0-9a-f]+:	24018000 	li	\$1,-32768
+[ 0-9a-f]+:	7c20ffa3 	prefe	0x0,-1\(\$1\)
+[ 0-9a-f]+:	34018000 	li	\$1,0x8000
+[ 0-9a-f]+:	00230821 	addu	\$1,\$1,\$3
+[ 0-9a-f]+:	7c220023 	prefe	0x2,0\(\$1\)
+[ 0-9a-f]+:	34018000 	li	\$1,0x8000
+[ 0-9a-f]+:	7c240023 	prefe	0x4,0\(\$1\)
+[ 0-9a-f]+:	3c018000 	lui	\$1,0x8000
+[ 0-9a-f]+:	00260821 	addu	\$1,\$1,\$6
+[ 0-9a-f]+:	7c250023 	prefe	0x5,0\(\$1\)
+[ 0-9a-f]+:	3c018000 	lui	\$1,0x8000
+[ 0-9a-f]+:	7c270023 	prefe	0x7,0\(\$1\)
+[ 0-9a-f]+:	3c018000 	lui	\$1,0x8000
+[ 0-9a-f]+:	00290821 	addu	\$1,\$1,\$9
+[ 0-9a-f]+:	7c28ffa3 	prefe	0x8,-1\(\$1\)
+[ 0-9a-f]+:	3c018000 	lui	\$1,0x8000
+[ 0-9a-f]+:	7c2affa3 	prefe	0xa,-1\(\$1\)
+[ 0-9a-f]+:	7d8b0023 	prefe	0xb,0\(\$12\)
+[ 0-9a-f]+:	3c010000 	lui	\$1,0x0
+			[ 0-9a-f]+: R_MIPS_HI16	MYDATA
+[ 0-9a-f]+:	24210000 	addiu	\$1,\$1,0
+			[ 0-9a-f]+: R_MIPS_LO16	MYDATA
+[ 0-9a-f]+:	7c2d0023 	prefe	0xd,0\(\$1\)
+[ 0-9a-f]+:	24c10000 	addiu	\$1,\$6,0
+			[ 0-9a-f]+: R_MIPS_LO16	foo
+[ 0-9a-f]+:	7c250023 	prefe	0x5,0\(\$1\)
+#pass
diff --git a/gas/testsuite/gas/mips/mipsr6@jal-svr4pic-noreorder.d b/gas/testsuite/gas/mips/mipsr6@jal-svr4pic-noreorder.d
new file mode 100644
index 00000000000..88b7e318341
--- /dev/null
+++ b/gas/testsuite/gas/mips/mipsr6@jal-svr4pic-noreorder.d
@@ -0,0 +1,46 @@
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS jal-svr4pic noreorder
+#as: -32 -KPIC
+#source: jal-svr4pic-noreorder.s
+
+# Test the jal macro with -KPIC and `.set noreorder'.
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 3c1c0000 	lui	gp,0x0
+[ 	]*[0-9a-f]+: R_MIPS_HI16	_gp_disp
+[0-9a-f]+ <[^>]*> 279c0000 	addiu	gp,gp,0
+[ 	]*[0-9a-f]+: R_MIPS_LO16	_gp_disp
+[0-9a-f]+ <[^>]*> 0399e021 	addu	gp,gp,t9
+[0-9a-f]+ <[^>]*> afbc0000 	sw	gp,0\(sp\)
+[0-9a-f]+ <[^>]*> 0320f809 	jalr	t9
+[0-9a-f]+ <[^>]*> 00000000 	nop
+[0-9a-f]+ <[^>]*> 8fbc0000 	lw	gp,0\(sp\)
+[0-9a-f]+ <[^>]*> 03202009 	jalr	a0,t9
+[0-9a-f]+ <[^>]*> 00000000 	nop
+[0-9a-f]+ <[^>]*> 8fbc0000 	lw	gp,0\(sp\)
+[0-9a-f]+ <[^>]*> 8f990000 	lw	t9,0\(gp\)
+[ 	]*[0-9a-f]+: R_MIPS_GOT16	.text
+[0-9a-f]+ <[^>]*> 27390000 	addiu	t9,t9,0
+[ 	]*[0-9a-f]+: R_MIPS_LO16	.text
+[0-9a-f]+ <[^>]*> 0320f809 	jalr	t9
+[ 	]*[0-9a-f]+: R_MIPS_JALR	text_label
+[0-9a-f]+ <[^>]*> 00000000 	nop
+[0-9a-f]+ <[^>]*> 8fbc0000 	lw	gp,0\(sp\)
+[0-9a-f]+ <[^>]*> 8f990000 	lw	t9,0\(gp\)
+[ 	]*[0-9a-f]+: R_MIPS_CALL16	weak_text_label
+[0-9a-f]+ <[^>]*> 0320f809 	jalr	t9
+[ 	]*[0-9a-f]+: R_MIPS_JALR	weak_text_label
+[0-9a-f]+ <[^>]*> 00000000 	nop
+[0-9a-f]+ <[^>]*> 8fbc0000 	lw	gp,0\(sp\)
+[0-9a-f]+ <[^>]*> 8f990000 	lw	t9,0\(gp\)
+[ 	]*[0-9a-f]+: R_MIPS_CALL16	external_text_label
+[0-9a-f]+ <[^>]*> 0320f809 	jalr	t9
+[ 	]*[0-9a-f]+: R_MIPS_JALR	external_text_label
+[0-9a-f]+ <[^>]*> 00000000 	nop
+[0-9a-f]+ <[^>]*> 8fbc0000 	lw	gp,0\(sp\)
+[0-9a-f]+ <[^>]*> 1000ffff 	b	0+005c <text_label\+0x5c>
+[	]*5c: .*R_MIPS_PC16	text_label
+[0-9a-f]+ <[^>]*> 00000000 	nop
+	\.\.\.
diff --git a/gas/testsuite/gas/mips/mipsr6@jal-svr4pic.d b/gas/testsuite/gas/mips/mipsr6@jal-svr4pic.d
new file mode 100644
index 00000000000..e0a5c0e2d3e
--- /dev/null
+++ b/gas/testsuite/gas/mips/mipsr6@jal-svr4pic.d
@@ -0,0 +1,44 @@
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS jal-svr4pic
+#as: -32 -KPIC
+#source: jal-svr4pic.s
+
+# Test the jal macro with -KPIC.
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 3c1c0000 	lui	gp,0x0
+[ 	]*[0-9a-f]+: R_MIPS_HI16	_gp_disp
+[0-9a-f]+ <[^>]*> 279c0000 	addiu	gp,gp,0
+[ 	]*[0-9a-f]+: R_MIPS_LO16	_gp_disp
+[0-9a-f]+ <[^>]*> 0399e021 	addu	gp,gp,t9
+[0-9a-f]+ <[^>]*> afbc0000 	sw	gp,0\(sp\)
+[0-9a-f]+ <[^>]*> 0320f809 	jalr	t9
+[0-9a-f]+ <[^>]*> 00000000 	nop
+[0-9a-f]+ <[^>]*> 03202009 	jalr	a0,t9
+[0-9a-f]+ <[^>]*> 8fbc0000 	lw	gp,0\(sp\)
+[0-9a-f]+ <[^>]*> 8fbc0000 	lw	gp,0\(sp\)
+[0-9a-f]+ <[^>]*> 8f990000 	lw	t9,0\(gp\)
+[ 	]*[0-9a-f]+: R_MIPS_GOT16	.text
+[0-9a-f]+ <[^>]*> 27390000 	addiu	t9,t9,0
+[ 	]*[0-9a-f]+: R_MIPS_LO16	.text
+[0-9a-f]+ <[^>]*> 0320f809 	jalr	t9
+[ 	]*[0-9a-f]+: R_MIPS_JALR	text_label
+[0-9a-f]+ <[^>]*> 00000000 	nop
+[0-9a-f]+ <[^>]*> 8fbc0000 	lw	gp,0\(sp\)
+[0-9a-f]+ <[^>]*> 8f990000 	lw	t9,0\(gp\)
+[ 	]*[0-9a-f]+: R_MIPS_CALL16	weak_text_label
+[0-9a-f]+ <[^>]*> 0320f809 	jalr	t9
+[ 	]*[0-9a-f]+: R_MIPS_JALR	weak_text_label
+[0-9a-f]+ <[^>]*> 00000000 	nop
+[0-9a-f]+ <[^>]*> 8fbc0000 	lw	gp,0\(sp\)
+[0-9a-f]+ <[^>]*> 8f990000 	lw	t9,0\(gp\)
+[ 	]*[0-9a-f]+: R_MIPS_CALL16	external_text_label
+[0-9a-f]+ <[^>]*> 0320f809 	jalr	t9
+[ 	]*[0-9a-f]+: R_MIPS_JALR	external_text_label
+[0-9a-f]+ <[^>]*> 00000000 	nop
+[0-9a-f]+ <[^>]*> 1000ffff 	b	0+0054 <text_label\+0x54>
+[	]*54: .*R_MIPS_PC16	text_label
+[0-9a-f]+ <[^>]*> 8fbc0000 	lw	gp,0\(sp\)
+	\.\.\.
diff --git a/gas/testsuite/gas/mips/mipsr6@ld-zero-2.d b/gas/testsuite/gas/mips/mipsr6@ld-zero-2.d
new file mode 100644
index 00000000000..2b1344f8ba2
--- /dev/null
+++ b/gas/testsuite/gas/mips/mipsr6@ld-zero-2.d
@@ -0,0 +1,13 @@
+#objdump: -dr --prefix-addresses
+#as: -32
+#name: MIPS II load $zero
+#source: ld-zero-2.s
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> lui	at,0x1234
+[0-9a-f]+ <[^>]*> ori	at,at,0x5600
+[0-9a-f]+ <[^>]*> addu	at,at,v0
+[0-9a-f]+ <[^>]*> ll	zero,120\(at\)
+	\.\.\.
diff --git a/gas/testsuite/gas/mips/mipsr6@ld-zero-3.d b/gas/testsuite/gas/mips/mipsr6@ld-zero-3.d
new file mode 100644
index 00000000000..855dd49cb79
--- /dev/null
+++ b/gas/testsuite/gas/mips/mipsr6@ld-zero-3.d
@@ -0,0 +1,19 @@
+#objdump: -dr --prefix-addresses
+#as: -mabi=o64
+#name: MIPS III load $zero
+#source: ld-zero-3.s
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> lui	at,0x1234
+[0-9a-f]+ <[^>]*> addu	at,at,v0
+[0-9a-f]+ <[^>]*> lwu	zero,22136\(at\)
+[0-9a-f]+ <[^>]*> lui	at,0x1234
+[0-9a-f]+ <[^>]*> addu	at,at,v0
+[0-9a-f]+ <[^>]*> ld	zero,22136\(at\)
+[0-9a-f]+ <[^>]*> lui	at,0x1234
+[0-9a-f]+ <[^>]*> ori	at,at,0x5600
+[0-9a-f]+ <[^>]*> addu	at,at,v0
+[0-9a-f]+ <[^>]*> lld	zero,120\(at\)
+	\.\.\.
diff --git a/gas/testsuite/gas/mips/mipsr6@loc-swap-dis.d b/gas/testsuite/gas/mips/mipsr6@loc-swap-dis.d
new file mode 100644
index 00000000000..d377f6abe81
--- /dev/null
+++ b/gas/testsuite/gas/mips/mipsr6@loc-swap-dis.d
@@ -0,0 +1,34 @@
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS DWARF-2 location information with branch swapping disassembly
+#as: -32
+#source: loc-swap.s
+
+# Check branch swapping with DWARF-2 location information.
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 02002021 	move	a0,s0
+[0-9a-f]+ <[^>]*> 00800009 	jr	a0
+[0-9a-f]+ <[^>]*> 00000000 	nop
+[0-9a-f]+ <[^>]*> 00800009 	jr	a0
+[0-9a-f]+ <[^>]*> 0200f821 	move	ra,s0
+[0-9a-f]+ <[^>]*> 03e00009 	jr	ra
+[0-9a-f]+ <[^>]*> 02002021 	move	a0,s0
+[0-9a-f]+ <[^>]*> 0200f821 	move	ra,s0
+[0-9a-f]+ <[^>]*> 03e00009 	jr	ra
+[0-9a-f]+ <[^>]*> 00000000 	nop
+[0-9a-f]+ <[^>]*> 02002021 	move	a0,s0
+[0-9a-f]+ <[^>]*> 0080f809 	jalr	a0
+[0-9a-f]+ <[^>]*> 00000000 	nop
+[0-9a-f]+ <[^>]*> 0200f821 	move	ra,s0
+[0-9a-f]+ <[^>]*> 0080f809 	jalr	a0
+[0-9a-f]+ <[^>]*> 00000000 	nop
+[0-9a-f]+ <[^>]*> 0c000000 	jal	0+0000 <foo>
+[ 	]*[0-9a-f]+: R_MIPS_26	bar
+[0-9a-f]+ <[^>]*> 02002021 	move	a0,s0
+[0-9a-f]+ <[^>]*> 0200f821 	move	ra,s0
+[0-9a-f]+ <[^>]*> 0c000000 	jal	0+0000 <foo>
+[ 	]*[0-9a-f]+: R_MIPS_26	bar
+[0-9a-f]+ <[^>]*> 00000000 	nop
+	\.\.\.
diff --git a/gas/testsuite/gas/mips/mipsr6@mips32-cp2.d b/gas/testsuite/gas/mips/mipsr6@mips32-cp2.d
new file mode 100644
index 00000000000..2b7c098972a
--- /dev/null
+++ b/gas/testsuite/gas/mips/mipsr6@mips32-cp2.d
@@ -0,0 +1,20 @@
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS MIPS32 cop2 instructions
+#source: mips32-cp2.s
+#as: -32
+
+# Check MIPS32 cop2 instruction assembly
+
+.*: +file format .*mips.*
+
+Disassembly of section .text:
+0+0000 <[^>]*> 48411000 	cfc2	at,\$2
+0+0004 <[^>]*> 4b234567 	c2	0x1234567
+0+0008 <[^>]*> 48c21800 	ctc2	v0,\$3
+0+000c <[^>]*> 48032000 	mfc2	v1,\$4
+0+0010 <[^>]*> 48042800 	mfc2	a0,\$5
+0+0014 <[^>]*> 48053007 	mfc2	a1,\$6,7
+0+0018 <[^>]*> 48863800 	mtc2	a2,\$7
+0+001c <[^>]*> 48874000 	mtc2	a3,\$8
+0+0020 <[^>]*> 48884807 	mtc2	t0,\$9,7
+#pass
diff --git a/gas/testsuite/gas/mips/mipsr6@mips32-dsp.d b/gas/testsuite/gas/mips/mipsr6@mips32-dsp.d
new file mode 100644
index 00000000000..2c9046e9257
--- /dev/null
+++ b/gas/testsuite/gas/mips/mipsr6@mips32-dsp.d
@@ -0,0 +1,147 @@
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS DSP ASE for MIPS32
+#as: -mdsp -32
+#source: mips32-dsp.s
+
+# Check MIPS DSP ASE for MIPS32 Instruction Assembly
+
+.*: +file format .*mips.*
+
+Disassembly of section .text:
+0+0000 <[^>]*> 7c220290 	addq\.ph	zero,at,v0
+0+0004 <[^>]*> 7c430b90 	addq_s\.ph	at,v0,v1
+0+0008 <[^>]*> 7c641590 	addq_s\.w	v0,v1,a0
+0+000c <[^>]*> 7c851810 	addu\.qb	v1,a0,a1
+0+0010 <[^>]*> 7ca62110 	addu_s\.qb	a0,a1,a2
+0+0014 <[^>]*> 7cc72ad0 	subq\.ph	a1,a2,a3
+0+0018 <[^>]*> 7ce833d0 	subq_s\.ph	a2,a3,t0
+0+001c <[^>]*> 7d093dd0 	subq_s\.w	a3,t0,t1
+0+0020 <[^>]*> 7d2a4050 	subu\.qb	t0,t1,t2
+0+0024 <[^>]*> 7d4b4950 	subu_s\.qb	t1,t2,t3
+0+0028 <[^>]*> 7d6c5410 	addsc	t2,t3,t4
+0+002c <[^>]*> 7d8d5c50 	addwc	t3,t4,t5
+0+0030 <[^>]*> 7dae6490 	modsub	t4,t5,t6
+0+0034 <[^>]*> 7dc06d10 	raddu\.w\.qb	t5,t6
+0+0038 <[^>]*> 7c0f7252 	absq_s\.ph	t6,t7
+0+003c <[^>]*> 7c107c52 	absq_s\.w	t7,s0
+0+0040 <[^>]*> 7e328311 	precrq\.qb\.ph	s0,s1,s2
+0+0044 <[^>]*> 7e538d11 	precrq\.ph\.w	s1,s2,s3
+0+0048 <[^>]*> 7e749551 	precrq_rs\.ph\.w	s2,s3,s4
+0+004c <[^>]*> 7e959bd1 	precrqu_s\.qb\.ph	s3,s4,s5
+0+0050 <[^>]*> 7c15a312 	preceq\.w\.phl	s4,s5
+0+0054 <[^>]*> 7c16ab52 	preceq\.w\.phr	s5,s6
+0+0058 <[^>]*> 7c17b112 	precequ\.ph\.qbl	s6,s7
+0+005c <[^>]*> 7c18b952 	precequ\.ph\.qbr	s7,t8
+0+0060 <[^>]*> 7c19c192 	precequ\.ph\.qbla	t8,t9
+0+0064 <[^>]*> 7c1ac9d2 	precequ\.ph\.qbra	t9,k0
+0+0068 <[^>]*> 7c1bd712 	preceu\.ph\.qbl	k0,k1
+0+006c <[^>]*> 7c1cdf52 	preceu\.ph\.qbr	k1,gp
+0+0070 <[^>]*> 7c1de792 	preceu\.ph\.qbla	gp,sp
+0+0074 <[^>]*> 7c1eefd2 	preceu\.ph\.qbra	sp,s8
+0+0078 <[^>]*> 7c1ff013 	shll\.qb	s8,ra,0x0
+0+007c <[^>]*> 7cfff013 	shll\.qb	s8,ra,0x7
+0+0080 <[^>]*> 7c20f893 	shllv\.qb	ra,zero,at
+0+0084 <[^>]*> 7c010213 	shll\.ph	zero,at,0x0
+0+0088 <[^>]*> 7de10213 	shll\.ph	zero,at,0xf
+0+008c <[^>]*> 7c620a93 	shllv\.ph	at,v0,v1
+0+0090 <[^>]*> 7c031313 	shll_s\.ph	v0,v1,0x0
+0+0094 <[^>]*> 7de31313 	shll_s\.ph	v0,v1,0xf
+0+0098 <[^>]*> 7ca41b93 	shllv_s\.ph	v1,a0,a1
+0+009c <[^>]*> 7c052513 	shll_s\.w	a0,a1,0x0
+0+00a0 <[^>]*> 7fe52513 	shll_s\.w	a0,a1,0x1f
+0+00a4 <[^>]*> 7ce62d93 	shllv_s\.w	a1,a2,a3
+0+00a8 <[^>]*> 7c073053 	shrl\.qb	a2,a3,0x0
+0+00ac <[^>]*> 7ce73053 	shrl\.qb	a2,a3,0x7
+0+00b0 <[^>]*> 7d2838d3 	shrlv\.qb	a3,t0,t1
+0+00b4 <[^>]*> 7c094253 	shra\.ph	t0,t1,0x0
+0+00b8 <[^>]*> 7de94253 	shra\.ph	t0,t1,0xf
+0+00bc <[^>]*> 7d6a4ad3 	shrav\.ph	t1,t2,t3
+0+00c0 <[^>]*> 7c0b5353 	shra_r\.ph	t2,t3,0x0
+0+00c4 <[^>]*> 7deb5353 	shra_r\.ph	t2,t3,0xf
+0+00c8 <[^>]*> 7dac5bd3 	shrav_r\.ph	t3,t4,t5
+0+00cc <[^>]*> 7c0d6553 	shra_r\.w	t4,t5,0x0
+0+00d0 <[^>]*> 7fed6553 	shra_r\.w	t4,t5,0x1f
+0+00d4 <[^>]*> 7dee6dd3 	shrav_r\.w	t5,t6,t7
+0+00d8 <[^>]*> 7df07190 	muleu_s\.ph\.qbl	t6,t7,s0
+0+00dc <[^>]*> 7e1179d0 	muleu_s\.ph\.qbr	t7,s0,s1
+0+00e0 <[^>]*> 7e3287d0 	mulq_rs\.ph	s0,s1,s2
+0+00e4 <[^>]*> 7e538f10 	muleq_s\.w\.phl	s1,s2,s3
+0+00e8 <[^>]*> 7e749750 	muleq_s\.w\.phr	s2,s3,s4
+0+00ec <[^>]*> 7e7400f0 	dpau\.h\.qbl	\$ac0,s3,s4
+0+00f0 <[^>]*> 7e9509f0 	dpau\.h\.qbr	\$ac1,s4,s5
+0+00f4 <[^>]*> 7eb612f0 	dpsu\.h\.qbl	\$ac2,s5,s6
+0+00f8 <[^>]*> 7ed71bf0 	dpsu\.h\.qbr	\$ac3,s6,s7
+0+00fc <[^>]*> 7ef80130 	dpaq_s\.w\.ph	\$ac0,s7,t8
+0+0100 <[^>]*> 7f190970 	dpsq_s\.w\.ph	\$ac1,t8,t9
+0+0104 <[^>]*> 7f3a11b0 	mulsaq_s\.w\.ph	\$ac2,t9,k0
+0+0108 <[^>]*> 7f5b1b30 	dpaq_sa\.l\.w	\$ac3,k0,k1
+0+010c <[^>]*> 7f7c0370 	dpsq_sa\.l\.w	\$ac0,k1,gp
+0+0110 <[^>]*> 7f9d0d30 	maq_s\.w\.phl	\$ac1,gp,sp
+0+0114 <[^>]*> 7fbe15b0 	maq_s\.w\.phr	\$ac2,sp,s8
+0+0118 <[^>]*> 7fdf1c30 	maq_sa\.w\.phl	\$ac3,s8,ra
+0+011c <[^>]*> 7fe004b0 	maq_sa\.w\.phr	\$ac0,ra,zero
+0+0120 <[^>]*> 7c0106d2 	bitrev	zero,at
+0+0124 <[^>]*> 7c41000c 	insv	at,v0
+0+0128 <[^>]*> 7c001092 	repl\.qb	v0,0x0
+0+012c <[^>]*> 7cff1092 	repl\.qb	v0,0xff
+0+0130 <[^>]*> 7c0418d2 	replv\.qb	v1,a0
+0+0134 <[^>]*> 7e002292 	repl\.ph	a0,-512
+0+0138 <[^>]*> 7dff2292 	repl\.ph	a0,511
+0+013c <[^>]*> 7c062ad2 	replv\.ph	a1,a2
+0+0140 <[^>]*> 7cc70011 	cmpu\.eq\.qb	a2,a3
+0+0144 <[^>]*> 7ce80051 	cmpu\.lt\.qb	a3,t0
+0+0148 <[^>]*> 7d090091 	cmpu\.le\.qb	t0,t1
+0+014c <[^>]*> 7d4b4911 	cmpgu\.eq\.qb	t1,t2,t3
+0+0150 <[^>]*> 7d6c5151 	cmpgu\.lt\.qb	t2,t3,t4
+0+0154 <[^>]*> 7d8d5991 	cmpgu\.le\.qb	t3,t4,t5
+0+0158 <[^>]*> 7d8d0211 	cmp\.eq\.ph	t4,t5
+0+015c <[^>]*> 7dae0251 	cmp\.lt\.ph	t5,t6
+0+0160 <[^>]*> 7dcf0291 	cmp\.le\.ph	t6,t7
+0+0164 <[^>]*> 7e1178d1 	pick\.qb	t7,s0,s1
+0+0168 <[^>]*> 7e3282d1 	pick\.ph	s0,s1,s2
+0+016c <[^>]*> 7e538b91 	packrl\.ph	s1,s2,s3
+0+0170 <[^>]*> 7c120838 	extr\.w	s2,\$ac1,0x0
+0+0174 <[^>]*> 7ff20838 	extr\.w	s2,\$ac1,0x1f
+0+0178 <[^>]*> 7c131138 	extr_r\.w	s3,\$ac2,0x0
+0+017c <[^>]*> 7ff31138 	extr_r\.w	s3,\$ac2,0x1f
+0+0180 <[^>]*> 7c1419b8 	extr_rs\.w	s4,\$ac3,0x0
+0+0184 <[^>]*> 7ff419b8 	extr_rs\.w	s4,\$ac3,0x1f
+0+0188 <[^>]*> 7c1503b8 	extr_s\.h	s5,\$ac0,0x0
+0+018c <[^>]*> 7ff503b8 	extr_s\.h	s5,\$ac0,0x1f
+0+0190 <[^>]*> 7ef60bf8 	extrv_s\.h	s6,\$ac1,s7
+0+0194 <[^>]*> 7f171078 	extrv\.w	s7,\$ac2,t8
+0+0198 <[^>]*> 7f381978 	extrv_r\.w	t8,\$ac3,t9
+0+019c <[^>]*> 7f5901f8 	extrv_rs\.w	t9,\$ac0,k0
+0+01a0 <[^>]*> 7c1a08b8 	extp	k0,\$ac1,0x0
+0+01a4 <[^>]*> 7ffa08b8 	extp	k0,\$ac1,0x1f
+0+01a8 <[^>]*> 7f9b10f8 	extpv	k1,\$ac2,gp
+0+01ac <[^>]*> 7c1c1ab8 	extpdp	gp,\$ac3,0x0
+0+01b0 <[^>]*> 7ffc1ab8 	extpdp	gp,\$ac3,0x1f
+0+01b4 <[^>]*> 7fdd02f8 	extpdpv	sp,\$ac0,s8
+0+01b8 <[^>]*> 7e000eb8 	shilo	\$ac1,-32
+0+01bc <[^>]*> 7df00eb8 	shilo	\$ac1,31
+0+01c0 <[^>]*> 7fc016f8 	shilov	\$ac2,s8
+0+01c4 <[^>]*> 7fe01ff8 	mthlip	ra,\$ac3
+0+01c8 <[^>]*> 00000010 	mfhi	zero,\$ac0
+0+01cc <[^>]*> 00200812 	mflo	at,\$ac1
+0+01d0 <[^>]*> 00401011 	mthi	v0,\$ac2
+0+01d4 <[^>]*> 00601813 	mtlo	v1,\$ac3
+0+01d8 <[^>]*> 7c8004f8 	wrdsp	a0,0x0
+0+01dc <[^>]*> 7c81fcf8 	wrdsp	a0,0x3f
+0+01e0 <[^>]*> 7cbffcf8 	wrdsp	a1
+0+01e4 <[^>]*> 7c0034b8 	rddsp	a2,0x0
+0+01e8 <[^>]*> 7c3f34b8 	rddsp	a2,0x3f
+0+01ec <[^>]*> 7fff3cb8 	rddsp	a3
+0+01f0 <[^>]*> 7d49418a 	lbux	t0,t1\(t2\)
+0+01f4 <[^>]*> 7d6a490a 	lhx	t1,t2\(t3\)
+0+01f8 <[^>]*> 7d8b500a 	lwx	t2,t3\(t4\)
+0+01fc <[^>]*> 041cffff 	bposge32	000001fc <[^>]*>
+			1fc: R_MIPS_PC16	text_label
+0+0200 <[^>]*> 00000000 	nop
+0+0204 <[^>]*> 716c1000 	madd	\$ac2,t3,t4
+0+0208 <[^>]*> 718d1801 	maddu	\$ac3,t4,t5
+0+020c <[^>]*> 71ae0004 	msub	\$ac0,t5,t6
+0+0210 <[^>]*> 71cf0805 	msubu	\$ac1,t6,t7
+0+0214 <[^>]*> 02b61818 	mult	\$ac3,s5,s6
+0+0218 <[^>]*> 02d70019 	multu	\$ac0,s6,s7
+	\.\.\.
diff --git a/gas/testsuite/gas/mips/mipsr6@mips32-dspr2.d b/gas/testsuite/gas/mips/mipsr6@mips32-dspr2.d
new file mode 100644
index 00000000000..feb0abcfd2c
--- /dev/null
+++ b/gas/testsuite/gas/mips/mipsr6@mips32-dspr2.d
@@ -0,0 +1,73 @@
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS DSP ASE Rev2 for MIPS32
+#as: -mdspr2 -32
+#source: mips32-dspr2.s
+
+# Check MIPS DSP ASE Rev2 for MIPS32 Instruction Assembly
+
+.*: +file format .*mips.*
+
+Disassembly of section .text:
+0+0000 <[^>]*> 7c010052 	absq_s\.qb	zero,at
+0+0004 <[^>]*> 7c430a10 	addu\.ph	at,v0,v1
+0+0008 <[^>]*> 7c641310 	addu_s\.ph	v0,v1,a0
+0+000c <[^>]*> 7c851818 	adduh\.qb	v1,a0,a1
+0+0010 <[^>]*> 7ca62098 	adduh_r\.qb	a0,a1,a2
+0+0014 <[^>]*> 7cc50031 	append	a1,a2,0x0
+0+0018 <[^>]*> 7cc5f831 	append	a1,a2,0x1f
+0+001c <[^>]*> 00000000 	nop
+0+0020 <[^>]*> 7ce60c31 	balign	a2,a3,0x1
+0+0024 <[^>]*> 7cc73391 	packrl\.ph	a2,a2,a3
+0+0028 <[^>]*> 7ce61c31 	balign	a2,a3,0x3
+0+002c <[^>]*> 7ce83611 	cmpgdu\.eq\.qb	a2,a3,t0
+0+0030 <[^>]*> 7d093e51 	cmpgdu\.lt\.qb	a3,t0,t1
+0+0034 <[^>]*> 7d2a4691 	cmpgdu\.le\.qb	t0,t1,t2
+0+0038 <[^>]*> 7d2a0030 	dpa\.w\.ph	\$ac0,t1,t2
+0+003c <[^>]*> 7d4b0870 	dps\.w\.ph	\$ac1,t2,t3
+0+0040 <[^>]*> 716c1000 	madd	\$ac2,t3,t4
+0+0044 <[^>]*> 718d1801 	maddu	\$ac3,t4,t5
+0+0048 <[^>]*> 71ae0004 	msub	\$ac0,t5,t6
+0+004c <[^>]*> 71cf0805 	msubu	\$ac1,t6,t7
+0+0050 <[^>]*> 7e117b18 	mul\.ph	t7,s0,s1
+0+0054 <[^>]*> 7e328398 	mul_s\.ph	s0,s1,s2
+0+0058 <[^>]*> 7e538dd8 	mulq_rs\.w	s1,s2,s3
+0+005c <[^>]*> 7e749790 	mulq_s\.ph	s2,s3,s4
+0+0060 <[^>]*> 7e959d98 	mulq_s\.w	s3,s4,s5
+0+0064 <[^>]*> 7e9510b0 	mulsa\.w\.ph	\$ac2,s4,s5
+0+0068 <[^>]*> 02b61818 	mult	\$ac3,s5,s6
+0+006c <[^>]*> 02d70019 	multu	\$ac0,s6,s7
+0+0070 <[^>]*> 7f19bb51 	precr\.qb\.ph	s7,t8,t9
+0+0074 <[^>]*> 7f380791 	precr_sra\.ph\.w	t8,t9,0x0
+0+0078 <[^>]*> 7f38ff91 	precr_sra\.ph\.w	t8,t9,0x1f
+0+007c <[^>]*> 7f5907d1 	precr_sra_r\.ph\.w	t9,k0,0x0
+0+0080 <[^>]*> 7f59ffd1 	precr_sra_r\.ph\.w	t9,k0,0x1f
+0+0084 <[^>]*> 7f7a0071 	prepend	k0,k1,0x0
+0+0088 <[^>]*> 7f7af871 	prepend	k0,k1,0x1f
+0+008c <[^>]*> 7c1cd913 	shra\.qb	k1,gp,0x0
+0+0090 <[^>]*> 7cfcd913 	shra\.qb	k1,gp,0x7
+0+0094 <[^>]*> 7c1de153 	shra_r\.qb	gp,sp,0x0
+0+0098 <[^>]*> 7cfde153 	shra_r\.qb	gp,sp,0x7
+0+009c <[^>]*> 7ffee993 	shrav\.qb	sp,s8,ra
+0+00a0 <[^>]*> 7c1ff1d3 	shrav_r\.qb	s8,ra,zero
+0+00a4 <[^>]*> 7c00fe53 	shrl\.ph	ra,zero,0x0
+0+00a8 <[^>]*> 7de0fe53 	shrl\.ph	ra,zero,0xf
+0+00ac <[^>]*> 7c4106d3 	shrlv\.ph	zero,at,v0
+0+00b0 <[^>]*> 7c430a50 	subu\.ph	at,v0,v1
+0+00b4 <[^>]*> 7c641350 	subu_s\.ph	v0,v1,a0
+0+00b8 <[^>]*> 7c851858 	subuh\.qb	v1,a0,a1
+0+00bc <[^>]*> 7ca620d8 	subuh_r\.qb	a0,a1,a2
+0+00c0 <[^>]*> 7cc72a18 	addqh\.ph	a1,a2,a3
+0+00c4 <[^>]*> 7ce83298 	addqh_r\.ph	a2,a3,t0
+0+00c8 <[^>]*> 7d093c18 	addqh\.w	a3,t0,t1
+0+00cc <[^>]*> 7d2a4498 	addqh_r\.w	t0,t1,t2
+0+00d0 <[^>]*> 7d4b4a58 	subqh\.ph	t1,t2,t3
+0+00d4 <[^>]*> 7d6c52d8 	subqh_r\.ph	t2,t3,t4
+0+00d8 <[^>]*> 7d8d5c58 	subqh\.w	t3,t4,t5
+0+00dc <[^>]*> 7dae64d8 	subqh_r\.w	t4,t5,t6
+0+00e0 <[^>]*> 7dae0a30 	dpax\.w\.ph	\$ac1,t5,t6
+0+00e4 <[^>]*> 7dcf1270 	dpsx\.w\.ph	\$ac2,t6,t7
+0+00e8 <[^>]*> 7df01e30 	dpaqx_s\.w\.ph	\$ac3,t7,s0
+0+00ec <[^>]*> 7e1106b0 	dpaqx_sa\.w\.ph	\$ac0,s0,s1
+0+00f0 <[^>]*> 7e320e70 	dpsqx_s\.w\.ph	\$ac1,s1,s2
+0+00f4 <[^>]*> 7e5316f0 	dpsqx_sa\.w\.ph	\$ac2,s2,s3
+	\.\.\.
diff --git a/gas/testsuite/gas/mips/mipsr6@mips32-imm.d b/gas/testsuite/gas/mips/mipsr6@mips32-imm.d
new file mode 100644
index 00000000000..5a98f8d9988
--- /dev/null
+++ b/gas/testsuite/gas/mips/mipsr6@mips32-imm.d
@@ -0,0 +1,13 @@
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS MIPS32 WAIT and SDBBP instructions
+#as: -32
+#source: mips32-imm.s
+
+# Check MIPS32 WAIT and SDBBP instruction assembly
+
+.*: +file format .*mips.*
+
+Disassembly of section .text:
+[0-9a-f]+ <[^>]*> 4359e260 	wait	0x56789
+[0-9a-f]+ <[^>]*> 0159e24e 	sdbbp	0x56789
+	\.\.\.
diff --git a/gas/testsuite/gas/mips/mipsr6@mips32.d b/gas/testsuite/gas/mips/mipsr6@mips32.d
new file mode 100644
index 00000000000..e7af216b499
--- /dev/null
+++ b/gas/testsuite/gas/mips/mipsr6@mips32.d
@@ -0,0 +1,32 @@
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS MIPS32 instructions
+#as: -32
+#source: mips32.s
+
+# Check MIPS32 instruction assembly
+
+.*: +file format .*mips.*
+
+Disassembly of section .text:
+0+0000 <[^>]*> 00400851 	clo	at,v0
+0+0004 <[^>]*> 00801850 	clz	v1,a0
+0+0008 <[^>]*> 01cf6898 	mul	t5,t6,t7
+0+000c <[^>]*> 7e040035 	pref	0x4,0\(s0\)
+0+0010 <[^>]*> 00000040 	ssnop
+0+0014 <[^>]*> 7c250025 	cache	0x5,0\(at\)
+0+0018 <[^>]*> 42000018 	eret
+0+001c <[^>]*> 42000008 	tlbp
+0+0020 <[^>]*> 42000001 	tlbr
+0+0024 <[^>]*> 42000002 	tlbwi
+0+0028 <[^>]*> 42000006 	tlbwr
+0+002c <[^>]*> 42000020 	wait
+0+0030 <[^>]*> 42000020 	wait
+0+0034 <[^>]*> 4200d160 	wait	0x345
+0+0038 <[^>]*> 0000000d 	break
+0+003c <[^>]*> 0000000d 	break
+0+0040 <[^>]*> 0345000d 	break	0x345
+0+0044 <[^>]*> 0048d14d 	break	0x48,0x345
+0+0048 <[^>]*> 0000000e 	sdbbp
+0+004c <[^>]*> 0000000e 	sdbbp
+0+0050 <[^>]*> 0000d14e 	sdbbp	0x345
+	\.\.\.
diff --git a/gas/testsuite/gas/mips/mipsr6@mips32r2-ill.l b/gas/testsuite/gas/mips/mipsr6@mips32r2-ill.l
new file mode 100644
index 00000000000..adffffde61a
--- /dev/null
+++ b/gas/testsuite/gas/mips/mipsr6@mips32r2-ill.l
@@ -0,0 +1,13 @@
+.*: Assembler messages:
+.*:12: Error: operand 3 out of range `ext \$4,\$5,-1,1'
+.*:15: Error: operand 3 out of range `ext \$4,\$5,32,1'
+.*:18: Error: operand 4 out of range `ext \$4,\$5,0,0'
+.*:21: Error: operand 4 out of range `ext \$4,\$5,0,33'
+.*:24: Error: operand 4 out of range `ext \$4,\$5,0,0'
+.*:27: Error: operand 4 out of range `ext \$4,\$5,31,2'
+.*:30: Error: operand 3 out of range `ins \$4,\$5,-1,1'
+.*:33: Error: operand 3 out of range `ins \$4,\$5,32,1'
+.*:36: Error: operand 4 out of range `ins \$4,\$5,0,0'
+.*:39: Error: operand 4 out of range `ins \$4,\$5,0,33'
+.*:42: Error: operand 4 out of range `ins \$4,\$5,0,0'
+.*:45: Error: operand 4 out of range `ins \$4,\$5,31,2'
diff --git a/gas/testsuite/gas/mips/mipsr6@mips32r2-ill.s b/gas/testsuite/gas/mips/mipsr6@mips32r2-ill.s
new file mode 100644
index 00000000000..0564316f927
--- /dev/null
+++ b/gas/testsuite/gas/mips/mipsr6@mips32r2-ill.s
@@ -0,0 +1,58 @@
+# source file to test illegal mips32r2 instructions
+
+        .set noreorder
+      .set noat
+
+      .text
+text_label:
+
+      # insert and extract position/size checks:
+
+	# ext constraint: 0 <= pos < 32
+	ext	$4, $5, -1, 1		# error
+	ext	$4, $5, 0, 1
+	ext	$4, $5, 31, 1
+	ext	$4, $5, 32, 1		# error
+
+	# ext constraint: 0 < size <= 32
+	ext	$4, $5, 0, 0		# error
+	ext	$4, $5, 0, 1
+	ext	$4, $5, 0, 32
+	ext	$4, $5, 0, 33		# error
+
+	# ext constraint: 0 < (pos+size) <= 32
+	ext	$4, $5, 0, 0		# error
+	ext	$4, $5, 0, 1
+	ext	$4, $5, 31, 1
+	ext	$4, $5, 31, 2		# error
+
+	# ins constraint: 0 <= pos < 32
+	ins	$4, $5, -1, 1		# error
+	ins	$4, $5, 0, 1
+	ins	$4, $5, 31, 1
+	ins	$4, $5, 32, 1		# error
+
+	# ins constraint: 0 < size <= 32
+	ins	$4, $5, 0, 0		# error
+	ins	$4, $5, 0, 1
+	ins	$4, $5, 0, 32
+	ins	$4, $5, 0, 33		# error
+
+	# ins constraint: 0 < (pos+size) <= 32
+	ins	$4, $5, 0, 0		# error
+	ins	$4, $5, 0, 1
+	ins	$4, $5, 31, 1
+	ins	$4, $5, 31, 2		# error
+
+      # FP register checks.
+      #
+      # Even registers are supported w/ 32-bit FPU, odd
+      # registers supported only for 64-bit FPU.
+      # This file tests 32-bit FPU.
+     
+	mfhc1	$17, $f0
+
+	mthc1	$17, $f0
+
+# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
+	.space  8
diff --git a/gas/testsuite/gas/mips/mipsr6@mips32r2.d b/gas/testsuite/gas/mips/mipsr6@mips32r2.d
new file mode 100644
index 00000000000..dbf680c8849
--- /dev/null
+++ b/gas/testsuite/gas/mips/mipsr6@mips32r2.d
@@ -0,0 +1,45 @@
+#objdump: -dr --prefix-addresses --show-raw-insn -M reg-names=numeric
+#name: MIPS MIPS32r2 non-fp instructions
+#as: -32
+#source: mips32r2.s
+
+# Check MIPS32 Release 2 (mips32r2) *non-fp* instruction assembly
+
+.*: +file format .*mips.*
+
+Disassembly of section .text:
+0+0000 <[^>]*> 000000c0 	ehb
+0+0004 <[^>]*> 7ca43980 	ext	\$4,\$5,0x6,0x8
+0+0008 <[^>]*> 7ca46984 	ins	\$4,\$5,0x6,0x8
+0+000c <[^>]*> 0100fc09 	jalr.hb	\$8
+0+0010 <[^>]*> 0120a409 	jalr.hb	\$20,\$9
+0+0014 <[^>]*> 01000409 	jr.hb	\$8
+0+0018 <[^>]*> 7c0a003b 	rdhwr	\$10,\$0
+0+001c <[^>]*> 7c0b083b 	rdhwr	\$11,\$1
+0+0020 <[^>]*> 7c0c103b 	rdhwr	\$12,\$2
+0+0024 <[^>]*> 7c0d183b 	rdhwr	\$13,\$3
+0+0028 <[^>]*> 7c0e203b 	rdhwr	\$14,\$4
+0+002c <[^>]*> 7c0f283b 	rdhwr	\$15,\$5
+0+0030 <[^>]*> 002acf02 	ror	\$25,\$10,0x1c
+0+0034 <[^>]*> 002ac902 	ror	\$25,\$10,0x4
+0+0038 <[^>]*> 0004c823 	negu	\$25,\$4
+0+003c <[^>]*> 032ac846 	rorv	\$25,\$10,\$25
+0+0040 <[^>]*> 008ac846 	rorv	\$25,\$10,\$4
+0+0044 <[^>]*> 008ac846 	rorv	\$25,\$10,\$4
+0+0048 <[^>]*> 7c073c20 	seb	\$7,\$7
+0+004c <[^>]*> 7c0a4420 	seb	\$8,\$10
+0+0050 <[^>]*> 7c073e20 	seh	\$7,\$7
+0+0054 <[^>]*> 7c0a4620 	seh	\$8,\$10
+0+0058 <[^>]*> 055f5555 	synci	21845\(\$10\)
+0+005c <[^>]*> 7c0738a0 	wsbh	\$7,\$7
+0+0060 <[^>]*> 7c0a40a0 	wsbh	\$8,\$10
+0+0064 <[^>]*> 41606000 	di
+0+0068 <[^>]*> 41606000 	di
+0+006c <[^>]*> 416a6000 	di	\$10
+0+0070 <[^>]*> 41606020 	ei
+0+0074 <[^>]*> 41606020 	ei
+0+0078 <[^>]*> 416a6020 	ei	\$10
+0+007c <[^>]*> 41595000 	rdpgpr	\$10,\$25
+0+0080 <[^>]*> 41d95000 	wrpgpr	\$10,\$25
+0+0084 <[^>]*> 00000140 	pause
+	...
diff --git a/gas/testsuite/gas/mips/mipsr6@mips4-fp.d b/gas/testsuite/gas/mips/mipsr6@mips4-fp.d
new file mode 100644
index 00000000000..a81a4233c9f
--- /dev/null
+++ b/gas/testsuite/gas/mips/mipsr6@mips4-fp.d
@@ -0,0 +1,13 @@
+#objdump: -dr --prefix-addresses
+#name: MIPS mips4 fp
+
+# Test mips4 fp instructions.
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> recip.d	\$f4,\$f6
+[0-9a-f]+ <[^>]*> recip.s	\$f4,\$f6
+[0-9a-f]+ <[^>]*> rsqrt.d	\$f4,\$f6
+[0-9a-f]+ <[^>]*> rsqrt.s	\$f4,\$f6
+	\.\.\.
diff --git a/gas/testsuite/gas/mips/mipsr6@mips4-fp.l b/gas/testsuite/gas/mips/mipsr6@mips4-fp.l
new file mode 100644
index 00000000000..85aef3db99c
--- /dev/null
+++ b/gas/testsuite/gas/mips/mipsr6@mips4-fp.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*:4: Error: opcode not supported on this processor: .* \(.*\) `recip.d \$f4,\$f6'
+.*:5: Error: opcode not supported on this processor: .* \(.*\) `recip.s \$f4,\$f6'
+.*:6: Error: opcode not supported on this processor: .* \(.*\) `rsqrt.d \$f4,\$f6'
+.*:7: Error: opcode not supported on this processor: .* \(.*\) `rsqrt.s \$f4,\$f6'
diff --git a/gas/testsuite/gas/mips/mipsr6@mips4-fp.s b/gas/testsuite/gas/mips/mipsr6@mips4-fp.s
new file mode 100644
index 00000000000..4d124e5327a
--- /dev/null
+++ b/gas/testsuite/gas/mips/mipsr6@mips4-fp.s
@@ -0,0 +1,11 @@
+# Source file used to test -mips4 fp instructions.
+
+text_label:
+	recip.d	$f4,$f6
+	recip.s	$f4,$f6
+	rsqrt.d	$f4,$f6
+	rsqrt.s	$f4,$f6
+
+# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
+	.align	2
+	.space	8
diff --git a/gas/testsuite/gas/mips/mipsr6@mips4.d b/gas/testsuite/gas/mips/mipsr6@mips4.d
new file mode 100644
index 00000000000..08b6d963b09
--- /dev/null
+++ b/gas/testsuite/gas/mips/mipsr6@mips4.d
@@ -0,0 +1,11 @@
+#objdump: -dr --prefix-addresses
+#name: MIPS mips4 non-fp
+#source: mips4.s
+
+# Test mips4 *non-fp* insturctions.
+
+.*: +file format .*mips.*
+
+Disassembly of section .text:
+0+0000 <[^>]*> pref	0x4,0\(a0\)
+	...
diff --git a/gas/testsuite/gas/mips/mipsr6@mips5-fp.d b/gas/testsuite/gas/mips/mipsr6@mips5-fp.d
new file mode 100644
index 00000000000..77244fb8501
--- /dev/null
+++ b/gas/testsuite/gas/mips/mipsr6@mips5-fp.d
@@ -0,0 +1,12 @@
+#objdump: -dr --prefix-addresses --show-raw-insn -M reg-names=numeric
+#name: MIPS mips5 instructions
+#stderr: mipsr6@mips5-fp.l
+
+# Check MIPS V instruction assembly
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+0+0000 <[^>]*> 46c09428 	cvt\.s\.pl	\$f16,\$f18
+0+0004 <[^>]*> 46c0a4a0 	cvt\.s\.pu	\$f18,\$f20
+	\.\.\.
diff --git a/gas/testsuite/gas/mips/mipsr6@mips5-fp.l b/gas/testsuite/gas/mips/mipsr6@mips5-fp.l
new file mode 100644
index 00000000000..927ff972720
--- /dev/null
+++ b/gas/testsuite/gas/mips/mipsr6@mips5-fp.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*:4: Warning: condition code register should be even for c.eq.ps, was 3
+.*:5: Warning: condition code register should be even for movf.ps, was 3
diff --git a/gas/testsuite/gas/mips/mipsr6@mips5-fp.s b/gas/testsuite/gas/mips/mipsr6@mips5-fp.s
new file mode 100644
index 00000000000..6bee111a4a4
--- /dev/null
+++ b/gas/testsuite/gas/mips/mipsr6@mips5-fp.s
@@ -0,0 +1,8 @@
+# Source file used to test -mips5 instructions.
+
+text_label:
+	cvt.s.pl	$f16, $f18
+	cvt.s.pu	$f18, $f20
+
+# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
+      .space  8
diff --git a/gas/testsuite/gas/mips/mipsr6@mips64.d b/gas/testsuite/gas/mips/mipsr6@mips64.d
new file mode 100644
index 00000000000..c9e732c4118
--- /dev/null
+++ b/gas/testsuite/gas/mips/mipsr6@mips64.d
@@ -0,0 +1,13 @@
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS MIPS64 instructions
+#as: -32
+#source: mips64.s
+
+# Check MIPS64 instruction assembly
+
+.*: +file format .*mips.*
+
+Disassembly of section .text:
+0+0000 <[^>]*> 00400853 	dclo	at,v0
+0+0004 <[^>]*> 00801852 	dclz	v1,a0
+#pass
diff --git a/gas/testsuite/gas/mips/mipsr6@msa-branch.d b/gas/testsuite/gas/mips/mipsr6@msa-branch.d
new file mode 100644
index 00000000000..34661455f5a
--- /dev/null
+++ b/gas/testsuite/gas/mips/mipsr6@msa-branch.d
@@ -0,0 +1,309 @@
+#objdump: -dr --prefix-addresses --show-raw-insn -Mmsa
+#name: MSA branch reorder
+#as: -32 -mmsa
+#source: msa-branch.s
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 7aa2081c 	fsune\.d	\$w0,\$w1,\$w2
+[0-9a-f]+ <[^>]*> 4700.... 	bz\.b	\$w0,[0-9a-f]+ <[^>]*>
+[	]*4: .*R_MIPS_PC16	test
+[0-9a-f]+ <[^>]*> 00000000 	nop
+[0-9a-f]+ <[^>]*> 4701.... 	bz\.b	\$w1,[0-9a-f]+ <[^>]*>
+[	]*c: .*R_MIPS_PC16	test
+[0-9a-f]+ <[^>]*> 7aa2081c 	fsune\.d	\$w0,\$w1,\$w2
+[0-9a-f]+ <[^>]*> 4702.... 	bz\.b	\$w2,[0-9a-f]+ <[^>]*>
+[	]*14: .*R_MIPS_PC16	test
+[0-9a-f]+ <[^>]*> 7aa2081c 	fsune\.d	\$w0,\$w1,\$w2
+[0-9a-f]+ <[^>]*> 46020800 	add\.s	\$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 4700.... 	bz\.b	\$w0,[0-9a-f]+ <[^>]*>
+[	]*20: .*R_MIPS_PC16	test
+[0-9a-f]+ <[^>]*> 00000000 	nop
+[0-9a-f]+ <[^>]*> 4701.... 	bz\.b	\$w1,[0-9a-f]+ <[^>]*>
+[	]*28: .*R_MIPS_PC16	test
+[0-9a-f]+ <[^>]*> 46020800 	add\.s	\$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 4702.... 	bz\.b	\$w2,[0-9a-f]+ <[^>]*>
+[	]*30: .*R_MIPS_PC16	test
+[0-9a-f]+ <[^>]*> 46020800 	add\.s	\$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 46241000 	add\.d	\$f0,\$f2,\$f4
+[0-9a-f]+ <[^>]*> 4700.... 	bz\.b	\$w0,[0-9a-f]+ <[^>]*>
+[	]*3c: .*R_MIPS_PC16	test
+[0-9a-f]+ <[^>]*> 00000000 	nop
+[0-9a-f]+ <[^>]*> 4701.... 	bz\.b	\$w1,[0-9a-f]+ <[^>]*>
+[	]*44: .*R_MIPS_PC16	test
+[0-9a-f]+ <[^>]*> 46241000 	add\.d	\$f0,\$f2,\$f4
+[0-9a-f]+ <[^>]*> 4702.... 	bz\.b	\$w2,[0-9a-f]+ <[^>]*>
+[	]*4c: .*R_MIPS_PC16	test
+[0-9a-f]+ <[^>]*> 46241000 	add\.d	\$f0,\$f2,\$f4
+[0-9a-f]+ <[^>]*> 7aa2081c 	fsune\.d	\$w0,\$w1,\$w2
+[0-9a-f]+ <[^>]*> 4720.... 	bz\.h	\$w0,[0-9a-f]+ <[^>]*>
+[	]*58: .*R_MIPS_PC16	test
+[0-9a-f]+ <[^>]*> 00000000 	nop
+[0-9a-f]+ <[^>]*> 4721.... 	bz\.h	\$w1,[0-9a-f]+ <[^>]*>
+[	]*60: .*R_MIPS_PC16	test
+[0-9a-f]+ <[^>]*> 7aa2081c 	fsune\.d	\$w0,\$w1,\$w2
+[0-9a-f]+ <[^>]*> 4722.... 	bz\.h	\$w2,[0-9a-f]+ <[^>]*>
+[	]*68: .*R_MIPS_PC16	test
+[0-9a-f]+ <[^>]*> 7aa2081c 	fsune\.d	\$w0,\$w1,\$w2
+[0-9a-f]+ <[^>]*> 46020800 	add\.s	\$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 4720.... 	bz\.h	\$w0,[0-9a-f]+ <[^>]*>
+[	]*74: .*R_MIPS_PC16	test
+[0-9a-f]+ <[^>]*> 00000000 	nop
+[0-9a-f]+ <[^>]*> 4721.... 	bz\.h	\$w1,[0-9a-f]+ <[^>]*>
+[	]*7c: .*R_MIPS_PC16	test
+[0-9a-f]+ <[^>]*> 46020800 	add\.s	\$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 4722.... 	bz\.h	\$w2,[0-9a-f]+ <[^>]*>
+[	]*84: .*R_MIPS_PC16	test
+[0-9a-f]+ <[^>]*> 46020800 	add\.s	\$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 46241000 	add\.d	\$f0,\$f2,\$f4
+[0-9a-f]+ <[^>]*> 4720.... 	bz\.h	\$w0,[0-9a-f]+ <[^>]*>
+[	]*90: .*R_MIPS_PC16	test
+[0-9a-f]+ <[^>]*> 00000000 	nop
+[0-9a-f]+ <[^>]*> 4721.... 	bz\.h	\$w1,[0-9a-f]+ <[^>]*>
+[	]*98: .*R_MIPS_PC16	test
+[0-9a-f]+ <[^>]*> 46241000 	add\.d	\$f0,\$f2,\$f4
+[0-9a-f]+ <[^>]*> 4722.... 	bz\.h	\$w2,[0-9a-f]+ <[^>]*>
+[	]*a0: .*R_MIPS_PC16	test
+[0-9a-f]+ <[^>]*> 46241000 	add\.d	\$f0,\$f2,\$f4
+[0-9a-f]+ <[^>]*> 7aa2081c 	fsune\.d	\$w0,\$w1,\$w2
+[0-9a-f]+ <[^>]*> 4740.... 	bz\.w	\$w0,[0-9a-f]+ <[^>]*>
+[	]*ac: .*R_MIPS_PC16	test
+[0-9a-f]+ <[^>]*> 00000000 	nop
+[0-9a-f]+ <[^>]*> 4741.... 	bz\.w	\$w1,[0-9a-f]+ <[^>]*>
+[	]*b4: .*R_MIPS_PC16	test
+[0-9a-f]+ <[^>]*> 7aa2081c 	fsune\.d	\$w0,\$w1,\$w2
+[0-9a-f]+ <[^>]*> 4742.... 	bz\.w	\$w2,[0-9a-f]+ <[^>]*>
+[	]*bc: .*R_MIPS_PC16	test
+[0-9a-f]+ <[^>]*> 7aa2081c 	fsune\.d	\$w0,\$w1,\$w2
+[0-9a-f]+ <[^>]*> 46020800 	add\.s	\$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 4740.... 	bz\.w	\$w0,[0-9a-f]+ <[^>]*>
+[	]*c8: .*R_MIPS_PC16	test
+[0-9a-f]+ <[^>]*> 00000000 	nop
+[0-9a-f]+ <[^>]*> 4741.... 	bz\.w	\$w1,[0-9a-f]+ <[^>]*>
+[	]*d0: .*R_MIPS_PC16	test
+[0-9a-f]+ <[^>]*> 46020800 	add\.s	\$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 4742.... 	bz\.w	\$w2,[0-9a-f]+ <[^>]*>
+[	]*d8: .*R_MIPS_PC16	test
+[0-9a-f]+ <[^>]*> 46020800 	add\.s	\$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 46241000 	add\.d	\$f0,\$f2,\$f4
+[0-9a-f]+ <[^>]*> 4740.... 	bz\.w	\$w0,[0-9a-f]+ <[^>]*>
+[	]*e4: .*R_MIPS_PC16	test
+[0-9a-f]+ <[^>]*> 00000000 	nop
+[0-9a-f]+ <[^>]*> 4741.... 	bz\.w	\$w1,[0-9a-f]+ <[^>]*>
+[	]*ec: .*R_MIPS_PC16	test
+[0-9a-f]+ <[^>]*> 46241000 	add\.d	\$f0,\$f2,\$f4
+[0-9a-f]+ <[^>]*> 4742.... 	bz\.w	\$w2,[0-9a-f]+ <[^>]*>
+[	]*f4: .*R_MIPS_PC16	test
+[0-9a-f]+ <[^>]*> 46241000 	add\.d	\$f0,\$f2,\$f4
+[0-9a-f]+ <[^>]*> 7aa2081c 	fsune\.d	\$w0,\$w1,\$w2
+[0-9a-f]+ <[^>]*> 4760.... 	bz\.d	\$w0,[0-9a-f]+ <[^>]*>
+[	]*100: .*R_MIPS_PC16	test
+[0-9a-f]+ <[^>]*> 00000000 	nop
+[0-9a-f]+ <[^>]*> 4761.... 	bz\.d	\$w1,[0-9a-f]+ <[^>]*>
+[	]*108: .*R_MIPS_PC16	test
+[0-9a-f]+ <[^>]*> 7aa2081c 	fsune\.d	\$w0,\$w1,\$w2
+[0-9a-f]+ <[^>]*> 4762.... 	bz\.d	\$w2,[0-9a-f]+ <[^>]*>
+[	]*110: .*R_MIPS_PC16	test
+[0-9a-f]+ <[^>]*> 7aa2081c 	fsune\.d	\$w0,\$w1,\$w2
+[0-9a-f]+ <[^>]*> 46020800 	add\.s	\$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 4760.... 	bz\.d	\$w0,[0-9a-f]+ <[^>]*>
+[	]*11c: .*R_MIPS_PC16	test
+[0-9a-f]+ <[^>]*> 00000000 	nop
+[0-9a-f]+ <[^>]*> 4761.... 	bz\.d	\$w1,[0-9a-f]+ <[^>]*>
+[	]*124: .*R_MIPS_PC16	test
+[0-9a-f]+ <[^>]*> 46020800 	add\.s	\$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 4762.... 	bz\.d	\$w2,[0-9a-f]+ <[^>]*>
+[	]*12c: .*R_MIPS_PC16	test
+[0-9a-f]+ <[^>]*> 46020800 	add\.s	\$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 46241000 	add\.d	\$f0,\$f2,\$f4
+[0-9a-f]+ <[^>]*> 4760.... 	bz\.d	\$w0,[0-9a-f]+ <[^>]*>
+[	]*138: .*R_MIPS_PC16	test
+[0-9a-f]+ <[^>]*> 00000000 	nop
+[0-9a-f]+ <[^>]*> 4761.... 	bz\.d	\$w1,[0-9a-f]+ <[^>]*>
+[	]*140: .*R_MIPS_PC16	test
+[0-9a-f]+ <[^>]*> 46241000 	add\.d	\$f0,\$f2,\$f4
+[0-9a-f]+ <[^>]*> 4762.... 	bz\.d	\$w2,[0-9a-f]+ <[^>]*>
+[	]*148: .*R_MIPS_PC16	test
+[0-9a-f]+ <[^>]*> 46241000 	add\.d	\$f0,\$f2,\$f4
+[0-9a-f]+ <[^>]*> 7aa2081c 	fsune\.d	\$w0,\$w1,\$w2
+[0-9a-f]+ <[^>]*> 4560.... 	bz\.v	\$w0,[0-9a-f]+ <[^>]*>
+[	]*154: .*R_MIPS_PC16	test
+[0-9a-f]+ <[^>]*> 00000000 	nop
+[0-9a-f]+ <[^>]*> 4561.... 	bz\.v	\$w1,[0-9a-f]+ <[^>]*>
+[	]*15c: .*R_MIPS_PC16	test
+[0-9a-f]+ <[^>]*> 7aa2081c 	fsune\.d	\$w0,\$w1,\$w2
+[0-9a-f]+ <[^>]*> 4562.... 	bz\.v	\$w2,[0-9a-f]+ <[^>]*>
+[	]*164: .*R_MIPS_PC16	test
+[0-9a-f]+ <[^>]*> 7aa2081c 	fsune\.d	\$w0,\$w1,\$w2
+[0-9a-f]+ <[^>]*> 46020800 	add\.s	\$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 4560.... 	bz\.v	\$w0,[0-9a-f]+ <[^>]*>
+[	]*170: .*R_MIPS_PC16	test
+[0-9a-f]+ <[^>]*> 00000000 	nop
+[0-9a-f]+ <[^>]*> 4561.... 	bz\.v	\$w1,[0-9a-f]+ <[^>]*>
+[	]*178: .*R_MIPS_PC16	test
+[0-9a-f]+ <[^>]*> 46020800 	add\.s	\$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 4562.... 	bz\.v	\$w2,[0-9a-f]+ <[^>]*>
+[	]*180: .*R_MIPS_PC16	test
+[0-9a-f]+ <[^>]*> 46020800 	add\.s	\$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 46241000 	add\.d	\$f0,\$f2,\$f4
+[0-9a-f]+ <[^>]*> 4560.... 	bz\.v	\$w0,[0-9a-f]+ <[^>]*>
+[	]*18c: .*R_MIPS_PC16	test
+[0-9a-f]+ <[^>]*> 00000000 	nop
+[0-9a-f]+ <[^>]*> 4561.... 	bz\.v	\$w1,[0-9a-f]+ <[^>]*>
+[	]*194: .*R_MIPS_PC16	test
+[0-9a-f]+ <[^>]*> 46241000 	add\.d	\$f0,\$f2,\$f4
+[0-9a-f]+ <[^>]*> 4562.... 	bz\.v	\$w2,[0-9a-f]+ <[^>]*>
+[	]*19c: .*R_MIPS_PC16	test
+[0-9a-f]+ <[^>]*> 46241000 	add\.d	\$f0,\$f2,\$f4
+[0-9a-f]+ <[^>]*> 7aa2081c 	fsune\.d	\$w0,\$w1,\$w2
+[0-9a-f]+ <[^>]*> 4780.... 	bnz\.b	\$w0,[0-9a-f]+ <[^>]*>
+[	]*1a8: .*R_MIPS_PC16	test
+[0-9a-f]+ <[^>]*> 00000000 	nop
+[0-9a-f]+ <[^>]*> 4781.... 	bnz\.b	\$w1,[0-9a-f]+ <[^>]*>
+[	]*1b0: .*R_MIPS_PC16	test
+[0-9a-f]+ <[^>]*> 7aa2081c 	fsune\.d	\$w0,\$w1,\$w2
+[0-9a-f]+ <[^>]*> 4782.... 	bnz\.b	\$w2,[0-9a-f]+ <[^>]*>
+[	]*1b8: .*R_MIPS_PC16	test
+[0-9a-f]+ <[^>]*> 7aa2081c 	fsune\.d	\$w0,\$w1,\$w2
+[0-9a-f]+ <[^>]*> 46020800 	add\.s	\$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 4780.... 	bnz\.b	\$w0,[0-9a-f]+ <[^>]*>
+[	]*1c4: .*R_MIPS_PC16	test
+[0-9a-f]+ <[^>]*> 00000000 	nop
+[0-9a-f]+ <[^>]*> 4781.... 	bnz\.b	\$w1,[0-9a-f]+ <[^>]*>
+[	]*1cc: .*R_MIPS_PC16	test
+[0-9a-f]+ <[^>]*> 46020800 	add\.s	\$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 4782.... 	bnz\.b	\$w2,[0-9a-f]+ <[^>]*>
+[	]*1d4: .*R_MIPS_PC16	test
+[0-9a-f]+ <[^>]*> 46020800 	add\.s	\$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 46241000 	add\.d	\$f0,\$f2,\$f4
+[0-9a-f]+ <[^>]*> 4780.... 	bnz\.b	\$w0,[0-9a-f]+ <[^>]*>
+[	]*1e0: .*R_MIPS_PC16	test
+[0-9a-f]+ <[^>]*> 00000000 	nop
+[0-9a-f]+ <[^>]*> 4781.... 	bnz\.b	\$w1,[0-9a-f]+ <[^>]*>
+[	]*1e8: .*R_MIPS_PC16	test
+[0-9a-f]+ <[^>]*> 46241000 	add\.d	\$f0,\$f2,\$f4
+[0-9a-f]+ <[^>]*> 4782.... 	bnz\.b	\$w2,[0-9a-f]+ <[^>]*>
+[	]*1f0: .*R_MIPS_PC16	test
+[0-9a-f]+ <[^>]*> 46241000 	add\.d	\$f0,\$f2,\$f4
+[0-9a-f]+ <[^>]*> 7aa2081c 	fsune\.d	\$w0,\$w1,\$w2
+[0-9a-f]+ <[^>]*> 47a0.... 	bnz\.h	\$w0,[0-9a-f]+ <[^>]*>
+[	]*1fc: .*R_MIPS_PC16	test
+[0-9a-f]+ <[^>]*> 00000000 	nop
+[0-9a-f]+ <[^>]*> 47a1.... 	bnz\.h	\$w1,[0-9a-f]+ <[^>]*>
+[	]*204: .*R_MIPS_PC16	test
+[0-9a-f]+ <[^>]*> 7aa2081c 	fsune\.d	\$w0,\$w1,\$w2
+[0-9a-f]+ <[^>]*> 47a2.... 	bnz\.h	\$w2,[0-9a-f]+ <[^>]*>
+[	]*20c: .*R_MIPS_PC16	test
+[0-9a-f]+ <[^>]*> 7aa2081c 	fsune\.d	\$w0,\$w1,\$w2
+[0-9a-f]+ <[^>]*> 46020800 	add\.s	\$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 47a0.... 	bnz\.h	\$w0,[0-9a-f]+ <[^>]*>
+[	]*218: .*R_MIPS_PC16	test
+[0-9a-f]+ <[^>]*> 00000000 	nop
+[0-9a-f]+ <[^>]*> 47a1.... 	bnz\.h	\$w1,[0-9a-f]+ <[^>]*>
+[	]*220: .*R_MIPS_PC16	test
+[0-9a-f]+ <[^>]*> 46020800 	add\.s	\$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 47a2.... 	bnz\.h	\$w2,[0-9a-f]+ <[^>]*>
+[	]*228: .*R_MIPS_PC16	test
+[0-9a-f]+ <[^>]*> 46020800 	add\.s	\$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 46241000 	add\.d	\$f0,\$f2,\$f4
+[0-9a-f]+ <[^>]*> 47a0.... 	bnz\.h	\$w0,[0-9a-f]+ <[^>]*>
+[	]*234: .*R_MIPS_PC16	test
+[0-9a-f]+ <[^>]*> 00000000 	nop
+[0-9a-f]+ <[^>]*> 47a1.... 	bnz\.h	\$w1,[0-9a-f]+ <[^>]*>
+[	]*23c: .*R_MIPS_PC16	test
+[0-9a-f]+ <[^>]*> 46241000 	add\.d	\$f0,\$f2,\$f4
+[0-9a-f]+ <[^>]*> 47a2.... 	bnz\.h	\$w2,[0-9a-f]+ <[^>]*>
+[	]*244: .*R_MIPS_PC16	test
+[0-9a-f]+ <[^>]*> 46241000 	add\.d	\$f0,\$f2,\$f4
+[0-9a-f]+ <[^>]*> 7aa2081c 	fsune\.d	\$w0,\$w1,\$w2
+[0-9a-f]+ <[^>]*> 47c0.... 	bnz\.w	\$w0,[0-9a-f]+ <[^>]*>
+[	]*250: .*R_MIPS_PC16	test
+[0-9a-f]+ <[^>]*> 00000000 	nop
+[0-9a-f]+ <[^>]*> 47c1.... 	bnz\.w	\$w1,[0-9a-f]+ <[^>]*>
+[	]*258: .*R_MIPS_PC16	test
+[0-9a-f]+ <[^>]*> 7aa2081c 	fsune\.d	\$w0,\$w1,\$w2
+[0-9a-f]+ <[^>]*> 47c2.... 	bnz\.w	\$w2,[0-9a-f]+ <[^>]*>
+[	]*260: .*R_MIPS_PC16	test
+[0-9a-f]+ <[^>]*> 7aa2081c 	fsune\.d	\$w0,\$w1,\$w2
+[0-9a-f]+ <[^>]*> 46020800 	add\.s	\$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 47c0.... 	bnz\.w	\$w0,[0-9a-f]+ <[^>]*>
+[	]*26c: .*R_MIPS_PC16	test
+[0-9a-f]+ <[^>]*> 00000000 	nop
+[0-9a-f]+ <[^>]*> 47c1.... 	bnz\.w	\$w1,[0-9a-f]+ <[^>]*>
+[	]*274: .*R_MIPS_PC16	test
+[0-9a-f]+ <[^>]*> 46020800 	add\.s	\$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 47c2.... 	bnz\.w	\$w2,[0-9a-f]+ <[^>]*>
+[	]*27c: .*R_MIPS_PC16	test
+[0-9a-f]+ <[^>]*> 46020800 	add\.s	\$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 46241000 	add\.d	\$f0,\$f2,\$f4
+[0-9a-f]+ <[^>]*> 47c0.... 	bnz\.w	\$w0,[0-9a-f]+ <[^>]*>
+[	]*288: .*R_MIPS_PC16	test
+[0-9a-f]+ <[^>]*> 00000000 	nop
+[0-9a-f]+ <[^>]*> 47c1.... 	bnz\.w	\$w1,[0-9a-f]+ <[^>]*>
+[	]*290: .*R_MIPS_PC16	test
+[0-9a-f]+ <[^>]*> 46241000 	add\.d	\$f0,\$f2,\$f4
+[0-9a-f]+ <[^>]*> 47c2.... 	bnz\.w	\$w2,[0-9a-f]+ <[^>]*>
+[	]*298: .*R_MIPS_PC16	test
+[0-9a-f]+ <[^>]*> 46241000 	add\.d	\$f0,\$f2,\$f4
+[0-9a-f]+ <[^>]*> 7aa2081c 	fsune\.d	\$w0,\$w1,\$w2
+[0-9a-f]+ <[^>]*> 47e0.... 	bnz\.d	\$w0,[0-9a-f]+ <[^>]*>
+[	]*2a4: .*R_MIPS_PC16	test
+[0-9a-f]+ <[^>]*> 00000000 	nop
+[0-9a-f]+ <[^>]*> 47e1.... 	bnz\.d	\$w1,[0-9a-f]+ <[^>]*>
+[	]*2ac: .*R_MIPS_PC16	test
+[0-9a-f]+ <[^>]*> 7aa2081c 	fsune\.d	\$w0,\$w1,\$w2
+[0-9a-f]+ <[^>]*> 47e2.... 	bnz\.d	\$w2,[0-9a-f]+ <[^>]*>
+[	]*2b4: .*R_MIPS_PC16	test
+[0-9a-f]+ <[^>]*> 7aa2081c 	fsune\.d	\$w0,\$w1,\$w2
+[0-9a-f]+ <[^>]*> 46020800 	add\.s	\$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 47e0.... 	bnz\.d	\$w0,[0-9a-f]+ <[^>]*>
+[	]*2c0: .*R_MIPS_PC16	test
+[0-9a-f]+ <[^>]*> 00000000 	nop
+[0-9a-f]+ <[^>]*> 47e1.... 	bnz\.d	\$w1,[0-9a-f]+ <[^>]*>
+[	]*2c8: .*R_MIPS_PC16	test
+[0-9a-f]+ <[^>]*> 46020800 	add\.s	\$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 47e2.... 	bnz\.d	\$w2,[0-9a-f]+ <[^>]*>
+[	]*2d0: .*R_MIPS_PC16	test
+[0-9a-f]+ <[^>]*> 46020800 	add\.s	\$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 46241000 	add\.d	\$f0,\$f2,\$f4
+[0-9a-f]+ <[^>]*> 47e0.... 	bnz\.d	\$w0,[0-9a-f]+ <[^>]*>
+[	]*2dc: .*R_MIPS_PC16	test
+[0-9a-f]+ <[^>]*> 00000000 	nop
+[0-9a-f]+ <[^>]*> 47e1.... 	bnz\.d	\$w1,[0-9a-f]+ <[^>]*>
+[	]*2e4: .*R_MIPS_PC16	test
+[0-9a-f]+ <[^>]*> 46241000 	add\.d	\$f0,\$f2,\$f4
+[0-9a-f]+ <[^>]*> 47e2.... 	bnz\.d	\$w2,[0-9a-f]+ <[^>]*>
+[	]*2ec: .*R_MIPS_PC16	test
+[0-9a-f]+ <[^>]*> 46241000 	add\.d	\$f0,\$f2,\$f4
+[0-9a-f]+ <[^>]*> 7aa2081c 	fsune\.d	\$w0,\$w1,\$w2
+[0-9a-f]+ <[^>]*> 45e0.... 	bnz\.v	\$w0,[0-9a-f]+ <[^>]*>
+[	]*2f8: .*R_MIPS_PC16	test
+[0-9a-f]+ <[^>]*> 00000000 	nop
+[0-9a-f]+ <[^>]*> 45e1.... 	bnz\.v	\$w1,[0-9a-f]+ <[^>]*>
+[	]*300: .*R_MIPS_PC16	test
+[0-9a-f]+ <[^>]*> 7aa2081c 	fsune\.d	\$w0,\$w1,\$w2
+[0-9a-f]+ <[^>]*> 45e2.... 	bnz\.v	\$w2,[0-9a-f]+ <[^>]*>
+[	]*308: .*R_MIPS_PC16	test
+[0-9a-f]+ <[^>]*> 7aa2081c 	fsune\.d	\$w0,\$w1,\$w2
+[0-9a-f]+ <[^>]*> 46020800 	add\.s	\$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 45e0.... 	bnz\.v	\$w0,[0-9a-f]+ <[^>]*>
+[	]*314: .*R_MIPS_PC16	test
+[0-9a-f]+ <[^>]*> 00000000 	nop
+[0-9a-f]+ <[^>]*> 45e1.... 	bnz\.v	\$w1,[0-9a-f]+ <[^>]*>
+[	]*31c: .*R_MIPS_PC16	test
+[0-9a-f]+ <[^>]*> 46020800 	add\.s	\$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 45e2.... 	bnz\.v	\$w2,[0-9a-f]+ <[^>]*>
+[	]*324: .*R_MIPS_PC16	test
+[0-9a-f]+ <[^>]*> 46020800 	add\.s	\$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 46241000 	add\.d	\$f0,\$f2,\$f4
+[0-9a-f]+ <[^>]*> 45e0.... 	bnz\.v	\$w0,[0-9a-f]+ <[^>]*>
+[	]*330: .*R_MIPS_PC16	test
+[0-9a-f]+ <[^>]*> 00000000 	nop
+[0-9a-f]+ <[^>]*> 45e1.... 	bnz\.v	\$w1,[0-9a-f]+ <[^>]*>
+[	]*338: .*R_MIPS_PC16	test
+[0-9a-f]+ <[^>]*> 46241000 	add\.d	\$f0,\$f2,\$f4
+[0-9a-f]+ <[^>]*> 45e2.... 	bnz\.v	\$w2,[0-9a-f]+ <[^>]*>
+[	]*340: .*R_MIPS_PC16	test
+[0-9a-f]+ <[^>]*> 46241000 	add\.d	\$f0,\$f2,\$f4
+	\.\.\.
diff --git a/gas/testsuite/gas/mips/mipsr6@msa.d b/gas/testsuite/gas/mips/mipsr6@msa.d
new file mode 100644
index 00000000000..4471c956b6a
--- /dev/null
+++ b/gas/testsuite/gas/mips/mipsr6@msa.d
@@ -0,0 +1,788 @@
+#objdump: -dr --prefix-addresses --show-raw-insn -Mmsa
+#name: MSA instructions
+#as: -32 -mmsa --defsym insn_log2=2
+#source: msa.s
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 7802080d 	sll\.b	\$w0,\$w1,\$w2
+[0-9a-f]+ <[^>]*> 782520cd 	sll\.h	\$w3,\$w4,\$w5
+[0-9a-f]+ <[^>]*> 7848398d 	sll\.w	\$w6,\$w7,\$w8
+[0-9a-f]+ <[^>]*> 786b524d 	sll\.d	\$w9,\$w10,\$w11
+[0-9a-f]+ <[^>]*> 78706b09 	slli\.b	\$w12,\$w13,0x0
+[0-9a-f]+ <[^>]*> 78777b89 	slli\.b	\$w14,\$w15,0x7
+[0-9a-f]+ <[^>]*> 78608c09 	slli\.h	\$w16,\$w17,0x0
+[0-9a-f]+ <[^>]*> 786f9c89 	slli\.h	\$w18,\$w19,0xf
+[0-9a-f]+ <[^>]*> 7840ad09 	slli\.w	\$w20,\$w21,0x0
+[0-9a-f]+ <[^>]*> 785fbd89 	slli\.w	\$w22,\$w23,0x1f
+[0-9a-f]+ <[^>]*> 7800ce09 	slli\.d	\$w24,\$w25,0x0
+[0-9a-f]+ <[^>]*> 783fde89 	slli\.d	\$w26,\$w27,0x3f
+[0-9a-f]+ <[^>]*> 789eef0d 	sra\.b	\$w28,\$w29,\$w30
+[0-9a-f]+ <[^>]*> 78a107cd 	sra\.h	\$w31,\$w0,\$w1
+[0-9a-f]+ <[^>]*> 78c4188d 	sra\.w	\$w2,\$w3,\$w4
+[0-9a-f]+ <[^>]*> 78e7314d 	sra\.d	\$w5,\$w6,\$w7
+[0-9a-f]+ <[^>]*> 78f04a09 	srai\.b	\$w8,\$w9,0x0
+[0-9a-f]+ <[^>]*> 78f75a89 	srai\.b	\$w10,\$w11,0x7
+[0-9a-f]+ <[^>]*> 78e06b09 	srai\.h	\$w12,\$w13,0x0
+[0-9a-f]+ <[^>]*> 78ef7b89 	srai\.h	\$w14,\$w15,0xf
+[0-9a-f]+ <[^>]*> 78c08c09 	srai\.w	\$w16,\$w17,0x0
+[0-9a-f]+ <[^>]*> 78df9c89 	srai\.w	\$w18,\$w19,0x1f
+[0-9a-f]+ <[^>]*> 7880ad09 	srai\.d	\$w20,\$w21,0x0
+[0-9a-f]+ <[^>]*> 78bfbd89 	srai\.d	\$w22,\$w23,0x3f
+[0-9a-f]+ <[^>]*> 791ace0d 	srl\.b	\$w24,\$w25,\$w26
+[0-9a-f]+ <[^>]*> 793de6cd 	srl\.h	\$w27,\$w28,\$w29
+[0-9a-f]+ <[^>]*> 7940ff8d 	srl\.w	\$w30,\$w31,\$w0
+[0-9a-f]+ <[^>]*> 7963104d 	srl\.d	\$w1,\$w2,\$w3
+[0-9a-f]+ <[^>]*> 79702909 	srli\.b	\$w4,\$w5,0x0
+[0-9a-f]+ <[^>]*> 79773989 	srli\.b	\$w6,\$w7,0x7
+[0-9a-f]+ <[^>]*> 79604a09 	srli\.h	\$w8,\$w9,0x0
+[0-9a-f]+ <[^>]*> 796f5a89 	srli\.h	\$w10,\$w11,0xf
+[0-9a-f]+ <[^>]*> 79406b09 	srli\.w	\$w12,\$w13,0x0
+[0-9a-f]+ <[^>]*> 795f7b89 	srli\.w	\$w14,\$w15,0x1f
+[0-9a-f]+ <[^>]*> 79008c09 	srli\.d	\$w16,\$w17,0x0
+[0-9a-f]+ <[^>]*> 793f9c89 	srli\.d	\$w18,\$w19,0x3f
+[0-9a-f]+ <[^>]*> 7996ad0d 	bclr\.b	\$w20,\$w21,\$w22
+[0-9a-f]+ <[^>]*> 79b9c5cd 	bclr\.h	\$w23,\$w24,\$w25
+[0-9a-f]+ <[^>]*> 79dcde8d 	bclr\.w	\$w26,\$w27,\$w28
+[0-9a-f]+ <[^>]*> 79fff74d 	bclr\.d	\$w29,\$w30,\$w31
+[0-9a-f]+ <[^>]*> 79f00809 	bclri\.b	\$w0,\$w1,0x0
+[0-9a-f]+ <[^>]*> 79f71889 	bclri\.b	\$w2,\$w3,0x7
+[0-9a-f]+ <[^>]*> 79e02909 	bclri\.h	\$w4,\$w5,0x0
+[0-9a-f]+ <[^>]*> 79ef3989 	bclri\.h	\$w6,\$w7,0xf
+[0-9a-f]+ <[^>]*> 79c04a09 	bclri\.w	\$w8,\$w9,0x0
+[0-9a-f]+ <[^>]*> 79df5a89 	bclri\.w	\$w10,\$w11,0x1f
+[0-9a-f]+ <[^>]*> 79806b09 	bclri\.d	\$w12,\$w13,0x0
+[0-9a-f]+ <[^>]*> 79bf7b89 	bclri\.d	\$w14,\$w15,0x3f
+[0-9a-f]+ <[^>]*> 7a128c0d 	bset\.b	\$w16,\$w17,\$w18
+[0-9a-f]+ <[^>]*> 7a35a4cd 	bset\.h	\$w19,\$w20,\$w21
+[0-9a-f]+ <[^>]*> 7a58bd8d 	bset\.w	\$w22,\$w23,\$w24
+[0-9a-f]+ <[^>]*> 7a7bd64d 	bset\.d	\$w25,\$w26,\$w27
+[0-9a-f]+ <[^>]*> 7a70ef09 	bseti\.b	\$w28,\$w29,0x0
+[0-9a-f]+ <[^>]*> 7a77ff89 	bseti\.b	\$w30,\$w31,0x7
+[0-9a-f]+ <[^>]*> 7a600809 	bseti\.h	\$w0,\$w1,0x0
+[0-9a-f]+ <[^>]*> 7a6f1889 	bseti\.h	\$w2,\$w3,0xf
+[0-9a-f]+ <[^>]*> 7a402909 	bseti\.w	\$w4,\$w5,0x0
+[0-9a-f]+ <[^>]*> 7a5f3989 	bseti\.w	\$w6,\$w7,0x1f
+[0-9a-f]+ <[^>]*> 7a004a09 	bseti\.d	\$w8,\$w9,0x0
+[0-9a-f]+ <[^>]*> 7a3f5a89 	bseti\.d	\$w10,\$w11,0x3f
+[0-9a-f]+ <[^>]*> 7a8e6b0d 	bneg\.b	\$w12,\$w13,\$w14
+[0-9a-f]+ <[^>]*> 7ab183cd 	bneg\.h	\$w15,\$w16,\$w17
+[0-9a-f]+ <[^>]*> 7ad49c8d 	bneg\.w	\$w18,\$w19,\$w20
+[0-9a-f]+ <[^>]*> 7af7b54d 	bneg\.d	\$w21,\$w22,\$w23
+[0-9a-f]+ <[^>]*> 7af0ce09 	bnegi\.b	\$w24,\$w25,0x0
+[0-9a-f]+ <[^>]*> 7af7de89 	bnegi\.b	\$w26,\$w27,0x7
+[0-9a-f]+ <[^>]*> 7ae0ef09 	bnegi\.h	\$w28,\$w29,0x0
+[0-9a-f]+ <[^>]*> 7aefff89 	bnegi\.h	\$w30,\$w31,0xf
+[0-9a-f]+ <[^>]*> 7ac00809 	bnegi\.w	\$w0,\$w1,0x0
+[0-9a-f]+ <[^>]*> 7adf1889 	bnegi\.w	\$w2,\$w3,0x1f
+[0-9a-f]+ <[^>]*> 7a802909 	bnegi\.d	\$w4,\$w5,0x0
+[0-9a-f]+ <[^>]*> 7abf3989 	bnegi\.d	\$w6,\$w7,0x3f
+[0-9a-f]+ <[^>]*> 7b0a4a0d 	binsl\.b	\$w8,\$w9,\$w10
+[0-9a-f]+ <[^>]*> 7b2d62cd 	binsl\.h	\$w11,\$w12,\$w13
+[0-9a-f]+ <[^>]*> 7b507b8d 	binsl\.w	\$w14,\$w15,\$w16
+[0-9a-f]+ <[^>]*> 7b73944d 	binsl\.d	\$w17,\$w18,\$w19
+[0-9a-f]+ <[^>]*> 7b70ad09 	binsli\.b	\$w20,\$w21,0x0
+[0-9a-f]+ <[^>]*> 7b77bd89 	binsli\.b	\$w22,\$w23,0x7
+[0-9a-f]+ <[^>]*> 7b60ce09 	binsli\.h	\$w24,\$w25,0x0
+[0-9a-f]+ <[^>]*> 7b6fde89 	binsli\.h	\$w26,\$w27,0xf
+[0-9a-f]+ <[^>]*> 7b40ef09 	binsli\.w	\$w28,\$w29,0x0
+[0-9a-f]+ <[^>]*> 7b5fff89 	binsli\.w	\$w30,\$w31,0x1f
+[0-9a-f]+ <[^>]*> 7b000809 	binsli\.d	\$w0,\$w1,0x0
+[0-9a-f]+ <[^>]*> 7b3f1889 	binsli\.d	\$w2,\$w3,0x3f
+[0-9a-f]+ <[^>]*> 7b86290d 	binsr\.b	\$w4,\$w5,\$w6
+[0-9a-f]+ <[^>]*> 7ba941cd 	binsr\.h	\$w7,\$w8,\$w9
+[0-9a-f]+ <[^>]*> 7bcc5a8d 	binsr\.w	\$w10,\$w11,\$w12
+[0-9a-f]+ <[^>]*> 7bef734d 	binsr\.d	\$w13,\$w14,\$w15
+[0-9a-f]+ <[^>]*> 7bf08c09 	binsri\.b	\$w16,\$w17,0x0
+[0-9a-f]+ <[^>]*> 7bf79c89 	binsri\.b	\$w18,\$w19,0x7
+[0-9a-f]+ <[^>]*> 7be0ad09 	binsri\.h	\$w20,\$w21,0x0
+[0-9a-f]+ <[^>]*> 7befbd89 	binsri\.h	\$w22,\$w23,0xf
+[0-9a-f]+ <[^>]*> 7bc0ce09 	binsri\.w	\$w24,\$w25,0x0
+[0-9a-f]+ <[^>]*> 7bdfde89 	binsri\.w	\$w26,\$w27,0x1f
+[0-9a-f]+ <[^>]*> 7b80ef09 	binsri\.d	\$w28,\$w29,0x0
+[0-9a-f]+ <[^>]*> 7bbfff89 	binsri\.d	\$w30,\$w31,0x3f
+[0-9a-f]+ <[^>]*> 7802080e 	addv\.b	\$w0,\$w1,\$w2
+[0-9a-f]+ <[^>]*> 782520ce 	addv\.h	\$w3,\$w4,\$w5
+[0-9a-f]+ <[^>]*> 7848398e 	addv\.w	\$w6,\$w7,\$w8
+[0-9a-f]+ <[^>]*> 786b524e 	addv\.d	\$w9,\$w10,\$w11
+[0-9a-f]+ <[^>]*> 78006b06 	addvi\.b	\$w12,\$w13,0
+[0-9a-f]+ <[^>]*> 781f7b86 	addvi\.b	\$w14,\$w15,31
+[0-9a-f]+ <[^>]*> 78208c06 	addvi\.h	\$w16,\$w17,0
+[0-9a-f]+ <[^>]*> 783f9c86 	addvi\.h	\$w18,\$w19,31
+[0-9a-f]+ <[^>]*> 7840ad06 	addvi\.w	\$w20,\$w21,0
+[0-9a-f]+ <[^>]*> 785fbd86 	addvi\.w	\$w22,\$w23,31
+[0-9a-f]+ <[^>]*> 7860ce06 	addvi\.d	\$w24,\$w25,0
+[0-9a-f]+ <[^>]*> 787fde86 	addvi\.d	\$w26,\$w27,31
+[0-9a-f]+ <[^>]*> 789eef0e 	subv\.b	\$w28,\$w29,\$w30
+[0-9a-f]+ <[^>]*> 78a107ce 	subv\.h	\$w31,\$w0,\$w1
+[0-9a-f]+ <[^>]*> 78c4188e 	subv\.w	\$w2,\$w3,\$w4
+[0-9a-f]+ <[^>]*> 78e7314e 	subv\.d	\$w5,\$w6,\$w7
+[0-9a-f]+ <[^>]*> 78804a06 	subvi\.b	\$w8,\$w9,0
+[0-9a-f]+ <[^>]*> 789f5a86 	subvi\.b	\$w10,\$w11,31
+[0-9a-f]+ <[^>]*> 78a06b06 	subvi\.h	\$w12,\$w13,0
+[0-9a-f]+ <[^>]*> 78bf7b86 	subvi\.h	\$w14,\$w15,31
+[0-9a-f]+ <[^>]*> 78c08c06 	subvi\.w	\$w16,\$w17,0
+[0-9a-f]+ <[^>]*> 78df9c86 	subvi\.w	\$w18,\$w19,31
+[0-9a-f]+ <[^>]*> 78e0ad06 	subvi\.d	\$w20,\$w21,0
+[0-9a-f]+ <[^>]*> 78ffbd86 	subvi\.d	\$w22,\$w23,31
+[0-9a-f]+ <[^>]*> 791ace0e 	max_s\.b	\$w24,\$w25,\$w26
+[0-9a-f]+ <[^>]*> 793de6ce 	max_s\.h	\$w27,\$w28,\$w29
+[0-9a-f]+ <[^>]*> 7940ff8e 	max_s\.w	\$w30,\$w31,\$w0
+[0-9a-f]+ <[^>]*> 7963104e 	max_s\.d	\$w1,\$w2,\$w3
+[0-9a-f]+ <[^>]*> 79102906 	maxi_s\.b	\$w4,\$w5,-16
+[0-9a-f]+ <[^>]*> 790f3986 	maxi_s\.b	\$w6,\$w7,15
+[0-9a-f]+ <[^>]*> 79304a06 	maxi_s\.h	\$w8,\$w9,-16
+[0-9a-f]+ <[^>]*> 792f5a86 	maxi_s\.h	\$w10,\$w11,15
+[0-9a-f]+ <[^>]*> 79506b06 	maxi_s\.w	\$w12,\$w13,-16
+[0-9a-f]+ <[^>]*> 794f7b86 	maxi_s\.w	\$w14,\$w15,15
+[0-9a-f]+ <[^>]*> 79708c06 	maxi_s\.d	\$w16,\$w17,-16
+[0-9a-f]+ <[^>]*> 796f9c86 	maxi_s\.d	\$w18,\$w19,15
+[0-9a-f]+ <[^>]*> 7996ad0e 	max_u\.b	\$w20,\$w21,\$w22
+[0-9a-f]+ <[^>]*> 79b9c5ce 	max_u\.h	\$w23,\$w24,\$w25
+[0-9a-f]+ <[^>]*> 79dcde8e 	max_u\.w	\$w26,\$w27,\$w28
+[0-9a-f]+ <[^>]*> 79fff74e 	max_u\.d	\$w29,\$w30,\$w31
+[0-9a-f]+ <[^>]*> 79800806 	maxi_u\.b	\$w0,\$w1,0
+[0-9a-f]+ <[^>]*> 799f1886 	maxi_u\.b	\$w2,\$w3,31
+[0-9a-f]+ <[^>]*> 79a02906 	maxi_u\.h	\$w4,\$w5,0
+[0-9a-f]+ <[^>]*> 79bf3986 	maxi_u\.h	\$w6,\$w7,31
+[0-9a-f]+ <[^>]*> 79c04a06 	maxi_u\.w	\$w8,\$w9,0
+[0-9a-f]+ <[^>]*> 79df5a86 	maxi_u\.w	\$w10,\$w11,31
+[0-9a-f]+ <[^>]*> 79e06b06 	maxi_u\.d	\$w12,\$w13,0
+[0-9a-f]+ <[^>]*> 79ff7b86 	maxi_u\.d	\$w14,\$w15,31
+[0-9a-f]+ <[^>]*> 7a128c0e 	min_s\.b	\$w16,\$w17,\$w18
+[0-9a-f]+ <[^>]*> 7a35a4ce 	min_s\.h	\$w19,\$w20,\$w21
+[0-9a-f]+ <[^>]*> 7a58bd8e 	min_s\.w	\$w22,\$w23,\$w24
+[0-9a-f]+ <[^>]*> 7a7bd64e 	min_s\.d	\$w25,\$w26,\$w27
+[0-9a-f]+ <[^>]*> 7a10ef06 	mini_s\.b	\$w28,\$w29,-16
+[0-9a-f]+ <[^>]*> 7a0fff86 	mini_s\.b	\$w30,\$w31,15
+[0-9a-f]+ <[^>]*> 7a300806 	mini_s\.h	\$w0,\$w1,-16
+[0-9a-f]+ <[^>]*> 7a2f1886 	mini_s\.h	\$w2,\$w3,15
+[0-9a-f]+ <[^>]*> 7a502906 	mini_s\.w	\$w4,\$w5,-16
+[0-9a-f]+ <[^>]*> 7a4f3986 	mini_s\.w	\$w6,\$w7,15
+[0-9a-f]+ <[^>]*> 7a704a06 	mini_s\.d	\$w8,\$w9,-16
+[0-9a-f]+ <[^>]*> 7a6f5a86 	mini_s\.d	\$w10,\$w11,15
+[0-9a-f]+ <[^>]*> 7a8e6b0e 	min_u\.b	\$w12,\$w13,\$w14
+[0-9a-f]+ <[^>]*> 7ab183ce 	min_u\.h	\$w15,\$w16,\$w17
+[0-9a-f]+ <[^>]*> 7ad49c8e 	min_u\.w	\$w18,\$w19,\$w20
+[0-9a-f]+ <[^>]*> 7af7b54e 	min_u\.d	\$w21,\$w22,\$w23
+[0-9a-f]+ <[^>]*> 7a80ce06 	mini_u\.b	\$w24,\$w25,0
+[0-9a-f]+ <[^>]*> 7a9fde86 	mini_u\.b	\$w26,\$w27,31
+[0-9a-f]+ <[^>]*> 7aa0ef06 	mini_u\.h	\$w28,\$w29,0
+[0-9a-f]+ <[^>]*> 7abfff86 	mini_u\.h	\$w30,\$w31,31
+[0-9a-f]+ <[^>]*> 7ac00806 	mini_u\.w	\$w0,\$w1,0
+[0-9a-f]+ <[^>]*> 7adf1886 	mini_u\.w	\$w2,\$w3,31
+[0-9a-f]+ <[^>]*> 7ae02906 	mini_u\.d	\$w4,\$w5,0
+[0-9a-f]+ <[^>]*> 7aff3986 	mini_u\.d	\$w6,\$w7,31
+[0-9a-f]+ <[^>]*> 7b0a4a0e 	max_a\.b	\$w8,\$w9,\$w10
+[0-9a-f]+ <[^>]*> 7b2d62ce 	max_a\.h	\$w11,\$w12,\$w13
+[0-9a-f]+ <[^>]*> 7b507b8e 	max_a\.w	\$w14,\$w15,\$w16
+[0-9a-f]+ <[^>]*> 7b73944e 	max_a\.d	\$w17,\$w18,\$w19
+[0-9a-f]+ <[^>]*> 7b96ad0e 	min_a\.b	\$w20,\$w21,\$w22
+[0-9a-f]+ <[^>]*> 7bb9c5ce 	min_a\.h	\$w23,\$w24,\$w25
+[0-9a-f]+ <[^>]*> 7bdcde8e 	min_a\.w	\$w26,\$w27,\$w28
+[0-9a-f]+ <[^>]*> 7bfff74e 	min_a\.d	\$w29,\$w30,\$w31
+[0-9a-f]+ <[^>]*> 7802080f 	ceq\.b	\$w0,\$w1,\$w2
+[0-9a-f]+ <[^>]*> 782520cf 	ceq\.h	\$w3,\$w4,\$w5
+[0-9a-f]+ <[^>]*> 7848398f 	ceq\.w	\$w6,\$w7,\$w8
+[0-9a-f]+ <[^>]*> 786b524f 	ceq\.d	\$w9,\$w10,\$w11
+[0-9a-f]+ <[^>]*> 78106b07 	ceqi\.b	\$w12,\$w13,-16
+[0-9a-f]+ <[^>]*> 780f7b87 	ceqi\.b	\$w14,\$w15,15
+[0-9a-f]+ <[^>]*> 78308c07 	ceqi\.h	\$w16,\$w17,-16
+[0-9a-f]+ <[^>]*> 782f9c87 	ceqi\.h	\$w18,\$w19,15
+[0-9a-f]+ <[^>]*> 7850ad07 	ceqi\.w	\$w20,\$w21,-16
+[0-9a-f]+ <[^>]*> 784fbd87 	ceqi\.w	\$w22,\$w23,15
+[0-9a-f]+ <[^>]*> 7870ce07 	ceqi\.d	\$w24,\$w25,-16
+[0-9a-f]+ <[^>]*> 786fde87 	ceqi\.d	\$w26,\$w27,15
+[0-9a-f]+ <[^>]*> 791eef0f 	clt_s\.b	\$w28,\$w29,\$w30
+[0-9a-f]+ <[^>]*> 792107cf 	clt_s\.h	\$w31,\$w0,\$w1
+[0-9a-f]+ <[^>]*> 7944188f 	clt_s\.w	\$w2,\$w3,\$w4
+[0-9a-f]+ <[^>]*> 7967314f 	clt_s\.d	\$w5,\$w6,\$w7
+[0-9a-f]+ <[^>]*> 79104a07 	clti_s\.b	\$w8,\$w9,-16
+[0-9a-f]+ <[^>]*> 790f5a87 	clti_s\.b	\$w10,\$w11,15
+[0-9a-f]+ <[^>]*> 79306b07 	clti_s\.h	\$w12,\$w13,-16
+[0-9a-f]+ <[^>]*> 792f7b87 	clti_s\.h	\$w14,\$w15,15
+[0-9a-f]+ <[^>]*> 79508c07 	clti_s\.w	\$w16,\$w17,-16
+[0-9a-f]+ <[^>]*> 794f9c87 	clti_s\.w	\$w18,\$w19,15
+[0-9a-f]+ <[^>]*> 7970ad07 	clti_s\.d	\$w20,\$w21,-16
+[0-9a-f]+ <[^>]*> 796fbd87 	clti_s\.d	\$w22,\$w23,15
+[0-9a-f]+ <[^>]*> 799ace0f 	clt_u\.b	\$w24,\$w25,\$w26
+[0-9a-f]+ <[^>]*> 79bde6cf 	clt_u\.h	\$w27,\$w28,\$w29
+[0-9a-f]+ <[^>]*> 79c0ff8f 	clt_u\.w	\$w30,\$w31,\$w0
+[0-9a-f]+ <[^>]*> 79e3104f 	clt_u\.d	\$w1,\$w2,\$w3
+[0-9a-f]+ <[^>]*> 79802907 	clti_u\.b	\$w4,\$w5,0
+[0-9a-f]+ <[^>]*> 799f3987 	clti_u\.b	\$w6,\$w7,31
+[0-9a-f]+ <[^>]*> 79a04a07 	clti_u\.h	\$w8,\$w9,0
+[0-9a-f]+ <[^>]*> 79bf5a87 	clti_u\.h	\$w10,\$w11,31
+[0-9a-f]+ <[^>]*> 79c06b07 	clti_u\.w	\$w12,\$w13,0
+[0-9a-f]+ <[^>]*> 79df7b87 	clti_u\.w	\$w14,\$w15,31
+[0-9a-f]+ <[^>]*> 79e08c07 	clti_u\.d	\$w16,\$w17,0
+[0-9a-f]+ <[^>]*> 79ff9c87 	clti_u\.d	\$w18,\$w19,31
+[0-9a-f]+ <[^>]*> 7a16ad0f 	cle_s\.b	\$w20,\$w21,\$w22
+[0-9a-f]+ <[^>]*> 7a39c5cf 	cle_s\.h	\$w23,\$w24,\$w25
+[0-9a-f]+ <[^>]*> 7a5cde8f 	cle_s\.w	\$w26,\$w27,\$w28
+[0-9a-f]+ <[^>]*> 7a7ff74f 	cle_s\.d	\$w29,\$w30,\$w31
+[0-9a-f]+ <[^>]*> 7a100807 	clei_s\.b	\$w0,\$w1,-16
+[0-9a-f]+ <[^>]*> 7a0f1887 	clei_s\.b	\$w2,\$w3,15
+[0-9a-f]+ <[^>]*> 7a302907 	clei_s\.h	\$w4,\$w5,-16
+[0-9a-f]+ <[^>]*> 7a2f3987 	clei_s\.h	\$w6,\$w7,15
+[0-9a-f]+ <[^>]*> 7a504a07 	clei_s\.w	\$w8,\$w9,-16
+[0-9a-f]+ <[^>]*> 7a4f5a87 	clei_s\.w	\$w10,\$w11,15
+[0-9a-f]+ <[^>]*> 7a706b07 	clei_s\.d	\$w12,\$w13,-16
+[0-9a-f]+ <[^>]*> 7a6f7b87 	clei_s\.d	\$w14,\$w15,15
+[0-9a-f]+ <[^>]*> 7a928c0f 	cle_u\.b	\$w16,\$w17,\$w18
+[0-9a-f]+ <[^>]*> 7ab5a4cf 	cle_u\.h	\$w19,\$w20,\$w21
+[0-9a-f]+ <[^>]*> 7ad8bd8f 	cle_u\.w	\$w22,\$w23,\$w24
+[0-9a-f]+ <[^>]*> 7afbd64f 	cle_u\.d	\$w25,\$w26,\$w27
+[0-9a-f]+ <[^>]*> 7a80ef07 	clei_u\.b	\$w28,\$w29,0
+[0-9a-f]+ <[^>]*> 7a9fff87 	clei_u\.b	\$w30,\$w31,31
+[0-9a-f]+ <[^>]*> 7aa00807 	clei_u\.h	\$w0,\$w1,0
+[0-9a-f]+ <[^>]*> 7abf1887 	clei_u\.h	\$w2,\$w3,31
+[0-9a-f]+ <[^>]*> 7ac02907 	clei_u\.w	\$w4,\$w5,0
+[0-9a-f]+ <[^>]*> 7adf3987 	clei_u\.w	\$w6,\$w7,31
+[0-9a-f]+ <[^>]*> 7ae04a07 	clei_u\.d	\$w8,\$w9,0
+[0-9a-f]+ <[^>]*> 7aff5a87 	clei_u\.d	\$w10,\$w11,31
+[0-9a-f]+ <[^>]*> 7a006b20 	ld\.b	\$w12,-512\(t5\)
+[0-9a-f]+ <[^>]*> 79ff7ba0 	ld\.b	\$w14,511\(t7\)
+[0-9a-f]+ <[^>]*> 7a008c21 	ld\.h	\$w16,-1024\(s1\)
+[0-9a-f]+ <[^>]*> 79ff9ca1 	ld\.h	\$w18,1022\(s3\)
+[0-9a-f]+ <[^>]*> 7a00ad22 	ld\.w	\$w20,-2048\(s5\)
+[0-9a-f]+ <[^>]*> 79ffbda2 	ld\.w	\$w22,2044\(s7\)
+[0-9a-f]+ <[^>]*> 7a00ce23 	ld\.d	\$w24,-4096\(t9\)
+[0-9a-f]+ <[^>]*> 79ffdea3 	ld\.d	\$w26,4088\(k1\)
+[0-9a-f]+ <[^>]*> 7a00ef24 	st\.b	\$w28,-512\(sp\)
+[0-9a-f]+ <[^>]*> 79ffffa4 	st\.b	\$w30,511\(ra\)
+[0-9a-f]+ <[^>]*> 7a000825 	st\.h	\$w0,-1024\(at\)
+[0-9a-f]+ <[^>]*> 79ff18a5 	st\.h	\$w2,1022\(v1\)
+[0-9a-f]+ <[^>]*> 7a002926 	st\.w	\$w4,-2048\(a1\)
+[0-9a-f]+ <[^>]*> 79ff39a6 	st\.w	\$w6,2044\(a3\)
+[0-9a-f]+ <[^>]*> 7a004a27 	st\.d	\$w8,-4096\(t1\)
+[0-9a-f]+ <[^>]*> 79ff5aa7 	st\.d	\$w10,4088\(t3\)
+[0-9a-f]+ <[^>]*> 78706b0a 	sat_s\.b	\$w12,\$w13,0x0
+[0-9a-f]+ <[^>]*> 78777b8a 	sat_s\.b	\$w14,\$w15,0x7
+[0-9a-f]+ <[^>]*> 78608c0a 	sat_s\.h	\$w16,\$w17,0x0
+[0-9a-f]+ <[^>]*> 786f9c8a 	sat_s\.h	\$w18,\$w19,0xf
+[0-9a-f]+ <[^>]*> 7840ad0a 	sat_s\.w	\$w20,\$w21,0x0
+[0-9a-f]+ <[^>]*> 785fbd8a 	sat_s\.w	\$w22,\$w23,0x1f
+[0-9a-f]+ <[^>]*> 7800ce0a 	sat_s\.d	\$w24,\$w25,0x0
+[0-9a-f]+ <[^>]*> 783fde8a 	sat_s\.d	\$w26,\$w27,0x3f
+[0-9a-f]+ <[^>]*> 78f0ef0a 	sat_u\.b	\$w28,\$w29,0x0
+[0-9a-f]+ <[^>]*> 78f7ff8a 	sat_u\.b	\$w30,\$w31,0x7
+[0-9a-f]+ <[^>]*> 78e0080a 	sat_u\.h	\$w0,\$w1,0x0
+[0-9a-f]+ <[^>]*> 78ef188a 	sat_u\.h	\$w2,\$w3,0xf
+[0-9a-f]+ <[^>]*> 78c0290a 	sat_u\.w	\$w4,\$w5,0x0
+[0-9a-f]+ <[^>]*> 78df398a 	sat_u\.w	\$w6,\$w7,0x1f
+[0-9a-f]+ <[^>]*> 78804a0a 	sat_u\.d	\$w8,\$w9,0x0
+[0-9a-f]+ <[^>]*> 78bf5a8a 	sat_u\.d	\$w10,\$w11,0x3f
+[0-9a-f]+ <[^>]*> 780e6b10 	add_a\.b	\$w12,\$w13,\$w14
+[0-9a-f]+ <[^>]*> 783183d0 	add_a\.h	\$w15,\$w16,\$w17
+[0-9a-f]+ <[^>]*> 78549c90 	add_a\.w	\$w18,\$w19,\$w20
+[0-9a-f]+ <[^>]*> 7877b550 	add_a\.d	\$w21,\$w22,\$w23
+[0-9a-f]+ <[^>]*> 789ace10 	adds_a\.b	\$w24,\$w25,\$w26
+[0-9a-f]+ <[^>]*> 78bde6d0 	adds_a\.h	\$w27,\$w28,\$w29
+[0-9a-f]+ <[^>]*> 78c0ff90 	adds_a\.w	\$w30,\$w31,\$w0
+[0-9a-f]+ <[^>]*> 78e31050 	adds_a\.d	\$w1,\$w2,\$w3
+[0-9a-f]+ <[^>]*> 79062910 	adds_s\.b	\$w4,\$w5,\$w6
+[0-9a-f]+ <[^>]*> 792941d0 	adds_s\.h	\$w7,\$w8,\$w9
+[0-9a-f]+ <[^>]*> 794c5a90 	adds_s\.w	\$w10,\$w11,\$w12
+[0-9a-f]+ <[^>]*> 796f7350 	adds_s\.d	\$w13,\$w14,\$w15
+[0-9a-f]+ <[^>]*> 79928c10 	adds_u\.b	\$w16,\$w17,\$w18
+[0-9a-f]+ <[^>]*> 79b5a4d0 	adds_u\.h	\$w19,\$w20,\$w21
+[0-9a-f]+ <[^>]*> 79d8bd90 	adds_u\.w	\$w22,\$w23,\$w24
+[0-9a-f]+ <[^>]*> 79fbd650 	adds_u\.d	\$w25,\$w26,\$w27
+[0-9a-f]+ <[^>]*> 7a1eef10 	ave_s\.b	\$w28,\$w29,\$w30
+[0-9a-f]+ <[^>]*> 7a2107d0 	ave_s\.h	\$w31,\$w0,\$w1
+[0-9a-f]+ <[^>]*> 7a441890 	ave_s\.w	\$w2,\$w3,\$w4
+[0-9a-f]+ <[^>]*> 7a673150 	ave_s\.d	\$w5,\$w6,\$w7
+[0-9a-f]+ <[^>]*> 7a8a4a10 	ave_u\.b	\$w8,\$w9,\$w10
+[0-9a-f]+ <[^>]*> 7aad62d0 	ave_u\.h	\$w11,\$w12,\$w13
+[0-9a-f]+ <[^>]*> 7ad07b90 	ave_u\.w	\$w14,\$w15,\$w16
+[0-9a-f]+ <[^>]*> 7af39450 	ave_u\.d	\$w17,\$w18,\$w19
+[0-9a-f]+ <[^>]*> 7b16ad10 	aver_s\.b	\$w20,\$w21,\$w22
+[0-9a-f]+ <[^>]*> 7b39c5d0 	aver_s\.h	\$w23,\$w24,\$w25
+[0-9a-f]+ <[^>]*> 7b5cde90 	aver_s\.w	\$w26,\$w27,\$w28
+[0-9a-f]+ <[^>]*> 7b7ff750 	aver_s\.d	\$w29,\$w30,\$w31
+[0-9a-f]+ <[^>]*> 7b820810 	aver_u\.b	\$w0,\$w1,\$w2
+[0-9a-f]+ <[^>]*> 7ba520d0 	aver_u\.h	\$w3,\$w4,\$w5
+[0-9a-f]+ <[^>]*> 7bc83990 	aver_u\.w	\$w6,\$w7,\$w8
+[0-9a-f]+ <[^>]*> 7beb5250 	aver_u\.d	\$w9,\$w10,\$w11
+[0-9a-f]+ <[^>]*> 780e6b11 	subs_s\.b	\$w12,\$w13,\$w14
+[0-9a-f]+ <[^>]*> 783183d1 	subs_s\.h	\$w15,\$w16,\$w17
+[0-9a-f]+ <[^>]*> 78549c91 	subs_s\.w	\$w18,\$w19,\$w20
+[0-9a-f]+ <[^>]*> 7877b551 	subs_s\.d	\$w21,\$w22,\$w23
+[0-9a-f]+ <[^>]*> 789ace11 	subs_u\.b	\$w24,\$w25,\$w26
+[0-9a-f]+ <[^>]*> 78bde6d1 	subs_u\.h	\$w27,\$w28,\$w29
+[0-9a-f]+ <[^>]*> 78c0ff91 	subs_u\.w	\$w30,\$w31,\$w0
+[0-9a-f]+ <[^>]*> 78e31051 	subs_u\.d	\$w1,\$w2,\$w3
+[0-9a-f]+ <[^>]*> 79062911 	subsus_u\.b	\$w4,\$w5,\$w6
+[0-9a-f]+ <[^>]*> 792941d1 	subsus_u\.h	\$w7,\$w8,\$w9
+[0-9a-f]+ <[^>]*> 794c5a91 	subsus_u\.w	\$w10,\$w11,\$w12
+[0-9a-f]+ <[^>]*> 796f7351 	subsus_u\.d	\$w13,\$w14,\$w15
+[0-9a-f]+ <[^>]*> 79928c11 	subsuu_s\.b	\$w16,\$w17,\$w18
+[0-9a-f]+ <[^>]*> 79b5a4d1 	subsuu_s\.h	\$w19,\$w20,\$w21
+[0-9a-f]+ <[^>]*> 79d8bd91 	subsuu_s\.w	\$w22,\$w23,\$w24
+[0-9a-f]+ <[^>]*> 79fbd651 	subsuu_s\.d	\$w25,\$w26,\$w27
+[0-9a-f]+ <[^>]*> 7a1eef11 	asub_s\.b	\$w28,\$w29,\$w30
+[0-9a-f]+ <[^>]*> 7a2107d1 	asub_s\.h	\$w31,\$w0,\$w1
+[0-9a-f]+ <[^>]*> 7a441891 	asub_s\.w	\$w2,\$w3,\$w4
+[0-9a-f]+ <[^>]*> 7a673151 	asub_s\.d	\$w5,\$w6,\$w7
+[0-9a-f]+ <[^>]*> 7a8a4a11 	asub_u\.b	\$w8,\$w9,\$w10
+[0-9a-f]+ <[^>]*> 7aad62d1 	asub_u\.h	\$w11,\$w12,\$w13
+[0-9a-f]+ <[^>]*> 7ad07b91 	asub_u\.w	\$w14,\$w15,\$w16
+[0-9a-f]+ <[^>]*> 7af39451 	asub_u\.d	\$w17,\$w18,\$w19
+[0-9a-f]+ <[^>]*> 7816ad12 	mulv\.b	\$w20,\$w21,\$w22
+[0-9a-f]+ <[^>]*> 7839c5d2 	mulv\.h	\$w23,\$w24,\$w25
+[0-9a-f]+ <[^>]*> 785cde92 	mulv\.w	\$w26,\$w27,\$w28
+[0-9a-f]+ <[^>]*> 787ff752 	mulv\.d	\$w29,\$w30,\$w31
+[0-9a-f]+ <[^>]*> 78820812 	maddv\.b	\$w0,\$w1,\$w2
+[0-9a-f]+ <[^>]*> 78a520d2 	maddv\.h	\$w3,\$w4,\$w5
+[0-9a-f]+ <[^>]*> 78c83992 	maddv\.w	\$w6,\$w7,\$w8
+[0-9a-f]+ <[^>]*> 78eb5252 	maddv\.d	\$w9,\$w10,\$w11
+[0-9a-f]+ <[^>]*> 790e6b12 	msubv\.b	\$w12,\$w13,\$w14
+[0-9a-f]+ <[^>]*> 793183d2 	msubv\.h	\$w15,\$w16,\$w17
+[0-9a-f]+ <[^>]*> 79549c92 	msubv\.w	\$w18,\$w19,\$w20
+[0-9a-f]+ <[^>]*> 7977b552 	msubv\.d	\$w21,\$w22,\$w23
+[0-9a-f]+ <[^>]*> 7a1ace12 	div_s\.b	\$w24,\$w25,\$w26
+[0-9a-f]+ <[^>]*> 7a3de6d2 	div_s\.h	\$w27,\$w28,\$w29
+[0-9a-f]+ <[^>]*> 7a40ff92 	div_s\.w	\$w30,\$w31,\$w0
+[0-9a-f]+ <[^>]*> 7a631052 	div_s\.d	\$w1,\$w2,\$w3
+[0-9a-f]+ <[^>]*> 7a862912 	div_u\.b	\$w4,\$w5,\$w6
+[0-9a-f]+ <[^>]*> 7aa941d2 	div_u\.h	\$w7,\$w8,\$w9
+[0-9a-f]+ <[^>]*> 7acc5a92 	div_u\.w	\$w10,\$w11,\$w12
+[0-9a-f]+ <[^>]*> 7aef7352 	div_u\.d	\$w13,\$w14,\$w15
+[0-9a-f]+ <[^>]*> 7b128c12 	mod_s\.b	\$w16,\$w17,\$w18
+[0-9a-f]+ <[^>]*> 7b35a4d2 	mod_s\.h	\$w19,\$w20,\$w21
+[0-9a-f]+ <[^>]*> 7b58bd92 	mod_s\.w	\$w22,\$w23,\$w24
+[0-9a-f]+ <[^>]*> 7b7bd652 	mod_s\.d	\$w25,\$w26,\$w27
+[0-9a-f]+ <[^>]*> 7b9eef12 	mod_u\.b	\$w28,\$w29,\$w30
+[0-9a-f]+ <[^>]*> 7ba107d2 	mod_u\.h	\$w31,\$w0,\$w1
+[0-9a-f]+ <[^>]*> 7bc41892 	mod_u\.w	\$w2,\$w3,\$w4
+[0-9a-f]+ <[^>]*> 7be73152 	mod_u\.d	\$w5,\$w6,\$w7
+[0-9a-f]+ <[^>]*> 782a4a13 	dotp_s\.h	\$w8,\$w9,\$w10
+[0-9a-f]+ <[^>]*> 784d62d3 	dotp_s\.w	\$w11,\$w12,\$w13
+[0-9a-f]+ <[^>]*> 78707b93 	dotp_s\.d	\$w14,\$w15,\$w16
+[0-9a-f]+ <[^>]*> 78b39453 	dotp_u\.h	\$w17,\$w18,\$w19
+[0-9a-f]+ <[^>]*> 78d6ad13 	dotp_u\.w	\$w20,\$w21,\$w22
+[0-9a-f]+ <[^>]*> 78f9c5d3 	dotp_u\.d	\$w23,\$w24,\$w25
+[0-9a-f]+ <[^>]*> 793cde93 	dpadd_s\.h	\$w26,\$w27,\$w28
+[0-9a-f]+ <[^>]*> 795ff753 	dpadd_s\.w	\$w29,\$w30,\$w31
+[0-9a-f]+ <[^>]*> 79620813 	dpadd_s\.d	\$w0,\$w1,\$w2
+[0-9a-f]+ <[^>]*> 79a520d3 	dpadd_u\.h	\$w3,\$w4,\$w5
+[0-9a-f]+ <[^>]*> 79c83993 	dpadd_u\.w	\$w6,\$w7,\$w8
+[0-9a-f]+ <[^>]*> 79eb5253 	dpadd_u\.d	\$w9,\$w10,\$w11
+[0-9a-f]+ <[^>]*> 7a2e6b13 	dpsub_s\.h	\$w12,\$w13,\$w14
+[0-9a-f]+ <[^>]*> 7a5183d3 	dpsub_s\.w	\$w15,\$w16,\$w17
+[0-9a-f]+ <[^>]*> 7a749c93 	dpsub_s\.d	\$w18,\$w19,\$w20
+[0-9a-f]+ <[^>]*> 7ab7b553 	dpsub_u\.h	\$w21,\$w22,\$w23
+[0-9a-f]+ <[^>]*> 7adace13 	dpsub_u\.w	\$w24,\$w25,\$w26
+[0-9a-f]+ <[^>]*> 7afde6d3 	dpsub_u\.d	\$w27,\$w28,\$w29
+[0-9a-f]+ <[^>]*> 7800ff94 	sld\.b	\$w30,\$w31\[zero\]
+[0-9a-f]+ <[^>]*> 78231054 	sld\.h	\$w1,\$w2\[v1\]
+[0-9a-f]+ <[^>]*> 78462914 	sld\.w	\$w4,\$w5\[a2\]
+[0-9a-f]+ <[^>]*> 786941d4 	sld\.d	\$w7,\$w8\[t1\]
+[0-9a-f]+ <[^>]*> 78005a99 	sldi\.b	\$w10,\$w11\[0\]
+[0-9a-f]+ <[^>]*> 780f6b19 	sldi\.b	\$w12,\$w13\[15\]
+[0-9a-f]+ <[^>]*> 78207b99 	sldi\.h	\$w14,\$w15\[0\]
+[0-9a-f]+ <[^>]*> 78278c19 	sldi\.h	\$w16,\$w17\[7\]
+[0-9a-f]+ <[^>]*> 78309c99 	sldi\.w	\$w18,\$w19\[0\]
+[0-9a-f]+ <[^>]*> 7833ad19 	sldi\.w	\$w20,\$w21\[3\]
+[0-9a-f]+ <[^>]*> 7838bd99 	sldi\.d	\$w22,\$w23\[0\]
+[0-9a-f]+ <[^>]*> 7839ce19 	sldi\.d	\$w24,\$w25\[1\]
+[0-9a-f]+ <[^>]*> 789cde94 	splat\.b	\$w26,\$w27\[gp\]
+[0-9a-f]+ <[^>]*> 78bff754 	splat\.h	\$w29,\$w30\[ra\]
+[0-9a-f]+ <[^>]*> 78c20814 	splat\.w	\$w0,\$w1\[v0\]
+[0-9a-f]+ <[^>]*> 78e520d4 	splat\.d	\$w3,\$w4\[a1\]
+[0-9a-f]+ <[^>]*> 78403999 	splati\.b	\$w6,\$w7\[0\]
+[0-9a-f]+ <[^>]*> 784f4a19 	splati\.b	\$w8,\$w9\[15\]
+[0-9a-f]+ <[^>]*> 78605a99 	splati\.h	\$w10,\$w11\[0\]
+[0-9a-f]+ <[^>]*> 78676b19 	splati\.h	\$w12,\$w13\[7\]
+[0-9a-f]+ <[^>]*> 78707b99 	splati\.w	\$w14,\$w15\[0\]
+[0-9a-f]+ <[^>]*> 78738c19 	splati\.w	\$w16,\$w17\[3\]
+[0-9a-f]+ <[^>]*> 78789c99 	splati\.d	\$w18,\$w19\[0\]
+[0-9a-f]+ <[^>]*> 7879ad19 	splati\.d	\$w20,\$w21\[1\]
+[0-9a-f]+ <[^>]*> 7918bd94 	pckev\.b	\$w22,\$w23,\$w24
+[0-9a-f]+ <[^>]*> 793bd654 	pckev\.h	\$w25,\$w26,\$w27
+[0-9a-f]+ <[^>]*> 795eef14 	pckev\.w	\$w28,\$w29,\$w30
+[0-9a-f]+ <[^>]*> 796107d4 	pckev\.d	\$w31,\$w0,\$w1
+[0-9a-f]+ <[^>]*> 79841894 	pckod\.b	\$w2,\$w3,\$w4
+[0-9a-f]+ <[^>]*> 79a73154 	pckod\.h	\$w5,\$w6,\$w7
+[0-9a-f]+ <[^>]*> 79ca4a14 	pckod\.w	\$w8,\$w9,\$w10
+[0-9a-f]+ <[^>]*> 79ed62d4 	pckod\.d	\$w11,\$w12,\$w13
+[0-9a-f]+ <[^>]*> 7a107b94 	ilvl\.b	\$w14,\$w15,\$w16
+[0-9a-f]+ <[^>]*> 7a339454 	ilvl\.h	\$w17,\$w18,\$w19
+[0-9a-f]+ <[^>]*> 7a56ad14 	ilvl\.w	\$w20,\$w21,\$w22
+[0-9a-f]+ <[^>]*> 7a79c5d4 	ilvl\.d	\$w23,\$w24,\$w25
+[0-9a-f]+ <[^>]*> 7a9cde94 	ilvr\.b	\$w26,\$w27,\$w28
+[0-9a-f]+ <[^>]*> 7abff754 	ilvr\.h	\$w29,\$w30,\$w31
+[0-9a-f]+ <[^>]*> 7ac20814 	ilvr\.w	\$w0,\$w1,\$w2
+[0-9a-f]+ <[^>]*> 7ae520d4 	ilvr\.d	\$w3,\$w4,\$w5
+[0-9a-f]+ <[^>]*> 7b083994 	ilvev\.b	\$w6,\$w7,\$w8
+[0-9a-f]+ <[^>]*> 7b2b5254 	ilvev\.h	\$w9,\$w10,\$w11
+[0-9a-f]+ <[^>]*> 7b4e6b14 	ilvev\.w	\$w12,\$w13,\$w14
+[0-9a-f]+ <[^>]*> 7b7183d4 	ilvev\.d	\$w15,\$w16,\$w17
+[0-9a-f]+ <[^>]*> 7b949c94 	ilvod\.b	\$w18,\$w19,\$w20
+[0-9a-f]+ <[^>]*> 7bb7b554 	ilvod\.h	\$w21,\$w22,\$w23
+[0-9a-f]+ <[^>]*> 7bdace14 	ilvod\.w	\$w24,\$w25,\$w26
+[0-9a-f]+ <[^>]*> 7bfde6d4 	ilvod\.d	\$w27,\$w28,\$w29
+[0-9a-f]+ <[^>]*> 7800ff95 	vshf\.b	\$w30,\$w31,\$w0
+[0-9a-f]+ <[^>]*> 78231055 	vshf\.h	\$w1,\$w2,\$w3
+[0-9a-f]+ <[^>]*> 78462915 	vshf\.w	\$w4,\$w5,\$w6
+[0-9a-f]+ <[^>]*> 786941d5 	vshf\.d	\$w7,\$w8,\$w9
+[0-9a-f]+ <[^>]*> 788c5a95 	srar\.b	\$w10,\$w11,\$w12
+[0-9a-f]+ <[^>]*> 78af7355 	srar\.h	\$w13,\$w14,\$w15
+[0-9a-f]+ <[^>]*> 78d28c15 	srar\.w	\$w16,\$w17,\$w18
+[0-9a-f]+ <[^>]*> 78f5a4d5 	srar\.d	\$w19,\$w20,\$w21
+[0-9a-f]+ <[^>]*> 7970bd8a 	srari\.b	\$w22,\$w23,0x0
+[0-9a-f]+ <[^>]*> 7977ce0a 	srari\.b	\$w24,\$w25,0x7
+[0-9a-f]+ <[^>]*> 7960de8a 	srari\.h	\$w26,\$w27,0x0
+[0-9a-f]+ <[^>]*> 796fef0a 	srari\.h	\$w28,\$w29,0xf
+[0-9a-f]+ <[^>]*> 7940ff8a 	srari\.w	\$w30,\$w31,0x0
+[0-9a-f]+ <[^>]*> 795f080a 	srari\.w	\$w0,\$w1,0x1f
+[0-9a-f]+ <[^>]*> 7900188a 	srari\.d	\$w2,\$w3,0x0
+[0-9a-f]+ <[^>]*> 793f290a 	srari\.d	\$w4,\$w5,0x3f
+[0-9a-f]+ <[^>]*> 79083995 	srlr\.b	\$w6,\$w7,\$w8
+[0-9a-f]+ <[^>]*> 792b5255 	srlr\.h	\$w9,\$w10,\$w11
+[0-9a-f]+ <[^>]*> 794e6b15 	srlr\.w	\$w12,\$w13,\$w14
+[0-9a-f]+ <[^>]*> 797183d5 	srlr\.d	\$w15,\$w16,\$w17
+[0-9a-f]+ <[^>]*> 79f09c8a 	srlri\.b	\$w18,\$w19,0x0
+[0-9a-f]+ <[^>]*> 79f7ad0a 	srlri\.b	\$w20,\$w21,0x7
+[0-9a-f]+ <[^>]*> 79e0bd8a 	srlri\.h	\$w22,\$w23,0x0
+[0-9a-f]+ <[^>]*> 79efce0a 	srlri\.h	\$w24,\$w25,0xf
+[0-9a-f]+ <[^>]*> 79c0de8a 	srlri\.w	\$w26,\$w27,0x0
+[0-9a-f]+ <[^>]*> 79dfef0a 	srlri\.w	\$w28,\$w29,0x1f
+[0-9a-f]+ <[^>]*> 7980ff8a 	srlri\.d	\$w30,\$w31,0x0
+[0-9a-f]+ <[^>]*> 79bf080a 	srlri\.d	\$w0,\$w1,0x3f
+[0-9a-f]+ <[^>]*> 7a241895 	hadd_s\.h	\$w2,\$w3,\$w4
+[0-9a-f]+ <[^>]*> 7a473155 	hadd_s\.w	\$w5,\$w6,\$w7
+[0-9a-f]+ <[^>]*> 7a6a4a15 	hadd_s\.d	\$w8,\$w9,\$w10
+[0-9a-f]+ <[^>]*> 7aad62d5 	hadd_u\.h	\$w11,\$w12,\$w13
+[0-9a-f]+ <[^>]*> 7ad07b95 	hadd_u\.w	\$w14,\$w15,\$w16
+[0-9a-f]+ <[^>]*> 7af39455 	hadd_u\.d	\$w17,\$w18,\$w19
+[0-9a-f]+ <[^>]*> 7b36ad15 	hsub_s\.h	\$w20,\$w21,\$w22
+[0-9a-f]+ <[^>]*> 7b59c5d5 	hsub_s\.w	\$w23,\$w24,\$w25
+[0-9a-f]+ <[^>]*> 7b7cde95 	hsub_s\.d	\$w26,\$w27,\$w28
+[0-9a-f]+ <[^>]*> 7bbff755 	hsub_u\.h	\$w29,\$w30,\$w31
+[0-9a-f]+ <[^>]*> 7bc20815 	hsub_u\.w	\$w0,\$w1,\$w2
+[0-9a-f]+ <[^>]*> 7be520d5 	hsub_u\.d	\$w3,\$w4,\$w5
+[0-9a-f]+ <[^>]*> 7808399e 	and\.v	\$w6,\$w7,\$w8
+[0-9a-f]+ <[^>]*> 78005240 	andi\.b	\$w9,\$w10,0x0
+[0-9a-f]+ <[^>]*> 78ff62c0 	andi\.b	\$w11,\$w12,0xff
+[0-9a-f]+ <[^>]*> 782f735e 	or\.v	\$w13,\$w14,\$w15
+[0-9a-f]+ <[^>]*> 79008c00 	ori\.b	\$w16,\$w17,0x0
+[0-9a-f]+ <[^>]*> 79ff9c80 	ori\.b	\$w18,\$w19,0xff
+[0-9a-f]+ <[^>]*> 7856ad1e 	nor\.v	\$w20,\$w21,\$w22
+[0-9a-f]+ <[^>]*> 7a00c5c0 	nori\.b	\$w23,\$w24,0x0
+[0-9a-f]+ <[^>]*> 7affd640 	nori\.b	\$w25,\$w26,0xff
+[0-9a-f]+ <[^>]*> 787de6de 	xor\.v	\$w27,\$w28,\$w29
+[0-9a-f]+ <[^>]*> 7b00ff80 	xori\.b	\$w30,\$w31,0x0
+[0-9a-f]+ <[^>]*> 7bff0800 	xori\.b	\$w0,\$w1,0xff
+[0-9a-f]+ <[^>]*> 7884189e 	bmnz\.v	\$w2,\$w3,\$w4
+[0-9a-f]+ <[^>]*> 78003141 	bmnzi\.b	\$w5,\$w6,0x0
+[0-9a-f]+ <[^>]*> 78ff41c1 	bmnzi\.b	\$w7,\$w8,0xff
+[0-9a-f]+ <[^>]*> 78ab525e 	bmz\.v	\$w9,\$w10,\$w11
+[0-9a-f]+ <[^>]*> 79006b01 	bmzi\.b	\$w12,\$w13,0x0
+[0-9a-f]+ <[^>]*> 79ff7b81 	bmzi\.b	\$w14,\$w15,0xff
+[0-9a-f]+ <[^>]*> 78d28c1e 	bsel\.v	\$w16,\$w17,\$w18
+[0-9a-f]+ <[^>]*> 7a00a4c1 	bseli\.b	\$w19,\$w20,0x0
+[0-9a-f]+ <[^>]*> 7affb541 	bseli\.b	\$w21,\$w22,0xff
+[0-9a-f]+ <[^>]*> 7800c5c2 	shf\.b	\$w23,\$w24,0x0
+[0-9a-f]+ <[^>]*> 78ffd642 	shf\.b	\$w25,\$w26,0xff
+[0-9a-f]+ <[^>]*> 7900e6c2 	shf\.h	\$w27,\$w28,0x0
+[0-9a-f]+ <[^>]*> 79fff742 	shf\.h	\$w29,\$w30,0xff
+[0-9a-f]+ <[^>]*> 7a0007c2 	shf\.w	\$w31,\$w0,0x0
+[0-9a-f]+ <[^>]*> 7aff1042 	shf\.w	\$w1,\$w2,0xff
+[0-9a-f]+ <[^>]*> 45e38000 	bnz\.v	\$w3,[0-9a-f]+ <[^>]*>
+[	]*794: .*R_MIPS_PC16	L0.
+[0-9a-f]+ <[^>]*> 00000000 	nop
+[0-9a-f]+ <[^>]*> 45e47fff 	bnz\.v	\$w4,[0-9a-f]+ <[^>]*>
+[	]*79c: .*R_MIPS_PC16	L0.
+[0-9a-f]+ <[^>]*> 00000000 	nop
+[0-9a-f]+ <[^>]*> 45e5ffff 	bnz\.v	\$w5,[0-9a-f]+ <[^>]*>
+[	]*7a4: .*R_MIPS_PC16	.L1.1
+[0-9a-f]+ <[^>]*> 00000000 	nop
+[0-9a-f]+ <[^>]*> 45e6ffff 	bnz\.v	\$w6,[0-9a-f]+ <[^>]*>
+[	]*[0-9a-f]+: R_MIPS_PC16	external_label
+[0-9a-f]+ <[^>]*> 00000000 	nop
+[0-9a-f]+ <[^>]*> 45678000 	bz\.v	\$w7,[0-9a-f]+ <[^>]*>
+[	]*7b4: .*R_MIPS_PC16	L0.
+[0-9a-f]+ <[^>]*> 00000000 	nop
+[0-9a-f]+ <[^>]*> 45687fff 	bz\.v	\$w8,[0-9a-f]+ <[^>]*>
+[	]*7bc: .*R_MIPS_PC16	L0.
+[0-9a-f]+ <[^>]*> 00000000 	nop
+[0-9a-f]+ <[^>]*> 4569ffff 	bz\.v	\$w9,[0-9a-f]+ <[^>]*>
+[	]*7c4: .*R_MIPS_PC16	.L1.2
+[0-9a-f]+ <[^>]*> 00000000 	nop
+[0-9a-f]+ <[^>]*> 456affff 	bz\.v	\$w10,[0-9a-f]+ <[^>]*>
+[	]*[0-9a-f]+: R_MIPS_PC16	external_label
+[0-9a-f]+ <[^>]*> 00000000 	nop
+[0-9a-f]+ <[^>]*> 7b0062de 	fill\.b	\$w11,t4
+[0-9a-f]+ <[^>]*> 7b01735e 	fill\.h	\$w13,t6
+[0-9a-f]+ <[^>]*> 7b0283de 	fill\.w	\$w15,s0
+[0-9a-f]+ <[^>]*> 7b04a4de 	pcnt\.b	\$w19,\$w20
+[0-9a-f]+ <[^>]*> 7b05b55e 	pcnt\.h	\$w21,\$w22
+[0-9a-f]+ <[^>]*> 7b06c5de 	pcnt\.w	\$w23,\$w24
+[0-9a-f]+ <[^>]*> 7b07d65e 	pcnt\.d	\$w25,\$w26
+[0-9a-f]+ <[^>]*> 7b08e6de 	nloc\.b	\$w27,\$w28
+[0-9a-f]+ <[^>]*> 7b09f75e 	nloc\.h	\$w29,\$w30
+[0-9a-f]+ <[^>]*> 7b0a07de 	nloc\.w	\$w31,\$w0
+[0-9a-f]+ <[^>]*> 7b0b105e 	nloc\.d	\$w1,\$w2
+[0-9a-f]+ <[^>]*> 7b0c20de 	nlzc\.b	\$w3,\$w4
+[0-9a-f]+ <[^>]*> 7b0d315e 	nlzc\.h	\$w5,\$w6
+[0-9a-f]+ <[^>]*> 7b0e41de 	nlzc\.w	\$w7,\$w8
+[0-9a-f]+ <[^>]*> 7b0f525e 	nlzc\.d	\$w9,\$w10
+[0-9a-f]+ <[^>]*> 788062d9 	copy_s\.b	t3,\$w12\[0\]
+[0-9a-f]+ <[^>]*> 788f7359 	copy_s\.b	t5,\$w14\[15\]
+[0-9a-f]+ <[^>]*> 78a083d9 	copy_s\.h	t7,\$w16\[0\]
+[0-9a-f]+ <[^>]*> 78a79459 	copy_s\.h	s1,\$w18\[7\]
+[0-9a-f]+ <[^>]*> 78b0a4d9 	copy_s\.w	s3,\$w20\[0\]
+[0-9a-f]+ <[^>]*> 78b3b559 	copy_s\.w	s5,\$w22\[3\]
+[0-9a-f]+ <[^>]*> 78c0e6d9 	copy_u\.b	k1,\$w28\[0\]
+[0-9a-f]+ <[^>]*> 78cff759 	copy_u\.b	sp,\$w30\[15\]
+[0-9a-f]+ <[^>]*> 78e007d9 	copy_u\.h	ra,\$w0\[0\]
+[0-9a-f]+ <[^>]*> 78e71059 	copy_u\.h	at,\$w2\[7\]
+[0-9a-f]+ <[^>]*> 78f020d9 	copy_u\.w	v1,\$w4\[0\]
+[0-9a-f]+ <[^>]*> 78f33159 	copy_u\.w	a1,\$w6\[3\]
+[0-9a-f]+ <[^>]*> 790062d9 	insert\.b	\$w11\[0\],t4
+[0-9a-f]+ <[^>]*> 790f7359 	insert\.b	\$w13\[15\],t6
+[0-9a-f]+ <[^>]*> 792083d9 	insert\.h	\$w15\[0\],s0
+[0-9a-f]+ <[^>]*> 79279459 	insert\.h	\$w17\[7\],s2
+[0-9a-f]+ <[^>]*> 7930a4d9 	insert\.w	\$w19\[0\],s4
+[0-9a-f]+ <[^>]*> 7933b559 	insert\.w	\$w21\[3\],s6
+[0-9a-f]+ <[^>]*> 7940e6d9 	insve\.b	\$w27\[0\],\$w28\[0\]
+[0-9a-f]+ <[^>]*> 794ff759 	insve\.b	\$w29\[15\],\$w30\[0\]
+[0-9a-f]+ <[^>]*> 796007d9 	insve\.h	\$w31\[0\],\$w0\[0\]
+[0-9a-f]+ <[^>]*> 79671059 	insve\.h	\$w1\[7\],\$w2\[0\]
+[0-9a-f]+ <[^>]*> 797020d9 	insve\.w	\$w3\[0\],\$w4\[0\]
+[0-9a-f]+ <[^>]*> 79733159 	insve\.w	\$w5\[3\],\$w6\[0\]
+[0-9a-f]+ <[^>]*> 797841d9 	insve\.d	\$w7\[0\],\$w8\[0\]
+[0-9a-f]+ <[^>]*> 79795259 	insve\.d	\$w9\[1\],\$w10\[0\]
+[0-9a-f]+ <[^>]*> 478b8000 	bnz\.b	\$w11,[0-9a-f]+ <[^>]*>
+[	]*878: .*R_MIPS_PC16	L0.
+[0-9a-f]+ <[^>]*> 00000000 	nop
+[0-9a-f]+ <[^>]*> 478c7fff 	bnz\.b	\$w12,[0-9a-f]+ <[^>]*>
+[	]*880: .*R_MIPS_PC16	L0.
+[0-9a-f]+ <[^>]*> 00000000 	nop
+[0-9a-f]+ <[^>]*> 478dffff 	bnz\.b	\$w13,[0-9a-f]+ <[^>]*>
+[	]*888: .*R_MIPS_PC16	.L1.3
+[0-9a-f]+ <[^>]*> 00000000 	nop
+[0-9a-f]+ <[^>]*> 478effff 	bnz\.b	\$w14,[0-9a-f]+ <[^>]*>
+[	]*[0-9a-f]+: R_MIPS_PC16	external_label
+[0-9a-f]+ <[^>]*> 00000000 	nop
+[0-9a-f]+ <[^>]*> 47af8000 	bnz\.h	\$w15,[0-9a-f]+ <[^>]*>
+[	]*898: .*R_MIPS_PC16	L0.
+[0-9a-f]+ <[^>]*> 00000000 	nop
+[0-9a-f]+ <[^>]*> 47b07fff 	bnz\.h	\$w16,[0-9a-f]+ <[^>]*>
+[	]*8a0: .*R_MIPS_PC16	L0.
+[0-9a-f]+ <[^>]*> 00000000 	nop
+[0-9a-f]+ <[^>]*> 47b1ffff 	bnz\.h	\$w17,[0-9a-f]+ <[^>]*>
+[	]*8a8: .*R_MIPS_PC16	.L1.4
+[0-9a-f]+ <[^>]*> 00000000 	nop
+[0-9a-f]+ <[^>]*> 47b2ffff 	bnz\.h	\$w18,[0-9a-f]+ <[^>]*>
+[	]*[0-9a-f]+: R_MIPS_PC16	external_label
+[0-9a-f]+ <[^>]*> 00000000 	nop
+[0-9a-f]+ <[^>]*> 47d38000 	bnz\.w	\$w19,[0-9a-f]+ <[^>]*>
+[	]*8b8: .*R_MIPS_PC16	L0.
+[0-9a-f]+ <[^>]*> 00000000 	nop
+[0-9a-f]+ <[^>]*> 47d47fff 	bnz\.w	\$w20,[0-9a-f]+ <[^>]*>
+[	]*8c0: .*R_MIPS_PC16	L0.
+[0-9a-f]+ <[^>]*> 00000000 	nop
+[0-9a-f]+ <[^>]*> 47d5ffff 	bnz\.w	\$w21,[0-9a-f]+ <[^>]*>
+[	]*8c8: .*R_MIPS_PC16	.L1.5
+[0-9a-f]+ <[^>]*> 00000000 	nop
+[0-9a-f]+ <[^>]*> 47d6ffff 	bnz\.w	\$w22,[0-9a-f]+ <[^>]*>
+[	]*[0-9a-f]+: R_MIPS_PC16	external_label
+[0-9a-f]+ <[^>]*> 00000000 	nop
+[0-9a-f]+ <[^>]*> 47f78000 	bnz\.d	\$w23,[0-9a-f]+ <[^>]*>
+[	]*8d8: .*R_MIPS_PC16	L0.
+[0-9a-f]+ <[^>]*> 00000000 	nop
+[0-9a-f]+ <[^>]*> 47f87fff 	bnz\.d	\$w24,[0-9a-f]+ <[^>]*>
+[	]*8e0: .*R_MIPS_PC16	L0.
+[0-9a-f]+ <[^>]*> 00000000 	nop
+[0-9a-f]+ <[^>]*> 47f9ffff 	bnz\.d	\$w25,[0-9a-f]+ <[^>]*>
+[	]*8e8: .*R_MIPS_PC16	.L1.6
+[0-9a-f]+ <[^>]*> 00000000 	nop
+[0-9a-f]+ <[^>]*> 47faffff 	bnz\.d	\$w26,[0-9a-f]+ <[^>]*>
+[	]*[0-9a-f]+: R_MIPS_PC16	external_label
+[0-9a-f]+ <[^>]*> 00000000 	nop
+[0-9a-f]+ <[^>]*> 471b8000 	bz\.b	\$w27,[0-9a-f]+ <[^>]*>
+[	]*8f8: .*R_MIPS_PC16	L0.
+[0-9a-f]+ <[^>]*> 00000000 	nop
+[0-9a-f]+ <[^>]*> 471c7fff 	bz\.b	\$w28,[0-9a-f]+ <[^>]*>
+[	]*900: .*R_MIPS_PC16	L0.
+[0-9a-f]+ <[^>]*> 00000000 	nop
+[0-9a-f]+ <[^>]*> 471dffff 	bz\.b	\$w29,[0-9a-f]+ <[^>]*>
+[	]*908: .*R_MIPS_PC16	.L1.7
+[0-9a-f]+ <[^>]*> 00000000 	nop
+[0-9a-f]+ <[^>]*> 471effff 	bz\.b	\$w30,[0-9a-f]+ <[^>]*>
+[	]*[0-9a-f]+: R_MIPS_PC16	external_label
+[0-9a-f]+ <[^>]*> 00000000 	nop
+[0-9a-f]+ <[^>]*> 473f8000 	bz\.h	\$w31,[0-9a-f]+ <[^>]*>
+[	]*918: .*R_MIPS_PC16	L0.
+[0-9a-f]+ <[^>]*> 00000000 	nop
+[0-9a-f]+ <[^>]*> 47207fff 	bz\.h	\$w0,[0-9a-f]+ <[^>]*>
+[	]*920: .*R_MIPS_PC16	L0.
+[0-9a-f]+ <[^>]*> 00000000 	nop
+[0-9a-f]+ <[^>]*> 4721ffff 	bz\.h	\$w1,[0-9a-f]+ <[^>]*>
+[	]*928: .*R_MIPS_PC16	.L1.8
+[0-9a-f]+ <[^>]*> 00000000 	nop
+[0-9a-f]+ <[^>]*> 4722ffff 	bz\.h	\$w2,[0-9a-f]+ <[^>]*>
+[	]*[0-9a-f]+: R_MIPS_PC16	external_label
+[0-9a-f]+ <[^>]*> 00000000 	nop
+[0-9a-f]+ <[^>]*> 47438000 	bz\.w	\$w3,[0-9a-f]+ <[^>]*>
+[	]*938: .*R_MIPS_PC16	L0.
+[0-9a-f]+ <[^>]*> 00000000 	nop
+[0-9a-f]+ <[^>]*> 47447fff 	bz\.w	\$w4,[0-9a-f]+ <[^>]*>
+[	]*940: .*R_MIPS_PC16	L0.
+[0-9a-f]+ <[^>]*> 00000000 	nop
+[0-9a-f]+ <[^>]*> 4745ffff 	bz\.w	\$w5,[0-9a-f]+ <[^>]*>
+[	]*948: .*R_MIPS_PC16	.L1.9
+[0-9a-f]+ <[^>]*> 00000000 	nop
+[0-9a-f]+ <[^>]*> 4746ffff 	bz\.w	\$w6,[0-9a-f]+ <[^>]*>
+[	]*[0-9a-f]+: R_MIPS_PC16	external_label
+[0-9a-f]+ <[^>]*> 00000000 	nop
+[0-9a-f]+ <[^>]*> 47678000 	bz\.d	\$w7,[0-9a-f]+ <[^>]*>
+[	]*958: .*R_MIPS_PC16	L0.
+[0-9a-f]+ <[^>]*> 00000000 	nop
+[0-9a-f]+ <[^>]*> 47687fff 	bz\.d	\$w8,[0-9a-f]+ <[^>]*>
+[	]*960: .*R_MIPS_PC16	L0.
+[0-9a-f]+ <[^>]*> 00000000 	nop
+[0-9a-f]+ <[^>]*> 4769ffff 	bz\.d	\$w9,[0-9a-f]+ <[^>]*>
+[	]*968: .*R_MIPS_PC16	.L1.10
+[0-9a-f]+ <[^>]*> 00000000 	nop
+[0-9a-f]+ <[^>]*> 476affff 	bz\.d	\$w10,[0-9a-f]+ <[^>]*>
+[	]*[0-9a-f]+: R_MIPS_PC16	external_label
+[0-9a-f]+ <[^>]*> 00000000 	nop
+[0-9a-f]+ <[^>]*> 7b1002c7 	ldi\.b	\$w11,-512
+[0-9a-f]+ <[^>]*> 7b0ffb07 	ldi\.b	\$w12,511
+[0-9a-f]+ <[^>]*> 7b300347 	ldi\.h	\$w13,-512
+[0-9a-f]+ <[^>]*> 7b2ffb87 	ldi\.h	\$w14,511
+[0-9a-f]+ <[^>]*> 7b5003c7 	ldi\.w	\$w15,-512
+[0-9a-f]+ <[^>]*> 7b4ffc07 	ldi\.w	\$w16,511
+[0-9a-f]+ <[^>]*> 7b700447 	ldi\.d	\$w17,-512
+[0-9a-f]+ <[^>]*> 7b6ffc87 	ldi\.d	\$w18,511
+[0-9a-f]+ <[^>]*> 7815a4da 	fcaf\.w	\$w19,\$w20,\$w21
+[0-9a-f]+ <[^>]*> 7838bd9a 	fcaf\.d	\$w22,\$w23,\$w24
+[0-9a-f]+ <[^>]*> 785bd65a 	fcun\.w	\$w25,\$w26,\$w27
+[0-9a-f]+ <[^>]*> 787eef1a 	fcun\.d	\$w28,\$w29,\$w30
+[0-9a-f]+ <[^>]*> 788107da 	fceq\.w	\$w31,\$w0,\$w1
+[0-9a-f]+ <[^>]*> 78a4189a 	fceq\.d	\$w2,\$w3,\$w4
+[0-9a-f]+ <[^>]*> 78c7315a 	fcueq\.w	\$w5,\$w6,\$w7
+[0-9a-f]+ <[^>]*> 78ea4a1a 	fcueq\.d	\$w8,\$w9,\$w10
+[0-9a-f]+ <[^>]*> 790d62da 	fclt\.w	\$w11,\$w12,\$w13
+[0-9a-f]+ <[^>]*> 79307b9a 	fclt\.d	\$w14,\$w15,\$w16
+[0-9a-f]+ <[^>]*> 7953945a 	fcult\.w	\$w17,\$w18,\$w19
+[0-9a-f]+ <[^>]*> 7976ad1a 	fcult\.d	\$w20,\$w21,\$w22
+[0-9a-f]+ <[^>]*> 7999c5da 	fcle\.w	\$w23,\$w24,\$w25
+[0-9a-f]+ <[^>]*> 79bcde9a 	fcle\.d	\$w26,\$w27,\$w28
+[0-9a-f]+ <[^>]*> 79dff75a 	fcule\.w	\$w29,\$w30,\$w31
+[0-9a-f]+ <[^>]*> 79e2081a 	fcule\.d	\$w0,\$w1,\$w2
+[0-9a-f]+ <[^>]*> 7a0520da 	fsaf\.w	\$w3,\$w4,\$w5
+[0-9a-f]+ <[^>]*> 7a28399a 	fsaf\.d	\$w6,\$w7,\$w8
+[0-9a-f]+ <[^>]*> 7a4b525a 	fsun\.w	\$w9,\$w10,\$w11
+[0-9a-f]+ <[^>]*> 7a6e6b1a 	fsun\.d	\$w12,\$w13,\$w14
+[0-9a-f]+ <[^>]*> 7a9183da 	fseq\.w	\$w15,\$w16,\$w17
+[0-9a-f]+ <[^>]*> 7ab49c9a 	fseq\.d	\$w18,\$w19,\$w20
+[0-9a-f]+ <[^>]*> 7ad7b55a 	fsueq\.w	\$w21,\$w22,\$w23
+[0-9a-f]+ <[^>]*> 7aface1a 	fsueq\.d	\$w24,\$w25,\$w26
+[0-9a-f]+ <[^>]*> 7b1de6da 	fslt\.w	\$w27,\$w28,\$w29
+[0-9a-f]+ <[^>]*> 7b20ff9a 	fslt\.d	\$w30,\$w31,\$w0
+[0-9a-f]+ <[^>]*> 7b43105a 	fsult\.w	\$w1,\$w2,\$w3
+[0-9a-f]+ <[^>]*> 7b66291a 	fsult\.d	\$w4,\$w5,\$w6
+[0-9a-f]+ <[^>]*> 7b8941da 	fsle\.w	\$w7,\$w8,\$w9
+[0-9a-f]+ <[^>]*> 7bac5a9a 	fsle\.d	\$w10,\$w11,\$w12
+[0-9a-f]+ <[^>]*> 7bcf735a 	fsule\.w	\$w13,\$w14,\$w15
+[0-9a-f]+ <[^>]*> 7bf28c1a 	fsule\.d	\$w16,\$w17,\$w18
+[0-9a-f]+ <[^>]*> 7815a4db 	fadd\.w	\$w19,\$w20,\$w21
+[0-9a-f]+ <[^>]*> 7838bd9b 	fadd\.d	\$w22,\$w23,\$w24
+[0-9a-f]+ <[^>]*> 785bd65b 	fsub\.w	\$w25,\$w26,\$w27
+[0-9a-f]+ <[^>]*> 787eef1b 	fsub\.d	\$w28,\$w29,\$w30
+[0-9a-f]+ <[^>]*> 788107db 	fmul\.w	\$w31,\$w0,\$w1
+[0-9a-f]+ <[^>]*> 78a4189b 	fmul\.d	\$w2,\$w3,\$w4
+[0-9a-f]+ <[^>]*> 78c7315b 	fdiv\.w	\$w5,\$w6,\$w7
+[0-9a-f]+ <[^>]*> 78ea4a1b 	fdiv\.d	\$w8,\$w9,\$w10
+[0-9a-f]+ <[^>]*> 790d62db 	fmadd\.w	\$w11,\$w12,\$w13
+[0-9a-f]+ <[^>]*> 79307b9b 	fmadd\.d	\$w14,\$w15,\$w16
+[0-9a-f]+ <[^>]*> 7953945b 	fmsub\.w	\$w17,\$w18,\$w19
+[0-9a-f]+ <[^>]*> 7976ad1b 	fmsub\.d	\$w20,\$w21,\$w22
+[0-9a-f]+ <[^>]*> 79d9c5db 	fexp2\.w	\$w23,\$w24,\$w25
+[0-9a-f]+ <[^>]*> 79fcde9b 	fexp2\.d	\$w26,\$w27,\$w28
+[0-9a-f]+ <[^>]*> 7a1ff75b 	fexdo\.h	\$w29,\$w30,\$w31
+[0-9a-f]+ <[^>]*> 7a22081b 	fexdo\.w	\$w0,\$w1,\$w2
+[0-9a-f]+ <[^>]*> 7a8520db 	ftq\.h	\$w3,\$w4,\$w5
+[0-9a-f]+ <[^>]*> 7aa8399b 	ftq\.w	\$w6,\$w7,\$w8
+[0-9a-f]+ <[^>]*> 7b0b525b 	fmin\.w	\$w9,\$w10,\$w11
+[0-9a-f]+ <[^>]*> 7b2e6b1b 	fmin\.d	\$w12,\$w13,\$w14
+[0-9a-f]+ <[^>]*> 7b5183db 	fmin_a\.w	\$w15,\$w16,\$w17
+[0-9a-f]+ <[^>]*> 7b749c9b 	fmin_a\.d	\$w18,\$w19,\$w20
+[0-9a-f]+ <[^>]*> 7b97b55b 	fmax\.w	\$w21,\$w22,\$w23
+[0-9a-f]+ <[^>]*> 7bbace1b 	fmax\.d	\$w24,\$w25,\$w26
+[0-9a-f]+ <[^>]*> 7bdde6db 	fmax_a\.w	\$w27,\$w28,\$w29
+[0-9a-f]+ <[^>]*> 7be0ff9b 	fmax_a\.d	\$w30,\$w31,\$w0
+[0-9a-f]+ <[^>]*> 7843105c 	fcor\.w	\$w1,\$w2,\$w3
+[0-9a-f]+ <[^>]*> 7866291c 	fcor\.d	\$w4,\$w5,\$w6
+[0-9a-f]+ <[^>]*> 788941dc 	fcune\.w	\$w7,\$w8,\$w9
+[0-9a-f]+ <[^>]*> 78ac5a9c 	fcune\.d	\$w10,\$w11,\$w12
+[0-9a-f]+ <[^>]*> 78cf735c 	fcne\.w	\$w13,\$w14,\$w15
+[0-9a-f]+ <[^>]*> 78f28c1c 	fcne\.d	\$w16,\$w17,\$w18
+[0-9a-f]+ <[^>]*> 7915a4dc 	mul_q\.h	\$w19,\$w20,\$w21
+[0-9a-f]+ <[^>]*> 7938bd9c 	mul_q\.w	\$w22,\$w23,\$w24
+[0-9a-f]+ <[^>]*> 795bd65c 	madd_q\.h	\$w25,\$w26,\$w27
+[0-9a-f]+ <[^>]*> 797eef1c 	madd_q\.w	\$w28,\$w29,\$w30
+[0-9a-f]+ <[^>]*> 798107dc 	msub_q\.h	\$w31,\$w0,\$w1
+[0-9a-f]+ <[^>]*> 79a4189c 	msub_q\.w	\$w2,\$w3,\$w4
+[0-9a-f]+ <[^>]*> 7a47315c 	fsor\.w	\$w5,\$w6,\$w7
+[0-9a-f]+ <[^>]*> 7a6a4a1c 	fsor\.d	\$w8,\$w9,\$w10
+[0-9a-f]+ <[^>]*> 7a8d62dc 	fsune\.w	\$w11,\$w12,\$w13
+[0-9a-f]+ <[^>]*> 7ab07b9c 	fsune\.d	\$w14,\$w15,\$w16
+[0-9a-f]+ <[^>]*> 7ad3945c 	fsne\.w	\$w17,\$w18,\$w19
+[0-9a-f]+ <[^>]*> 7af6ad1c 	fsne\.d	\$w20,\$w21,\$w22
+[0-9a-f]+ <[^>]*> 7b19c5dc 	mulr_q\.h	\$w23,\$w24,\$w25
+[0-9a-f]+ <[^>]*> 7b3cde9c 	mulr_q\.w	\$w26,\$w27,\$w28
+[0-9a-f]+ <[^>]*> 7b5ff75c 	maddr_q\.h	\$w29,\$w30,\$w31
+[0-9a-f]+ <[^>]*> 7b62081c 	maddr_q\.w	\$w0,\$w1,\$w2
+[0-9a-f]+ <[^>]*> 7b8520dc 	msubr_q\.h	\$w3,\$w4,\$w5
+[0-9a-f]+ <[^>]*> 7ba8399c 	msubr_q\.w	\$w6,\$w7,\$w8
+[0-9a-f]+ <[^>]*> 7b20525e 	fclass\.w	\$w9,\$w10
+[0-9a-f]+ <[^>]*> 7b2162de 	fclass\.d	\$w11,\$w12
+[0-9a-f]+ <[^>]*> 7b22735e 	ftrunc_s\.w	\$w13,\$w14
+[0-9a-f]+ <[^>]*> 7b2383de 	ftrunc_s\.d	\$w15,\$w16
+[0-9a-f]+ <[^>]*> 7b24945e 	ftrunc_u\.w	\$w17,\$w18
+[0-9a-f]+ <[^>]*> 7b25a4de 	ftrunc_u\.d	\$w19,\$w20
+[0-9a-f]+ <[^>]*> 7b26b55e 	fsqrt\.w	\$w21,\$w22
+[0-9a-f]+ <[^>]*> 7b27c5de 	fsqrt\.d	\$w23,\$w24
+[0-9a-f]+ <[^>]*> 7b28d65e 	frsqrt\.w	\$w25,\$w26
+[0-9a-f]+ <[^>]*> 7b29e6de 	frsqrt\.d	\$w27,\$w28
+[0-9a-f]+ <[^>]*> 7b2af75e 	frcp\.w	\$w29,\$w30
+[0-9a-f]+ <[^>]*> 7b2b07de 	frcp\.d	\$w31,\$w0
+[0-9a-f]+ <[^>]*> 7b2c105e 	frint\.w	\$w1,\$w2
+[0-9a-f]+ <[^>]*> 7b2d20de 	frint\.d	\$w3,\$w4
+[0-9a-f]+ <[^>]*> 7b2e315e 	flog2\.w	\$w5,\$w6
+[0-9a-f]+ <[^>]*> 7b2f41de 	flog2\.d	\$w7,\$w8
+[0-9a-f]+ <[^>]*> 7b30525e 	fexupl\.w	\$w9,\$w10
+[0-9a-f]+ <[^>]*> 7b3162de 	fexupl\.d	\$w11,\$w12
+[0-9a-f]+ <[^>]*> 7b32735e 	fexupr\.w	\$w13,\$w14
+[0-9a-f]+ <[^>]*> 7b3383de 	fexupr\.d	\$w15,\$w16
+[0-9a-f]+ <[^>]*> 7b34945e 	ffql\.w	\$w17,\$w18
+[0-9a-f]+ <[^>]*> 7b35a4de 	ffql\.d	\$w19,\$w20
+[0-9a-f]+ <[^>]*> 7b36b55e 	ffqr\.w	\$w21,\$w22
+[0-9a-f]+ <[^>]*> 7b37c5de 	ffqr\.d	\$w23,\$w24
+[0-9a-f]+ <[^>]*> 7b38d65e 	ftint_s\.w	\$w25,\$w26
+[0-9a-f]+ <[^>]*> 7b39e6de 	ftint_s\.d	\$w27,\$w28
+[0-9a-f]+ <[^>]*> 7b3af75e 	ftint_u\.w	\$w29,\$w30
+[0-9a-f]+ <[^>]*> 7b3b07de 	ftint_u\.d	\$w31,\$w0
+[0-9a-f]+ <[^>]*> 7b3c105e 	ffint_s\.w	\$w1,\$w2
+[0-9a-f]+ <[^>]*> 7b3d20de 	ffint_s\.d	\$w3,\$w4
+[0-9a-f]+ <[^>]*> 7b3e315e 	ffint_u\.w	\$w5,\$w6
+[0-9a-f]+ <[^>]*> 7b3f41de 	ffint_u\.d	\$w7,\$w8
+[0-9a-f]+ <[^>]*> 783e4819 	ctcmsa	msa_ir,t1
+[0-9a-f]+ <[^>]*> 783e5059 	ctcmsa	msa_csr,t2
+[0-9a-f]+ <[^>]*> 783e5899 	ctcmsa	msa_access,t3
+[0-9a-f]+ <[^>]*> 783e60d9 	ctcmsa	msa_save,t4
+[0-9a-f]+ <[^>]*> 787e0359 	cfcmsa	t5,msa_ir
+[0-9a-f]+ <[^>]*> 787e0b99 	cfcmsa	t6,msa_csr
+[0-9a-f]+ <[^>]*> 787e13d9 	cfcmsa	t7,msa_access
+[0-9a-f]+ <[^>]*> 787e1c19 	cfcmsa	s0,msa_save
+[0-9a-f]+ <[^>]*> 78be9459 	move\.v	\$w17,\$w18
+[0-9a-f]+ <[^>]*> 02959805 	lsa	s3,s4,s5,0x1
+[0-9a-f]+ <[^>]*> 02f8b0c5 	lsa	s6,s7,t8,0x4
+	\.\.\.
diff --git a/gas/testsuite/gas/mips/mipsr6@pref.d b/gas/testsuite/gas/mips/mipsr6@pref.d
new file mode 100644
index 00000000000..a6446655a98
--- /dev/null
+++ b/gas/testsuite/gas/mips/mipsr6@pref.d
@@ -0,0 +1,13 @@
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS PREF instruction
+#as: -32 --defsym tpref=1
+#source: cache.s
+
+# Check MIPS PREF instruction assembly.
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 7c457fb5 	pref	0x5,255\(v0\)
+[0-9a-f]+ <[^>]*> 7c658035 	pref	0x5,-256\(v1\)
+	\.\.\.
diff --git a/gas/testsuite/gas/mips/mipsr6@relax-swap3.d b/gas/testsuite/gas/mips/mipsr6@relax-swap3.d
new file mode 100644
index 00000000000..a848901d99e
--- /dev/null
+++ b/gas/testsuite/gas/mips/mipsr6@relax-swap3.d
@@ -0,0 +1,22 @@
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS relaxed macro with branch swapping
+#as: -32
+#source: relax-swap3.s
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 3c020000 	lui	v0,0x0
+[ 	]*[0-9a-f]+: R_MIPS_HI16	bar
+[0-9a-f]+ <[^>]*> 24420000 	addiu	v0,v0,0
+[ 	]*[0-9a-f]+: R_MIPS_LO16	bar
+[0-9a-f]+ <[^>]*> 00600009 	jr	v1
+[0-9a-f]+ <[^>]*> 00000000 	nop
+[0-9a-f]+ <[^>]*> 3c020000 	lui	v0,0x0
+[ 	]*[0-9a-f]+: R_MIPS_HI16	bar
+[0-9a-f]+ <[^>]*> 24420000 	addiu	v0,v0,0
+[ 	]*[0-9a-f]+: R_MIPS_LO16	bar
+[0-9a-f]+ <[^>]*> 1060ffff 	beqz	v1,[0-9a-f]+ <[^>]*>
+[ 	]*[0-9a-f]+: R_MIPS_PC16	.L.1
+[0-9a-f]+ <[^>]*> 00000000 	nop
+	\.\.\.
diff --git a/gas/testsuite/gas/mips/r6-64-n32.d b/gas/testsuite/gas/mips/r6-64-n32.d
new file mode 100644
index 00000000000..6d471c658d9
--- /dev/null
+++ b/gas/testsuite/gas/mips/r6-64-n32.d
@@ -0,0 +1,61 @@
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS MIPSR6 64 instructions
+#as: -n32
+#source: r6-64.s
+
+# Check MIPSR6 64 instructions
+
+.*: +file format .*mips.*
+
+Disassembly of section .text:
+0+0000 <[^>]*> 0064109c 	dmul	v0,v1,a0
+0+0004 <[^>]*> 006410dc 	dmuh	v0,v1,a0
+0+0008 <[^>]*> 0064109e 	ddiv	v0,v1,a0
+0+000c <[^>]*> 0064109d 	dmulu	v0,v1,a0
+0+0010 <[^>]*> 006410dd 	dmuhu	v0,v1,a0
+0+0014 <[^>]*> 006410de 	dmod	v0,v1,a0
+0+0018 <[^>]*> 0064109f 	ddivu	v0,v1,a0
+0+001c <[^>]*> 006410df 	dmodu	v0,v1,a0
+0+0020 <[^>]*> 00641015 	dlsa	v0,v1,a0,0x1
+0+0024 <[^>]*> 006410d5 	dlsa	v0,v1,a0,0x4
+0+0028 <[^>]*> 00601052 	dclz	v0,v1
+0+002c <[^>]*> 00601053 	dclo	v0,v1
+0+0030 <[^>]*> 7c628037 	lld	v0,-256\(v1\)
+0+0034 <[^>]*> 7c627fb7 	lld	v0,255\(v1\)
+0+0038 <[^>]*> 7c628027 	scd	v0,-256\(v1\)
+0+003c <[^>]*> 7c627fa7 	scd	v0,255\(v1\)
+0+0040 <[^>]*> 7c432224 	dalign	a0,v0,v1,0
+0+0044 <[^>]*> 7c432264 	dalign	a0,v0,v1,1
+0+0048 <[^>]*> 7c4322a4 	dalign	a0,v0,v1,2
+0+004c <[^>]*> 7c4322e4 	dalign	a0,v0,v1,3
+0+0050 <[^>]*> 7c432324 	dalign	a0,v0,v1,4
+0+0054 <[^>]*> 7c432364 	dalign	a0,v0,v1,5
+0+0058 <[^>]*> 7c4323a4 	dalign	a0,v0,v1,6
+0+005c <[^>]*> 7c4323e4 	dalign	a0,v0,v1,7
+0+0060 <[^>]*> 7c022024 	dbitswap	a0,v0
+0+0064 <[^>]*> 7443ffff 	daui	v1,v0,0xffff
+0+0068 <[^>]*> 0466ffff 	dahi	v1,v1,0xffff
+0+006c <[^>]*> 047effff 	dati	v1,v1,0xffff
+0+0070 <[^>]*> ec900000 	lwupc	a0,00000070 <[^>]*>
+[	]*70: R_MIPS_PC19_S2	\.L1.1
+0+0074 <[^>]*> ec900000 	lwupc	a0,00000074 <[^>]*>
+[	]*74: R_MIPS_PC19_S2	L0.-0x100000
+0+0078 <[^>]*> ec900000 	lwupc	a0,00000078 <[^>]*>
+[	]*78: R_MIPS_PC19_S2	L0.+0xffffc
+0+007c <[^>]*> ec940000 	lwupc	a0,fff0007c <[^>]*>
+0+0080 <[^>]*> ec93ffff 	lwupc	a0,0010007c <[^>]*>
+0+0084 <[^>]*> 00000000 	nop
+0+0088 <[^>]*> ec980000 	ldpc	a0,00000088 <[^>]*>
+[	]*88: R_MIPS_PC18_S3	\.L1.1
+0+008c <[^>]*> 00000000 	nop
+0+0090 <[^>]*> ec980000 	ldpc	a0,00000090 <[^>]*>
+[	]*90: R_MIPS_PC18_S3	L0.-0x100000
+0+0094 <[^>]*> 00000000 	nop
+0+0098 <[^>]*> ec980000 	ldpc	a0,00000098 <[^>]*>
+[	]*98: R_MIPS_PC18_S3	L0.+0xffff8
+0+009c <[^>]*> 00000000 	nop
+0+00a0 <[^>]*> ec9a0000 	ldpc	a0,fff000a0 <[^>]*>
+0+00a4 <[^>]*> 00000000 	nop
+0+00a8 <[^>]*> ec99ffff 	ldpc	a0,001000a0 <[^>]*>
+0+00ac <[^>]*> 00000000 	nop
+	\.\.\.
diff --git a/gas/testsuite/gas/mips/r6-64-n64.d b/gas/testsuite/gas/mips/r6-64-n64.d
new file mode 100644
index 00000000000..22028208145
--- /dev/null
+++ b/gas/testsuite/gas/mips/r6-64-n64.d
@@ -0,0 +1,73 @@
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS MIPSR6 64 instructions
+#as: -64
+#source: r6-64.s
+
+# Check MIPSR6 64 instructions
+
+.*: +file format .*mips.*
+
+Disassembly of section .text:
+0+0000 <[^>]*> 0064109c 	dmul	v0,v1,a0
+0+0004 <[^>]*> 006410dc 	dmuh	v0,v1,a0
+0+0008 <[^>]*> 0064109e 	ddiv	v0,v1,a0
+0+000c <[^>]*> 0064109d 	dmulu	v0,v1,a0
+0+0010 <[^>]*> 006410dd 	dmuhu	v0,v1,a0
+0+0014 <[^>]*> 006410de 	dmod	v0,v1,a0
+0+0018 <[^>]*> 0064109f 	ddivu	v0,v1,a0
+0+001c <[^>]*> 006410df 	dmodu	v0,v1,a0
+0+0020 <[^>]*> 00641015 	dlsa	v0,v1,a0,0x1
+0+0024 <[^>]*> 006410d5 	dlsa	v0,v1,a0,0x4
+0+0028 <[^>]*> 00601052 	dclz	v0,v1
+0+002c <[^>]*> 00601053 	dclo	v0,v1
+0+0030 <[^>]*> 7c628037 	lld	v0,-256\(v1\)
+0+0034 <[^>]*> 7c627fb7 	lld	v0,255\(v1\)
+0+0038 <[^>]*> 7c628027 	scd	v0,-256\(v1\)
+0+003c <[^>]*> 7c627fa7 	scd	v0,255\(v1\)
+0+0040 <[^>]*> 7c432224 	dalign	a0,v0,v1,0
+0+0044 <[^>]*> 7c432264 	dalign	a0,v0,v1,1
+0+0048 <[^>]*> 7c4322a4 	dalign	a0,v0,v1,2
+0+004c <[^>]*> 7c4322e4 	dalign	a0,v0,v1,3
+0+0050 <[^>]*> 7c432324 	dalign	a0,v0,v1,4
+0+0054 <[^>]*> 7c432364 	dalign	a0,v0,v1,5
+0+0058 <[^>]*> 7c4323a4 	dalign	a0,v0,v1,6
+0+005c <[^>]*> 7c4323e4 	dalign	a0,v0,v1,7
+0+0060 <[^>]*> 7c022024 	dbitswap	a0,v0
+0+0064 <[^>]*> 7443ffff 	daui	v1,v0,0xffff
+0+0068 <[^>]*> 0466ffff 	dahi	v1,v1,0xffff
+0+006c <[^>]*> 047effff 	dati	v1,v1,0xffff
+0+0070 <[^>]*> ec900000 	lwupc	a0,0+0000070 <[^>]*>
+[	]*70: R_MIPS_PC19_S2	\.L1.1
+[	]*70: R_MIPS_NONE	\*ABS\*
+[	]*70: R_MIPS_NONE	\*ABS\*
+0+0074 <[^>]*> ec900000 	lwupc	a0,0+0000074 <[^>]*>
+[	]*74: R_MIPS_PC19_S2	L0.-0x100000
+[	]*74: R_MIPS_NONE	\*ABS\*-0x100000
+[	]*74: R_MIPS_NONE	\*ABS\*-0x100000
+0+0078 <[^>]*> ec900000 	lwupc	a0,0+0000078 <[^>]*>
+[	]*78: R_MIPS_PC19_S2	L0.\+0xffffc
+[	]*78: R_MIPS_NONE	\*ABS\*\+0xffffc
+[	]*78: R_MIPS_NONE	\*ABS\*\+0xffffc
+0+007c <[^>]*> ec940000 	lwupc	a0,f+ff0007c <[^>]*>
+0+0080 <[^>]*> ec93ffff 	lwupc	a0,0+010007c <[^>]*>
+0+0084 <[^>]*> 00000000 	nop
+0+0088 <[^>]*> ec980000 	ldpc	a0,0+0000088 <[^>]*>
+[	]*88: R_MIPS_PC18_S3	\.L1.1
+[	]*88: R_MIPS_NONE	\*ABS\*
+[	]*88: R_MIPS_NONE	\*ABS\*
+0+008c <[^>]*> 00000000 	nop
+0+0090 <[^>]*> ec980000 	ldpc	a0,0+0000090 <[^>]*>
+[	]*90: R_MIPS_PC18_S3	L0.-0x100000
+[	]*90: R_MIPS_NONE	\*ABS\*-0x100000
+[	]*90: R_MIPS_NONE	\*ABS\*-0x100000
+0+0094 <[^>]*> 00000000 	nop
+0+0098 <[^>]*> ec980000 	ldpc	a0,0+0000098 <[^>]*>
+[	]*98: R_MIPS_PC18_S3	L0.\+0xffff8
+[	]*98: R_MIPS_NONE	\*ABS\*\+0xffff8
+[	]*98: R_MIPS_NONE	\*ABS\*\+0xffff8
+0+009c <[^>]*> 00000000 	nop
+0+00a0 <[^>]*> ec9a0000 	ldpc	a0,f+ff000a0 <[^>]*>
+0+00a4 <[^>]*> 00000000 	nop
+0+00a8 <[^>]*> ec99ffff 	ldpc	a0,0+01000a0 <[^>]*>
+0+00ac <[^>]*> 00000000 	nop
+	\.\.\.
diff --git a/gas/testsuite/gas/mips/r6-64-removed.l b/gas/testsuite/gas/mips/r6-64-removed.l
new file mode 100644
index 00000000000..a4208ba500a
--- /dev/null
+++ b/gas/testsuite/gas/mips/r6-64-removed.l
@@ -0,0 +1,10 @@
+.*: Assembler messages:
+.*:2: Error: opcode not supported on this processor: .* \(.*\) `daddi \$23,\$24,1023'
+.*:3: Error: invalid operands `ddiv \$2,\$4'
+.*:4: Error: invalid operands `ddivu \$2,\$4'
+.*:5: Error: opcode not supported on this processor: .* \(.*\) `dmult \$2,\$3'
+.*:6: Error: opcode not supported on this processor: .* \(.*\) `dmultu \$2,\$3'
+.*:7: Error: opcode not supported on this processor: .* \(.*\) `ldl \$2,1\(\$3\)'
+.*:8: Error: opcode not supported on this processor: .* \(.*\) `ldr \$2,1\(\$3\)'
+.*:9: Error: opcode not supported on this processor: .* \(.*\) `sdl \$2,1\(\$3\)'
+.*:10: Error: opcode not supported on this processor: .* \(.*\) `sdr \$2,1\(\$3\)'
diff --git a/gas/testsuite/gas/mips/r6-64-removed.s b/gas/testsuite/gas/mips/r6-64-removed.s
new file mode 100644
index 00000000000..77b8b0433ad
--- /dev/null
+++ b/gas/testsuite/gas/mips/r6-64-removed.s
@@ -0,0 +1,10 @@
+	.set	reorder
+	daddi	$23,$24,1023
+	ddiv $2, $4
+	ddivu $2, $4
+	dmult	$2,$3
+	dmultu	$2,$3
+	ldl	$2, 1($3)
+	ldr	$2, 1($3)
+	sdl	$2, 1($3)
+	sdr	$2, 1($3)
diff --git a/gas/testsuite/gas/mips/r6-64.s b/gas/testsuite/gas/mips/r6-64.s
new file mode 100644
index 00000000000..7a97ad2490c
--- /dev/null
+++ b/gas/testsuite/gas/mips/r6-64.s
@@ -0,0 +1,59 @@
+	.text
+	dmul	$2,$3,$4
+	dmuh	$2,$3,$4
+	ddiv	$2,$3,$4
+	dmulu	$2,$3,$4
+	dmuhu	$2,$3,$4
+	dmod	$2,$3,$4
+	ddivu	$2,$3,$4
+	dmodu	$2,$3,$4
+
+	dlsa	$2,$3,$4,1
+	dlsa	$2,$3,$4,4
+
+	dclz	$2,$3
+	dclo	$2,$3
+
+	lld	$2,-256($3)
+	lld	$2,255($3)
+	scd	$2,-256($3)
+	scd	$2,255($3)
+
+        dalign   $4, $2, $3, 0
+        dalign   $4, $2, $3, 1
+        dalign   $4, $2, $3, 2
+        dalign   $4, $2, $3, 3
+        dalign   $4, $2, $3, 4
+        dalign   $4, $2, $3, 5
+        dalign   $4, $2, $3, 6
+        dalign   $4, $2, $3, 7
+
+        dbitswap  $4, $2
+
+        daui      $3, $2, 0xffff
+        dahi      $3, $3, 0xffff
+        dati      $3, $3, 0xffff
+
+        lwupc      $4, 1f
+        lwupc      $4, .+(-262144 << 2)
+        lwupc      $4, .+(262143 << 2)
+        lwu      $4, (-262144 << 2)($pc)
+        lwu      $4, (262143 << 2)($pc)
+
+        .align 3
+        ldpc     $4, 1f
+        .align 3
+        ldpc     $4, .+(-131072 << 3)
+        .align 3
+        ldpc     $4, .+(131071 << 3)
+        .align 3
+        ld     $4, (-131072 << 3)($pc)
+        .align 3
+        ld     $4, (131071 << 3)($pc)
+        .align 3
+1:
+        nop
+
+# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
+	.align  2
+	.space  8
diff --git a/gas/testsuite/gas/mips/r6-attr-none-double.d b/gas/testsuite/gas/mips/r6-attr-none-double.d
new file mode 100644
index 00000000000..2a9fd367185
--- /dev/null
+++ b/gas/testsuite/gas/mips/r6-attr-none-double.d
@@ -0,0 +1,22 @@
+#PROG: readelf
+#source: empty.s
+#readelf: -A
+#name: MIPS infer fpabi (double-precision)
+
+Attribute Section: gnu
+File Attributes
+  Tag_GNU_MIPS_ABI_FP: Hard float \(32-bit CPU, 64-bit FPU\)
+
+MIPS ABI Flags Version: 0
+
+ISA: MIPS.*
+GPR size: .*
+CPR1 size: .*
+CPR2 size: 0
+FP ABI: Hard float \(32-bit CPU, 64-bit FPU\)
+ISA Extension: .*
+ASEs:
+#...
+FLAGS 1: 0000000.
+FLAGS 2: 00000000
+
diff --git a/gas/testsuite/gas/mips/r6-n32.d b/gas/testsuite/gas/mips/r6-n32.d
new file mode 100644
index 00000000000..4df4f3128ad
--- /dev/null
+++ b/gas/testsuite/gas/mips/r6-n32.d
@@ -0,0 +1,493 @@
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS MIPSR6 instructions
+#as: -n32
+#source: r6.s
+
+# Check MIPSR6 instructions
+
+.*: +file format .*mips.*
+
+Disassembly of section .text:
+0+0000 <[^>]*> 46020818 	maddf.s	\$f0,\$f1,\$f2
+0+0004 <[^>]*> 462520d8 	maddf.d	\$f3,\$f4,\$f5
+0+0008 <[^>]*> 46083999 	msubf.s	\$f6,\$f7,\$f8
+0+000c <[^>]*> 462b5259 	msubf.d	\$f9,\$f10,\$f11
+0+0010 <[^>]*> 46820800 	cmp.af.s	\$f0,\$f1,\$f2
+0+0014 <[^>]*> 46a20800 	cmp.af.d	\$f0,\$f1,\$f2
+0+0018 <[^>]*> 46820801 	cmp.un.s	\$f0,\$f1,\$f2
+0+001c <[^>]*> 46a20801 	cmp.un.d	\$f0,\$f1,\$f2
+0+0020 <[^>]*> 46820802 	cmp.eq.s	\$f0,\$f1,\$f2
+0+0024 <[^>]*> 46a20802 	cmp.eq.d	\$f0,\$f1,\$f2
+0+0028 <[^>]*> 46820803 	cmp.ueq.s	\$f0,\$f1,\$f2
+0+002c <[^>]*> 46a20803 	cmp.ueq.d	\$f0,\$f1,\$f2
+0+0030 <[^>]*> 46820804 	cmp.lt.s	\$f0,\$f1,\$f2
+0+0034 <[^>]*> 46a20804 	cmp.lt.d	\$f0,\$f1,\$f2
+0+0038 <[^>]*> 46820805 	cmp.ult.s	\$f0,\$f1,\$f2
+0+003c <[^>]*> 46a20805 	cmp.ult.d	\$f0,\$f1,\$f2
+0+0040 <[^>]*> 46820806 	cmp.le.s	\$f0,\$f1,\$f2
+0+0044 <[^>]*> 46a20806 	cmp.le.d	\$f0,\$f1,\$f2
+0+0048 <[^>]*> 46820807 	cmp.ule.s	\$f0,\$f1,\$f2
+0+004c <[^>]*> 46a20807 	cmp.ule.d	\$f0,\$f1,\$f2
+0+0050 <[^>]*> 46820808 	cmp.saf.s	\$f0,\$f1,\$f2
+0+0054 <[^>]*> 46a20808 	cmp.saf.d	\$f0,\$f1,\$f2
+0+0058 <[^>]*> 46820809 	cmp.sun.s	\$f0,\$f1,\$f2
+0+005c <[^>]*> 46a20809 	cmp.sun.d	\$f0,\$f1,\$f2
+0+0060 <[^>]*> 4682080a 	cmp.seq.s	\$f0,\$f1,\$f2
+0+0064 <[^>]*> 46a2080a 	cmp.seq.d	\$f0,\$f1,\$f2
+0+0068 <[^>]*> 4682080b 	cmp.sueq.s	\$f0,\$f1,\$f2
+0+006c <[^>]*> 46a2080b 	cmp.sueq.d	\$f0,\$f1,\$f2
+0+0070 <[^>]*> 4682080c 	cmp.slt.s	\$f0,\$f1,\$f2
+0+0074 <[^>]*> 46a2080c 	cmp.slt.d	\$f0,\$f1,\$f2
+0+0078 <[^>]*> 4682080d 	cmp.sult.s	\$f0,\$f1,\$f2
+0+007c <[^>]*> 46a2080d 	cmp.sult.d	\$f0,\$f1,\$f2
+0+0080 <[^>]*> 4682080e 	cmp.sle.s	\$f0,\$f1,\$f2
+0+0084 <[^>]*> 46a2080e 	cmp.sle.d	\$f0,\$f1,\$f2
+0+0088 <[^>]*> 4682080f 	cmp.sule.s	\$f0,\$f1,\$f2
+0+008c <[^>]*> 46a2080f 	cmp.sule.d	\$f0,\$f1,\$f2
+0+0090 <[^>]*> 46820811 	cmp.or.s	\$f0,\$f1,\$f2
+0+0094 <[^>]*> 46a20811 	cmp.or.d	\$f0,\$f1,\$f2
+0+0098 <[^>]*> 46820812 	cmp.une.s	\$f0,\$f1,\$f2
+0+009c <[^>]*> 46a20812 	cmp.une.d	\$f0,\$f1,\$f2
+0+00a0 <[^>]*> 46820813 	cmp.ne.s	\$f0,\$f1,\$f2
+0+00a4 <[^>]*> 46a20813 	cmp.ne.d	\$f0,\$f1,\$f2
+0+00a8 <[^>]*> 46820819 	cmp.sor.s	\$f0,\$f1,\$f2
+0+00ac <[^>]*> 46a20819 	cmp.sor.d	\$f0,\$f1,\$f2
+0+00b0 <[^>]*> 4682081a 	cmp.sune.s	\$f0,\$f1,\$f2
+0+00b4 <[^>]*> 46a2081a 	cmp.sune.d	\$f0,\$f1,\$f2
+0+00b8 <[^>]*> 4682081b 	cmp.sne.s	\$f0,\$f1,\$f2
+0+00bc <[^>]*> 46a2081b 	cmp.sne.d	\$f0,\$f1,\$f2
+0+00c0 <[^>]*> 45200000 	bc1eqz	\$f0,000000c4 <[^>]*>
+[	]*c0: R_MIPS_PC16	.L1.1-0x4
+0+00c4 <[^>]*> 00000000 	nop
+0+00c8 <[^>]*> 453f0000 	bc1eqz	\$f31,000000cc <[^>]*>
+[	]*c8: R_MIPS_PC16	.L1.1-0x4
+0+00cc <[^>]*> 00000000 	nop
+0+00d0 <[^>]*> 453f0000 	bc1eqz	\$f31,000000d4 <[^>]*>
+[	]*d0: R_MIPS_PC16	new-0x4
+0+00d4 <[^>]*> 00000000 	nop
+0+00d8 <[^>]*> 453f0000 	bc1eqz	\$f31,000000dc <[^>]*>
+[	]*d8: R_MIPS_PC16	external_label-0x4
+0+00dc <[^>]*> 00000000 	nop
+0+00e0 <[^>]*> 45a00000 	bc1nez	\$f0,000000e4 <[^>]*>
+[	]*e0: R_MIPS_PC16	.L1.1-0x4
+0+00e4 <[^>]*> 00000000 	nop
+0+00e8 <[^>]*> 45bf0000 	bc1nez	\$f31,000000ec <[^>]*>
+[	]*e8: R_MIPS_PC16	.L1.1-0x4
+0+00ec <[^>]*> 00000000 	nop
+0+00f0 <[^>]*> 45bf0000 	bc1nez	\$f31,000000f4 <[^>]*>
+[	]*f0: R_MIPS_PC16	new-0x4
+0+00f4 <[^>]*> 00000000 	nop
+0+00f8 <[^>]*> 45bf0000 	bc1nez	\$f31,000000fc <[^>]*>
+[	]*f8: R_MIPS_PC16	external_label-0x4
+0+00fc <[^>]*> 00000000 	nop
+0+0100 <[^>]*> 49200000 	bc2eqz	\$0,00000104 <[^>]*>
+[	]*100: R_MIPS_PC16	.L1.1-0x4
+0+0104 <[^>]*> 00000000 	nop
+0+0108 <[^>]*> 493f0000 	bc2eqz	\$31,0000010c <[^>]*>
+[	]*108: R_MIPS_PC16	.L1.1-0x4
+0+010c <[^>]*> 00000000 	nop
+0+0110 <[^>]*> 493f0000 	bc2eqz	\$31,00000114 <[^>]*>
+[	]*110: R_MIPS_PC16	new-0x4
+0+0114 <[^>]*> 00000000 	nop
+0+0118 <[^>]*> 493f0000 	bc2eqz	\$31,0000011c <[^>]*>
+[	]*118: R_MIPS_PC16	external_label-0x4
+0+011c <[^>]*> 00000000 	nop
+0+0120 <[^>]*> 49a00000 	bc2nez	\$0,00000124 <[^>]*>
+[	]*120: R_MIPS_PC16	.L1.1-0x4
+0+0124 <[^>]*> 00000000 	nop
+0+0128 <[^>]*> 49bf0000 	bc2nez	\$31,0000012c <[^>]*>
+[	]*128: R_MIPS_PC16	.L1.1-0x4
+0+012c <[^>]*> 00000000 	nop
+0+0130 <[^>]*> 49bf0000 	bc2nez	\$31,00000134 <[^>]*>
+[	]*130: R_MIPS_PC16	new-0x4
+0+0134 <[^>]*> 00000000 	nop
+0+0138 <[^>]*> 49bf0000 	bc2nez	\$31,0000013c <[^>]*>
+[	]*138: R_MIPS_PC16	external_label-0x4
+0+013c <[^>]*> 00000000 	nop
+0+0140 <[^>]*> 46020810 	sel.s	\$f0,\$f1,\$f2
+0+0144 <[^>]*> 46220810 	sel.d	\$f0,\$f1,\$f2
+0+0148 <[^>]*> 46020814 	seleqz.s	\$f0,\$f1,\$f2
+0+014c <[^>]*> 46220814 	seleqz.d	\$f0,\$f1,\$f2
+0+0150 <[^>]*> 46020817 	selnez.s	\$f0,\$f1,\$f2
+0+0154 <[^>]*> 46220817 	selnez.d	\$f0,\$f1,\$f2
+0+0158 <[^>]*> 00641035 	seleqz	v0,v1,a0
+0+015c <[^>]*> 00641037 	selnez	v0,v1,a0
+0+0160 <[^>]*> 00641098 	mul	v0,v1,a0
+0+0164 <[^>]*> 006410d8 	muh	v0,v1,a0
+0+0168 <[^>]*> 00641099 	mulu	v0,v1,a0
+0+016c <[^>]*> 006410d9 	muhu	v0,v1,a0
+0+0170 <[^>]*> 0064109a 	div	v0,v1,a0
+0+0174 <[^>]*> 006410da 	mod	v0,v1,a0
+0+0178 <[^>]*> 0064109b 	divu	v0,v1,a0
+0+017c <[^>]*> 006410db 	modu	v0,v1,a0
+0+0180 <[^>]*> 49422000 	lwc2	\$2,0\(a0\)
+0+0184 <[^>]*> 49422400 	lwc2	\$2,-1024\(a0\)
+0+0188 <[^>]*> 494223ff 	lwc2	\$2,1023\(a0\)
+0+018c <[^>]*> 49622000 	swc2	\$2,0\(a0\)
+0+0190 <[^>]*> 49622400 	swc2	\$2,-1024\(a0\)
+0+0194 <[^>]*> 496223ff 	swc2	\$2,1023\(a0\)
+0+0198 <[^>]*> 49c22000 	ldc2	\$2,0\(a0\)
+0+019c <[^>]*> 49c22400 	ldc2	\$2,-1024\(a0\)
+0+01a0 <[^>]*> 49c223ff 	ldc2	\$2,1023\(a0\)
+0+01a4 <[^>]*> 49e22000 	sdc2	\$2,0\(a0\)
+0+01a8 <[^>]*> 49e22400 	sdc2	\$2,-1024\(a0\)
+0+01ac <[^>]*> 49e223ff 	sdc2	\$2,1023\(a0\)
+0+01b0 <[^>]*> 00641005 	lsa	v0,v1,a0,0x1
+0+01b4 <[^>]*> 006410c5 	lsa	v0,v1,a0,0x4
+0+01b8 <[^>]*> 00601050 	clz	v0,v1
+0+01bc <[^>]*> 00601051 	clo	v0,v1
+0+01c0 <[^>]*> 0000000e 	sdbbp
+0+01c4 <[^>]*> 0000000e 	sdbbp
+0+01c8 <[^>]*> 0000004e 	sdbbp	0x1
+0+01cc <[^>]*> 03ffffce 	sdbbp	0xfffff
+0+01d0 <[^>]*> 3c02ffff 	lui	v0,0xffff
+0+01d4 <[^>]*> 7c008035 	pref	0x0,-256\(zero\)
+0+01d8 <[^>]*> 7fff7fb5 	pref	0x1f,255\(ra\)
+0+01dc <[^>]*> 7c628036 	ll	v0,-256\(v1\)
+0+01e0 <[^>]*> 7c627fb6 	ll	v0,255\(v1\)
+0+01e4 <[^>]*> 7c628026 	sc	v0,-256\(v1\)
+0+01e8 <[^>]*> 7c627fa6 	sc	v0,255\(v1\)
+0+01ec <[^>]*> 7c608025 	cache	0x0,-256\(v1\)
+0+01f0 <[^>]*> 7c7f7fa5 	cache	0x1f,255\(v1\)
+0+01f4 <[^>]*> 7c432220 	align	a0,v0,v1,0
+0+01f8 <[^>]*> 7c432260 	align	a0,v0,v1,1
+0+01fc <[^>]*> 7c4322a0 	align	a0,v0,v1,2
+0+0200 <[^>]*> 7c4322e0 	align	a0,v0,v1,3
+0+0204 <[^>]*> 7c022020 	bitswap	a0,v0
+0+0208 <[^>]*> 20000000 	bovc	zero,zero,0000020c <[^>]*>
+[	]*208: R_MIPS_PC16	ext-0x4
+0+020c <[^>]*> 00000000 	nop
+0+0210 <[^>]*> 20400000 	bovc	v0,zero,00000214 <[^>]*>
+[	]*210: R_MIPS_PC16	ext-0x4
+0+0214 <[^>]*> 00000000 	nop
+0+0218 <[^>]*> 20400000 	bovc	v0,zero,0000021c <[^>]*>
+[	]*218: R_MIPS_PC16	ext-0x4
+0+021c <[^>]*> 00000000 	nop
+0+0220 <[^>]*> 20820000 	bovc	a0,v0,00000224 <[^>]*>
+[	]*220: R_MIPS_PC16	ext-0x4
+0+0224 <[^>]*> 00000000 	nop
+0+0228 <[^>]*> 20820000 	bovc	a0,v0,0000022c <[^>]*>
+[	]*228: R_MIPS_PC16	ext-0x4
+0+022c <[^>]*> 00000000 	nop
+0+0230 <[^>]*> 20820000 	bovc	a0,v0,00000234 <[^>]*>
+[	]*230: R_MIPS_PC16	L0.-0x20000
+0+0234 <[^>]*> 00000000 	nop
+0+0238 <[^>]*> 20820000 	bovc	a0,v0,0000023c <[^>]*>
+[	]*238: R_MIPS_PC16	L0.+0x1fffc
+0+023c <[^>]*> 00000000 	nop
+0+0240 <[^>]*> 20820000 	bovc	a0,v0,00000244 <[^>]*>
+[	]*240: R_MIPS_PC16	.L1.2-0x4
+0+0244 <[^>]*> 00000000 	nop
+0+0248 <[^>]*> 20420000 	bovc	v0,v0,0000024c <[^>]*>
+[	]*248: R_MIPS_PC16	ext-0x4
+0+024c <[^>]*> 00000000 	nop
+0+0250 <[^>]*> 20420000 	bovc	v0,v0,00000254 <[^>]*>
+[	]*250: R_MIPS_PC16	L0.-0x20000
+0+0254 <[^>]*> 00000000 	nop
+0+0258 <[^>]*> 20020000 	beqzalc	v0,0000025c <[^>]*>
+[	]*258: R_MIPS_PC16	ext-0x4
+0+025c <[^>]*> 00000000 	nop
+0+0260 <[^>]*> 20020000 	beqzalc	v0,00000264 <[^>]*>
+[	]*260: R_MIPS_PC16	L0.-0x20000
+0+0264 <[^>]*> 00000000 	nop
+0+0268 <[^>]*> 20020000 	beqzalc	v0,0000026c <[^>]*>
+[	]*268: R_MIPS_PC16	L0.+0x1fffc
+0+026c <[^>]*> 00000000 	nop
+0+0270 <[^>]*> 20020000 	beqzalc	v0,00000274 <[^>]*>
+[	]*270: R_MIPS_PC16	.L1.2-0x4
+0+0274 <[^>]*> 00000000 	nop
+0+0278 <[^>]*> 20430000 	beqc	v0,v1,0000027c <[^>]*>
+[	]*278: R_MIPS_PC16	ext-0x4
+0+027c <[^>]*> 00000000 	nop
+0+0280 <[^>]*> 20430000 	beqc	v0,v1,00000284 <[^>]*>
+[	]*280: R_MIPS_PC16	ext-0x4
+0+0284 <[^>]*> 00000000 	nop
+0+0288 <[^>]*> 20430000 	beqc	v0,v1,0000028c <[^>]*>
+[	]*288: R_MIPS_PC16	L0.-0x20000
+0+028c <[^>]*> 00000000 	nop
+0+0290 <[^>]*> 20430000 	beqc	v0,v1,00000294 <[^>]*>
+[	]*290: R_MIPS_PC16	L0.+0x1fffc
+0+0294 <[^>]*> 00000000 	nop
+0+0298 <[^>]*> 20430000 	beqc	v0,v1,0000029c <[^>]*>
+[	]*298: R_MIPS_PC16	.L1.2-0x4
+0+029c <[^>]*> 00000000 	nop
+0+02a0 <[^>]*> 60000000 	bnvc	zero,zero,000002a4 <[^>]*>
+[	]*2a0: R_MIPS_PC16	ext-0x4
+0+02a4 <[^>]*> 00000000 	nop
+0+02a8 <[^>]*> 60400000 	bnvc	v0,zero,000002ac <[^>]*>
+[	]*2a8: R_MIPS_PC16	ext-0x4
+0+02ac <[^>]*> 00000000 	nop
+0+02b0 <[^>]*> 60400000 	bnvc	v0,zero,000002b4 <[^>]*>
+[	]*2b0: R_MIPS_PC16	ext-0x4
+0+02b4 <[^>]*> 00000000 	nop
+0+02b8 <[^>]*> 60820000 	bnvc	a0,v0,000002bc <[^>]*>
+[	]*2b8: R_MIPS_PC16	ext-0x4
+0+02bc <[^>]*> 00000000 	nop
+0+02c0 <[^>]*> 60820000 	bnvc	a0,v0,000002c4 <[^>]*>
+[	]*2c0: R_MIPS_PC16	ext-0x4
+0+02c4 <[^>]*> 00000000 	nop
+0+02c8 <[^>]*> 60820000 	bnvc	a0,v0,000002cc <[^>]*>
+[	]*2c8: R_MIPS_PC16	L0.-0x20000
+0+02cc <[^>]*> 00000000 	nop
+0+02d0 <[^>]*> 60820000 	bnvc	a0,v0,000002d4 <[^>]*>
+[	]*2d0: R_MIPS_PC16	L0.+0x1fffc
+0+02d4 <[^>]*> 00000000 	nop
+0+02d8 <[^>]*> 60820000 	bnvc	a0,v0,000002dc <[^>]*>
+[	]*2d8: R_MIPS_PC16	.L1.2-0x4
+0+02dc <[^>]*> 00000000 	nop
+0+02e0 <[^>]*> 60420000 	bnvc	v0,v0,000002e4 <[^>]*>
+[	]*2e0: R_MIPS_PC16	ext-0x4
+0+02e4 <[^>]*> 00000000 	nop
+0+02e8 <[^>]*> 60420000 	bnvc	v0,v0,000002ec <[^>]*>
+[	]*2e8: R_MIPS_PC16	L0.-0x20000
+0+02ec <[^>]*> 00000000 	nop
+0+02f0 <[^>]*> 60020000 	bnezalc	v0,000002f4 <[^>]*>
+[	]*2f0: R_MIPS_PC16	ext-0x4
+0+02f4 <[^>]*> 00000000 	nop
+0+02f8 <[^>]*> 60020000 	bnezalc	v0,000002fc <[^>]*>
+[	]*2f8: R_MIPS_PC16	L0.-0x20000
+0+02fc <[^>]*> 00000000 	nop
+0+0300 <[^>]*> 60020000 	bnezalc	v0,00000304 <[^>]*>
+[	]*300: R_MIPS_PC16	L0.+0x1fffc
+0+0304 <[^>]*> 00000000 	nop
+0+0308 <[^>]*> 60020000 	bnezalc	v0,0000030c <[^>]*>
+[	]*308: R_MIPS_PC16	.L1.2-0x4
+0+030c <[^>]*> 00000000 	nop
+0+0310 <[^>]*> 60430000 	bnec	v0,v1,00000314 <[^>]*>
+[	]*310: R_MIPS_PC16	ext-0x4
+0+0314 <[^>]*> 00000000 	nop
+0+0318 <[^>]*> 60430000 	bnec	v0,v1,0000031c <[^>]*>
+[	]*318: R_MIPS_PC16	ext-0x4
+0+031c <[^>]*> 00000000 	nop
+0+0320 <[^>]*> 60430000 	bnec	v0,v1,00000324 <[^>]*>
+[	]*320: R_MIPS_PC16	L0.-0x20000
+0+0324 <[^>]*> 00000000 	nop
+0+0328 <[^>]*> 60430000 	bnec	v0,v1,0000032c <[^>]*>
+[	]*328: R_MIPS_PC16	L0.+0x1fffc
+0+032c <[^>]*> 00000000 	nop
+0+0330 <[^>]*> 60430000 	bnec	v0,v1,00000334 <[^>]*>
+[	]*330: R_MIPS_PC16	.L1.2-0x4
+0+0334 <[^>]*> 00000000 	nop
+0+0338 <[^>]*> 58020000 	blezc	v0,0000033c <[^>]*>
+[	]*338: R_MIPS_PC16	ext-0x4
+0+033c <[^>]*> 00000000 	nop
+0+0340 <[^>]*> 58020000 	blezc	v0,00000344 <[^>]*>
+[	]*340: R_MIPS_PC16	L0.-0x20000
+0+0344 <[^>]*> 00000000 	nop
+0+0348 <[^>]*> 58020000 	blezc	v0,0000034c <[^>]*>
+[	]*348: R_MIPS_PC16	L0.+0x1fffc
+0+034c <[^>]*> 00000000 	nop
+0+0350 <[^>]*> 58020000 	blezc	v0,00000354 <[^>]*>
+[	]*350: R_MIPS_PC16	.L1.2-0x4
+0+0354 <[^>]*> 00000000 	nop
+0+0358 <[^>]*> 58420000 	bgezc	v0,0000035c <[^>]*>
+[	]*358: R_MIPS_PC16	ext-0x4
+0+035c <[^>]*> 00000000 	nop
+0+0360 <[^>]*> 58420000 	bgezc	v0,00000364 <[^>]*>
+[	]*360: R_MIPS_PC16	L0.-0x20000
+0+0364 <[^>]*> 00000000 	nop
+0+0368 <[^>]*> 58420000 	bgezc	v0,0000036c <[^>]*>
+[	]*368: R_MIPS_PC16	L0.+0x1fffc
+0+036c <[^>]*> 00000000 	nop
+0+0370 <[^>]*> 58420000 	bgezc	v0,00000374 <[^>]*>
+[	]*370: R_MIPS_PC16	.L1.2-0x4
+0+0374 <[^>]*> 00000000 	nop
+0+0378 <[^>]*> 58430000 	bgec	v0,v1,0000037c <[^>]*>
+[	]*378: R_MIPS_PC16	ext-0x4
+0+037c <[^>]*> 00000000 	nop
+0+0380 <[^>]*> 58430000 	bgec	v0,v1,00000384 <[^>]*>
+[	]*380: R_MIPS_PC16	L0.-0x20000
+0+0384 <[^>]*> 00000000 	nop
+0+0388 <[^>]*> 58430000 	bgec	v0,v1,0000038c <[^>]*>
+[	]*388: R_MIPS_PC16	L0.+0x1fffc
+0+038c <[^>]*> 00000000 	nop
+0+0390 <[^>]*> 58430000 	bgec	v0,v1,00000394 <[^>]*>
+[	]*390: R_MIPS_PC16	.L1.2-0x4
+0+0394 <[^>]*> 00000000 	nop
+0+0398 <[^>]*> 58620000 	bgec	v1,v0,0000039c <[^>]*>
+[	]*398: R_MIPS_PC16	.L1.2-0x4
+0+039c <[^>]*> 00000000 	nop
+0+03a0 <[^>]*> 5c020000 	bgtzc	v0,000003a4 <[^>]*>
+[	]*3a0: R_MIPS_PC16	ext-0x4
+0+03a4 <[^>]*> 00000000 	nop
+0+03a8 <[^>]*> 5c020000 	bgtzc	v0,000003ac <[^>]*>
+[	]*3a8: R_MIPS_PC16	L0.-0x20000
+0+03ac <[^>]*> 00000000 	nop
+0+03b0 <[^>]*> 5c020000 	bgtzc	v0,000003b4 <[^>]*>
+[	]*3b0: R_MIPS_PC16	L0.+0x1fffc
+0+03b4 <[^>]*> 00000000 	nop
+0+03b8 <[^>]*> 5c020000 	bgtzc	v0,000003bc <[^>]*>
+[	]*3b8: R_MIPS_PC16	.L1.2-0x4
+0+03bc <[^>]*> 00000000 	nop
+0+03c0 <[^>]*> 5c420000 	bltzc	v0,000003c4 <[^>]*>
+[	]*3c0: R_MIPS_PC16	ext-0x4
+0+03c4 <[^>]*> 00000000 	nop
+0+03c8 <[^>]*> 5c420000 	bltzc	v0,000003cc <[^>]*>
+[	]*3c8: R_MIPS_PC16	L0.-0x20000
+0+03cc <[^>]*> 00000000 	nop
+0+03d0 <[^>]*> 5c420000 	bltzc	v0,000003d4 <[^>]*>
+[	]*3d0: R_MIPS_PC16	L0.+0x1fffc
+0+03d4 <[^>]*> 00000000 	nop
+0+03d8 <[^>]*> 5c420000 	bltzc	v0,000003dc <[^>]*>
+[	]*3d8: R_MIPS_PC16	.L1.2-0x4
+0+03dc <[^>]*> 00000000 	nop
+0+03e0 <[^>]*> 5c430000 	bltc	v0,v1,000003e4 <[^>]*>
+[	]*3e0: R_MIPS_PC16	ext-0x4
+0+03e4 <[^>]*> 00000000 	nop
+0+03e8 <[^>]*> 5c430000 	bltc	v0,v1,000003ec <[^>]*>
+[	]*3e8: R_MIPS_PC16	L0.-0x20000
+0+03ec <[^>]*> 00000000 	nop
+0+03f0 <[^>]*> 5c430000 	bltc	v0,v1,000003f4 <[^>]*>
+[	]*3f0: R_MIPS_PC16	L0.+0x1fffc
+0+03f4 <[^>]*> 00000000 	nop
+0+03f8 <[^>]*> 5c430000 	bltc	v0,v1,000003fc <[^>]*>
+[	]*3f8: R_MIPS_PC16	.L1.2-0x4
+0+03fc <[^>]*> 00000000 	nop
+0+0400 <[^>]*> 5c620000 	bltc	v1,v0,00000404 <[^>]*>
+[	]*400: R_MIPS_PC16	.L1.2-0x4
+0+0404 <[^>]*> 00000000 	nop
+0+0408 <[^>]*> 18020000 	blezalc	v0,0000040c <[^>]*>
+[	]*408: R_MIPS_PC16	ext-0x4
+0+040c <[^>]*> 00000000 	nop
+0+0410 <[^>]*> 18020000 	blezalc	v0,00000414 <[^>]*>
+[	]*410: R_MIPS_PC16	L0.-0x20000
+0+0414 <[^>]*> 00000000 	nop
+0+0418 <[^>]*> 18020000 	blezalc	v0,0000041c <[^>]*>
+[	]*418: R_MIPS_PC16	L0.+0x1fffc
+0+041c <[^>]*> 00000000 	nop
+0+0420 <[^>]*> 18020000 	blezalc	v0,00000424 <[^>]*>
+[	]*420: R_MIPS_PC16	.L1.2-0x4
+0+0424 <[^>]*> 00000000 	nop
+0+0428 <[^>]*> 18420000 	bgezalc	v0,0000042c <[^>]*>
+[	]*428: R_MIPS_PC16	ext-0x4
+0+042c <[^>]*> 00000000 	nop
+0+0430 <[^>]*> 18420000 	bgezalc	v0,00000434 <[^>]*>
+[	]*430: R_MIPS_PC16	L0.-0x20000
+0+0434 <[^>]*> 00000000 	nop
+0+0438 <[^>]*> 18420000 	bgezalc	v0,0000043c <[^>]*>
+[	]*438: R_MIPS_PC16	L0.+0x1fffc
+0+043c <[^>]*> 00000000 	nop
+0+0440 <[^>]*> 18420000 	bgezalc	v0,00000444 <[^>]*>
+[	]*440: R_MIPS_PC16	.L1.2-0x4
+0+0444 <[^>]*> 00000000 	nop
+0+0448 <[^>]*> 18430000 	bgeuc	v0,v1,0000044c <[^>]*>
+[	]*448: R_MIPS_PC16	ext-0x4
+0+044c <[^>]*> 00000000 	nop
+0+0450 <[^>]*> 18430000 	bgeuc	v0,v1,00000454 <[^>]*>
+[	]*450: R_MIPS_PC16	L0.-0x20000
+0+0454 <[^>]*> 00000000 	nop
+0+0458 <[^>]*> 18430000 	bgeuc	v0,v1,0000045c <[^>]*>
+[	]*458: R_MIPS_PC16	L0.+0x1fffc
+0+045c <[^>]*> 00000000 	nop
+0+0460 <[^>]*> 18430000 	bgeuc	v0,v1,00000464 <[^>]*>
+[	]*460: R_MIPS_PC16	.L1.2-0x4
+0+0464 <[^>]*> 00000000 	nop
+0+0468 <[^>]*> 18620000 	bgeuc	v1,v0,0000046c <[^>]*>
+[	]*468: R_MIPS_PC16	.L1.2-0x4
+0+046c <[^>]*> 00000000 	nop
+0+0470 <[^>]*> 1c020000 	bgtzalc	v0,00000474 <[^>]*>
+[	]*470: R_MIPS_PC16	ext-0x4
+0+0474 <[^>]*> 00000000 	nop
+0+0478 <[^>]*> 1c020000 	bgtzalc	v0,0000047c <[^>]*>
+[	]*478: R_MIPS_PC16	L0.-0x20000
+0+047c <[^>]*> 00000000 	nop
+0+0480 <[^>]*> 1c020000 	bgtzalc	v0,00000484 <[^>]*>
+[	]*480: R_MIPS_PC16	L0.+0x1fffc
+0+0484 <[^>]*> 00000000 	nop
+0+0488 <[^>]*> 1c020000 	bgtzalc	v0,0000048c <[^>]*>
+[	]*488: R_MIPS_PC16	.L1.2-0x4
+0+048c <[^>]*> 00000000 	nop
+0+0490 <[^>]*> 1c420000 	bltzalc	v0,00000494 <[^>]*>
+[	]*490: R_MIPS_PC16	ext-0x4
+0+0494 <[^>]*> 00000000 	nop
+0+0498 <[^>]*> 1c420000 	bltzalc	v0,0000049c <[^>]*>
+[	]*498: R_MIPS_PC16	L0.-0x20000
+0+049c <[^>]*> 00000000 	nop
+0+04a0 <[^>]*> 1c420000 	bltzalc	v0,000004a4 <[^>]*>
+[	]*4a0: R_MIPS_PC16	L0.+0x1fffc
+0+04a4 <[^>]*> 00000000 	nop
+0+04a8 <[^>]*> 1c420000 	bltzalc	v0,000004ac <[^>]*>
+[	]*4a8: R_MIPS_PC16	.L1.2-0x4
+0+04ac <[^>]*> 00000000 	nop
+0+04b0 <[^>]*> 1c430000 	bltuc	v0,v1,000004b4 <[^>]*>
+[	]*4b0: R_MIPS_PC16	ext-0x4
+0+04b4 <[^>]*> 00000000 	nop
+0+04b8 <[^>]*> 1c430000 	bltuc	v0,v1,000004bc <[^>]*>
+[	]*4b8: R_MIPS_PC16	L0.-0x20000
+0+04bc <[^>]*> 00000000 	nop
+0+04c0 <[^>]*> 1c430000 	bltuc	v0,v1,000004c4 <[^>]*>
+[	]*4c0: R_MIPS_PC16	L0.+0x1fffc
+0+04c4 <[^>]*> 00000000 	nop
+0+04c8 <[^>]*> 1c430000 	bltuc	v0,v1,000004cc <[^>]*>
+[	]*4c8: R_MIPS_PC16	.L1.2-0x4
+0+04cc <[^>]*> 00000000 	nop
+0+04d0 <[^>]*> 1c620000 	bltuc	v1,v0,000004d4 <[^>]*>
+[	]*4d0: R_MIPS_PC16	.L1.2-0x4
+0+04d4 <[^>]*> 00000000 	nop
+0+04d8 <[^>]*> c8000000 	bc	000004dc <[^>]*>
+[	]*4d8: R_MIPS_PC26_S2	ext-0x4
+0+04dc <[^>]*> c8000000 	bc	000004e0 <[^>]*>
+[	]*4dc: R_MIPS_PC26_S2	L0.-0x8000000
+0+04e0 <[^>]*> c8000000 	bc	000004e4 <[^>]*>
+[	]*4e0: R_MIPS_PC26_S2	L0.+0x7fffffc
+0+04e4 <[^>]*> c8000000 	bc	000004e8 <[^>]*>
+[	]*4e4: R_MIPS_PC26_S2	.L1.2-0x4
+0+04e8 <[^>]*> e8000000 	balc	000004ec <[^>]*>
+[	]*4e8: R_MIPS_PC26_S2	ext-0x4
+0+04ec <[^>]*> e8000000 	balc	000004f0 <[^>]*>
+[	]*4ec: R_MIPS_PC26_S2	L0.-0x8000000
+0+04f0 <[^>]*> e8000000 	balc	000004f4 <[^>]*>
+[	]*4f0: R_MIPS_PC26_S2	L0.+0x7fffffc
+0+04f4 <[^>]*> e8000000 	balc	000004f8 <[^>]*>
+[	]*4f4: R_MIPS_PC26_S2	.L1.2-0x4
+0+04f8 <[^>]*> d8400000 	beqzc	v0,000004fc <[^>]*>
+[	]*4f8: R_MIPS_PC21_S2	ext-0x4
+0+04fc <[^>]*> 00000000 	nop
+0+0500 <[^>]*> d8400000 	beqzc	v0,00000504 <[^>]*>
+[	]*500: R_MIPS_PC21_S2	L0.-0x400000
+0+0504 <[^>]*> 00000000 	nop
+0+0508 <[^>]*> d8400000 	beqzc	v0,0000050c <[^>]*>
+[	]*508: R_MIPS_PC21_S2	L0.+0x3ffffc
+0+050c <[^>]*> 00000000 	nop
+0+0510 <[^>]*> d8400000 	beqzc	v0,00000514 <[^>]*>
+[	]*510: R_MIPS_PC21_S2	.L1.2-0x4
+0+0514 <[^>]*> 00000000 	nop
+0+0518 <[^>]*> d8038000 	jic	v1,-32768
+0+051c <[^>]*> d8037fff 	jic	v1,32767
+0+0520 <[^>]*> d81f0000 	jrc	ra
+0+0524 <[^>]*> f8400000 	bnezc	v0,00000528 <[^>]*>
+[	]*524: R_MIPS_PC21_S2	ext-0x4
+0+0528 <[^>]*> 00000000 	nop
+0+052c <[^>]*> f8400000 	bnezc	v0,00000530 <[^>]*>
+[	]*52c: R_MIPS_PC21_S2	L0.-0x400000
+0+0530 <[^>]*> 00000000 	nop
+0+0534 <[^>]*> f8400000 	bnezc	v0,00000538 <[^>]*>
+[	]*534: R_MIPS_PC21_S2	L0.+0x3ffffc
+0+0538 <[^>]*> 00000000 	nop
+0+053c <[^>]*> f8400000 	bnezc	v0,00000540 <[^>]*>
+[	]*53c: R_MIPS_PC21_S2	.L1.2-0x4
+0+0540 <[^>]*> 00000000 	nop
+0+0544 <[^>]*> f8038000 	jialc	v1,-32768
+0+0548 <[^>]*> f8037fff 	jialc	v1,32767
+0+054c <[^>]*> 3c43ffff 	aui	v1,v0,0xffff
+0+0550 <[^>]*> ec600000 	lapc	v1,00000550 <[^>]*>
+[	]*550: R_MIPS_PC19_S2	.L1.2
+0+0554 <[^>]*> ec800000 	lapc	a0,00000554 <[^>]*>
+[	]*554: R_MIPS_PC19_S2	L0.-0x100000
+0+0558 <[^>]*> ec800000 	lapc	a0,00000558 <[^>]*>
+[	]*558: R_MIPS_PC19_S2	L0.+0xffffc
+0+055c <[^>]*> ec840000 	lapc	a0,fff0055c <[^>]*>
+0+0560 <[^>]*> ec83ffff 	lapc	a0,0010055c <[^>]*>
+0+0564 <[^>]*> ec7effff 	auipc	v1,0xffff
+0+0568 <[^>]*> ec7fffff 	aluipc	v1,0xffff
+0+056c <[^>]*> ec880000 	lwpc	a0,0000056c <[^>]*>
+[	]*56c: R_MIPS_PC19_S2	.L1.2
+0+0570 <[^>]*> ec880000 	lwpc	a0,00000570 <[^>]*>
+[	]*570: R_MIPS_PC19_S2	L0.-0x100000
+0+0574 <[^>]*> ec880000 	lwpc	a0,00000574 <[^>]*>
+[	]*574: R_MIPS_PC19_S2	L0.+0xffffc
+0+0578 <[^>]*> ec8c0000 	lwpc	a0,fff00578 <[^>]*>
+0+057c <[^>]*> ec8bffff 	lwpc	a0,00100578 <[^>]*>
+0+0580 <[^>]*> 00000000 	nop
+0+0584 <[^>]*> ec83ffff 	lapc	a0,00100580 <[^>]*>
+	\.\.\.
diff --git a/gas/testsuite/gas/mips/r6-n64.d b/gas/testsuite/gas/mips/r6-n64.d
new file mode 100644
index 00000000000..d0999880675
--- /dev/null
+++ b/gas/testsuite/gas/mips/r6-n64.d
@@ -0,0 +1,749 @@
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS MIPSR6 instructions
+#as: -64
+#source: r6.s
+
+# Check MIPSR6 instructions
+
+.*: +file format .*mips.*
+
+Disassembly of section .text:
+0+0000 <[^>]*> 46020818 	maddf.s	\$f0,\$f1,\$f2
+0+0004 <[^>]*> 462520d8 	maddf.d	\$f3,\$f4,\$f5
+0+0008 <[^>]*> 46083999 	msubf.s	\$f6,\$f7,\$f8
+0+000c <[^>]*> 462b5259 	msubf.d	\$f9,\$f10,\$f11
+0+0010 <[^>]*> 46820800 	cmp.af.s	\$f0,\$f1,\$f2
+0+0014 <[^>]*> 46a20800 	cmp.af.d	\$f0,\$f1,\$f2
+0+0018 <[^>]*> 46820801 	cmp.un.s	\$f0,\$f1,\$f2
+0+001c <[^>]*> 46a20801 	cmp.un.d	\$f0,\$f1,\$f2
+0+0020 <[^>]*> 46820802 	cmp.eq.s	\$f0,\$f1,\$f2
+0+0024 <[^>]*> 46a20802 	cmp.eq.d	\$f0,\$f1,\$f2
+0+0028 <[^>]*> 46820803 	cmp.ueq.s	\$f0,\$f1,\$f2
+0+002c <[^>]*> 46a20803 	cmp.ueq.d	\$f0,\$f1,\$f2
+0+0030 <[^>]*> 46820804 	cmp.lt.s	\$f0,\$f1,\$f2
+0+0034 <[^>]*> 46a20804 	cmp.lt.d	\$f0,\$f1,\$f2
+0+0038 <[^>]*> 46820805 	cmp.ult.s	\$f0,\$f1,\$f2
+0+003c <[^>]*> 46a20805 	cmp.ult.d	\$f0,\$f1,\$f2
+0+0040 <[^>]*> 46820806 	cmp.le.s	\$f0,\$f1,\$f2
+0+0044 <[^>]*> 46a20806 	cmp.le.d	\$f0,\$f1,\$f2
+0+0048 <[^>]*> 46820807 	cmp.ule.s	\$f0,\$f1,\$f2
+0+004c <[^>]*> 46a20807 	cmp.ule.d	\$f0,\$f1,\$f2
+0+0050 <[^>]*> 46820808 	cmp.saf.s	\$f0,\$f1,\$f2
+0+0054 <[^>]*> 46a20808 	cmp.saf.d	\$f0,\$f1,\$f2
+0+0058 <[^>]*> 46820809 	cmp.sun.s	\$f0,\$f1,\$f2
+0+005c <[^>]*> 46a20809 	cmp.sun.d	\$f0,\$f1,\$f2
+0+0060 <[^>]*> 4682080a 	cmp.seq.s	\$f0,\$f1,\$f2
+0+0064 <[^>]*> 46a2080a 	cmp.seq.d	\$f0,\$f1,\$f2
+0+0068 <[^>]*> 4682080b 	cmp.sueq.s	\$f0,\$f1,\$f2
+0+006c <[^>]*> 46a2080b 	cmp.sueq.d	\$f0,\$f1,\$f2
+0+0070 <[^>]*> 4682080c 	cmp.slt.s	\$f0,\$f1,\$f2
+0+0074 <[^>]*> 46a2080c 	cmp.slt.d	\$f0,\$f1,\$f2
+0+0078 <[^>]*> 4682080d 	cmp.sult.s	\$f0,\$f1,\$f2
+0+007c <[^>]*> 46a2080d 	cmp.sult.d	\$f0,\$f1,\$f2
+0+0080 <[^>]*> 4682080e 	cmp.sle.s	\$f0,\$f1,\$f2
+0+0084 <[^>]*> 46a2080e 	cmp.sle.d	\$f0,\$f1,\$f2
+0+0088 <[^>]*> 4682080f 	cmp.sule.s	\$f0,\$f1,\$f2
+0+008c <[^>]*> 46a2080f 	cmp.sule.d	\$f0,\$f1,\$f2
+0+0090 <[^>]*> 46820811 	cmp.or.s	\$f0,\$f1,\$f2
+0+0094 <[^>]*> 46a20811 	cmp.or.d	\$f0,\$f1,\$f2
+0+0098 <[^>]*> 46820812 	cmp.une.s	\$f0,\$f1,\$f2
+0+009c <[^>]*> 46a20812 	cmp.une.d	\$f0,\$f1,\$f2
+0+00a0 <[^>]*> 46820813 	cmp.ne.s	\$f0,\$f1,\$f2
+0+00a4 <[^>]*> 46a20813 	cmp.ne.d	\$f0,\$f1,\$f2
+0+00a8 <[^>]*> 46820819 	cmp.sor.s	\$f0,\$f1,\$f2
+0+00ac <[^>]*> 46a20819 	cmp.sor.d	\$f0,\$f1,\$f2
+0+00b0 <[^>]*> 4682081a 	cmp.sune.s	\$f0,\$f1,\$f2
+0+00b4 <[^>]*> 46a2081a 	cmp.sune.d	\$f0,\$f1,\$f2
+0+00b8 <[^>]*> 4682081b 	cmp.sne.s	\$f0,\$f1,\$f2
+0+00bc <[^>]*> 46a2081b 	cmp.sne.d	\$f0,\$f1,\$f2
+0+00c0 <[^>]*> 45200000 	bc1eqz	\$f0,0+00c4 <[^>]*>
+[	]*c0: R_MIPS_PC16	.L1.1-0x4
+[	]*c0: R_MIPS_NONE	\*ABS\*-0x4
+[	]*c0: R_MIPS_NONE	\*ABS\*-0x4
+0+00c4 <[^>]*> 00000000 	nop
+0+00c8 <[^>]*> 453f0000 	bc1eqz	\$f31,0+00cc <[^>]*>
+[	]*c8: R_MIPS_PC16	.L1.1-0x4
+[	]*c8: R_MIPS_NONE	\*ABS\*-0x4
+[	]*c8: R_MIPS_NONE	\*ABS\*-0x4
+0+00cc <[^>]*> 00000000 	nop
+0+00d0 <[^>]*> 453f0000 	bc1eqz	\$f31,0+00d4 <[^>]*>
+[	]*d0: R_MIPS_PC16	new-0x4
+[	]*d0: R_MIPS_NONE	\*ABS\*-0x4
+[	]*d0: R_MIPS_NONE	\*ABS\*-0x4
+0+00d4 <[^>]*> 00000000 	nop
+0+00d8 <[^>]*> 453f0000 	bc1eqz	\$f31,0+00dc <[^>]*>
+[	]*d8: R_MIPS_PC16	external_label-0x4
+[	]*d8: R_MIPS_NONE	\*ABS\*-0x4
+[	]*d8: R_MIPS_NONE	\*ABS\*-0x4
+0+00dc <[^>]*> 00000000 	nop
+0+00e0 <[^>]*> 45a00000 	bc1nez	\$f0,0+00e4 <[^>]*>
+[	]*e0: R_MIPS_PC16	.L1.1-0x4
+[	]*e0: R_MIPS_NONE	\*ABS\*-0x4
+[	]*e0: R_MIPS_NONE	\*ABS\*-0x4
+0+00e4 <[^>]*> 00000000 	nop
+0+00e8 <[^>]*> 45bf0000 	bc1nez	\$f31,0+00ec <[^>]*>
+[	]*e8: R_MIPS_PC16	.L1.1-0x4
+[	]*e8: R_MIPS_NONE	\*ABS\*-0x4
+[	]*e8: R_MIPS_NONE	\*ABS\*-0x4
+0+00ec <[^>]*> 00000000 	nop
+0+00f0 <[^>]*> 45bf0000 	bc1nez	\$f31,0+00f4 <[^>]*>
+[	]*f0: R_MIPS_PC16	new-0x4
+[	]*f0: R_MIPS_NONE	\*ABS\*-0x4
+[	]*f0: R_MIPS_NONE	\*ABS\*-0x4
+0+00f4 <[^>]*> 00000000 	nop
+0+00f8 <[^>]*> 45bf0000 	bc1nez	\$f31,0+00fc <[^>]*>
+[	]*f8: R_MIPS_PC16	external_label-0x4
+[	]*f8: R_MIPS_NONE	\*ABS\*-0x4
+[	]*f8: R_MIPS_NONE	\*ABS\*-0x4
+0+00fc <[^>]*> 00000000 	nop
+0+0100 <[^>]*> 49200000 	bc2eqz	\$0,0+0104 <[^>]*>
+[	]*100: R_MIPS_PC16	.L1.1-0x4
+[	]*100: R_MIPS_NONE	\*ABS\*-0x4
+[	]*100: R_MIPS_NONE	\*ABS\*-0x4
+0+0104 <[^>]*> 00000000 	nop
+0+0108 <[^>]*> 493f0000 	bc2eqz	\$31,0+010c <[^>]*>
+[	]*108: R_MIPS_PC16	.L1.1-0x4
+[	]*108: R_MIPS_NONE	\*ABS\*-0x4
+[	]*108: R_MIPS_NONE	\*ABS\*-0x4
+0+010c <[^>]*> 00000000 	nop
+0+0110 <[^>]*> 493f0000 	bc2eqz	\$31,0+0114 <[^>]*>
+[	]*110: R_MIPS_PC16	new-0x4
+[	]*110: R_MIPS_NONE	\*ABS\*-0x4
+[	]*110: R_MIPS_NONE	\*ABS\*-0x4
+0+0114 <[^>]*> 00000000 	nop
+0+0118 <[^>]*> 493f0000 	bc2eqz	\$31,0+011c <[^>]*>
+[	]*118: R_MIPS_PC16	external_label-0x4
+[	]*118: R_MIPS_NONE	\*ABS\*-0x4
+[	]*118: R_MIPS_NONE	\*ABS\*-0x4
+0+011c <[^>]*> 00000000 	nop
+0+0120 <[^>]*> 49a00000 	bc2nez	\$0,0+0124 <[^>]*>
+[	]*120: R_MIPS_PC16	.L1.1-0x4
+[	]*120: R_MIPS_NONE	\*ABS\*-0x4
+[	]*120: R_MIPS_NONE	\*ABS\*-0x4
+0+0124 <[^>]*> 00000000 	nop
+0+0128 <[^>]*> 49bf0000 	bc2nez	\$31,0+012c <[^>]*>
+[	]*128: R_MIPS_PC16	.L1.1-0x4
+[	]*128: R_MIPS_NONE	\*ABS\*-0x4
+[	]*128: R_MIPS_NONE	\*ABS\*-0x4
+0+012c <[^>]*> 00000000 	nop
+0+0130 <[^>]*> 49bf0000 	bc2nez	\$31,0+0134 <[^>]*>
+[	]*130: R_MIPS_PC16	new-0x4
+[	]*130: R_MIPS_NONE	\*ABS\*-0x4
+[	]*130: R_MIPS_NONE	\*ABS\*-0x4
+0+0134 <[^>]*> 00000000 	nop
+0+0138 <[^>]*> 49bf0000 	bc2nez	\$31,0+013c <[^>]*>
+[	]*138: R_MIPS_PC16	external_label-0x4
+[	]*138: R_MIPS_NONE	\*ABS\*-0x4
+[	]*138: R_MIPS_NONE	\*ABS\*-0x4
+0+013c <[^>]*> 00000000 	nop
+0+0140 <[^>]*> 46020810 	sel.s	\$f0,\$f1,\$f2
+0+0144 <[^>]*> 46220810 	sel.d	\$f0,\$f1,\$f2
+0+0148 <[^>]*> 46020814 	seleqz.s	\$f0,\$f1,\$f2
+0+014c <[^>]*> 46220814 	seleqz.d	\$f0,\$f1,\$f2
+0+0150 <[^>]*> 46020817 	selnez.s	\$f0,\$f1,\$f2
+0+0154 <[^>]*> 46220817 	selnez.d	\$f0,\$f1,\$f2
+0+0158 <[^>]*> 00641035 	seleqz	v0,v1,a0
+0+015c <[^>]*> 00641037 	selnez	v0,v1,a0
+0+0160 <[^>]*> 00641098 	mul	v0,v1,a0
+0+0164 <[^>]*> 006410d8 	muh	v0,v1,a0
+0+0168 <[^>]*> 00641099 	mulu	v0,v1,a0
+0+016c <[^>]*> 006410d9 	muhu	v0,v1,a0
+0+0170 <[^>]*> 0064109a 	div	v0,v1,a0
+0+0174 <[^>]*> 006410da 	mod	v0,v1,a0
+0+0178 <[^>]*> 0064109b 	divu	v0,v1,a0
+0+017c <[^>]*> 006410db 	modu	v0,v1,a0
+0+0180 <[^>]*> 49422000 	lwc2	\$2,0\(a0\)
+0+0184 <[^>]*> 49422400 	lwc2	\$2,-1024\(a0\)
+0+0188 <[^>]*> 494223ff 	lwc2	\$2,1023\(a0\)
+0+018c <[^>]*> 49622000 	swc2	\$2,0\(a0\)
+0+0190 <[^>]*> 49622400 	swc2	\$2,-1024\(a0\)
+0+0194 <[^>]*> 496223ff 	swc2	\$2,1023\(a0\)
+0+0198 <[^>]*> 49c22000 	ldc2	\$2,0\(a0\)
+0+019c <[^>]*> 49c22400 	ldc2	\$2,-1024\(a0\)
+0+01a0 <[^>]*> 49c223ff 	ldc2	\$2,1023\(a0\)
+0+01a4 <[^>]*> 49e22000 	sdc2	\$2,0\(a0\)
+0+01a8 <[^>]*> 49e22400 	sdc2	\$2,-1024\(a0\)
+0+01ac <[^>]*> 49e223ff 	sdc2	\$2,1023\(a0\)
+0+01b0 <[^>]*> 00641005 	lsa	v0,v1,a0,0x1
+0+01b4 <[^>]*> 006410c5 	lsa	v0,v1,a0,0x4
+0+01b8 <[^>]*> 00601050 	clz	v0,v1
+0+01bc <[^>]*> 00601051 	clo	v0,v1
+0+01c0 <[^>]*> 0000000e 	sdbbp
+0+01c4 <[^>]*> 0000000e 	sdbbp
+0+01c8 <[^>]*> 0000004e 	sdbbp	0x1
+0+01cc <[^>]*> 03ffffce 	sdbbp	0xfffff
+0+01d0 <[^>]*> 3c02ffff 	lui	v0,0xffff
+0+01d4 <[^>]*> 7c008035 	pref	0x0,-256\(zero\)
+0+01d8 <[^>]*> 7fff7fb5 	pref	0x1f,255\(ra\)
+0+01dc <[^>]*> 7c628036 	ll	v0,-256\(v1\)
+0+01e0 <[^>]*> 7c627fb6 	ll	v0,255\(v1\)
+0+01e4 <[^>]*> 7c628026 	sc	v0,-256\(v1\)
+0+01e8 <[^>]*> 7c627fa6 	sc	v0,255\(v1\)
+0+01ec <[^>]*> 7c608025 	cache	0x0,-256\(v1\)
+0+01f0 <[^>]*> 7c7f7fa5 	cache	0x1f,255\(v1\)
+0+01f4 <[^>]*> 7c432220 	align	a0,v0,v1,0
+0+01f8 <[^>]*> 7c432260 	align	a0,v0,v1,1
+0+01fc <[^>]*> 7c4322a0 	align	a0,v0,v1,2
+0+0200 <[^>]*> 7c4322e0 	align	a0,v0,v1,3
+0+0204 <[^>]*> 7c022020 	bitswap	a0,v0
+0+0208 <[^>]*> 20000000 	bovc	zero,zero,0+020c <[^>]*>
+[	]*208: R_MIPS_PC16	ext-0x4
+[	]*208: R_MIPS_NONE	\*ABS\*-0x4
+[	]*208: R_MIPS_NONE	\*ABS\*-0x4
+0+020c <[^>]*> 00000000 	nop
+0+0210 <[^>]*> 20400000 	bovc	v0,zero,0+0214 <[^>]*>
+[	]*210: R_MIPS_PC16	ext-0x4
+[	]*210: R_MIPS_NONE	\*ABS\*-0x4
+[	]*210: R_MIPS_NONE	\*ABS\*-0x4
+0+0214 <[^>]*> 00000000 	nop
+0+0218 <[^>]*> 20400000 	bovc	v0,zero,0+021c <[^>]*>
+[	]*218: R_MIPS_PC16	ext-0x4
+[	]*218: R_MIPS_NONE	\*ABS\*-0x4
+[	]*218: R_MIPS_NONE	\*ABS\*-0x4
+0+021c <[^>]*> 00000000 	nop
+0+0220 <[^>]*> 20820000 	bovc	a0,v0,0+0224 <[^>]*>
+[	]*220: R_MIPS_PC16	ext-0x4
+[	]*220: R_MIPS_NONE	\*ABS\*-0x4
+[	]*220: R_MIPS_NONE	\*ABS\*-0x4
+0+0224 <[^>]*> 00000000 	nop
+0+0228 <[^>]*> 20820000 	bovc	a0,v0,0+022c <[^>]*>
+[	]*228: R_MIPS_PC16	ext-0x4
+[	]*228: R_MIPS_NONE	\*ABS\*-0x4
+[	]*228: R_MIPS_NONE	\*ABS\*-0x4
+0+022c <[^>]*> 00000000 	nop
+0+0230 <[^>]*> 20820000 	bovc	a0,v0,0+0234 <[^>]*>
+[	]*230: R_MIPS_PC16	L0.-0x20000
+[	]*230: R_MIPS_NONE	\*ABS\*-0x20000
+[	]*230: R_MIPS_NONE	\*ABS\*-0x20000
+0+0234 <[^>]*> 00000000 	nop
+0+0238 <[^>]*> 20820000 	bovc	a0,v0,0+023c <[^>]*>
+[	]*238: R_MIPS_PC16	L0.\+0x1fffc
+[	]*238: R_MIPS_NONE	\*ABS\*\+0x1fffc
+[	]*238: R_MIPS_NONE	\*ABS\*\+0x1fffc
+0+023c <[^>]*> 00000000 	nop
+0+0240 <[^>]*> 20820000 	bovc	a0,v0,0+0244 <[^>]*>
+[	]*240: R_MIPS_PC16	.L1.2-0x4
+[	]*240: R_MIPS_NONE	\*ABS\*-0x4
+[	]*240: R_MIPS_NONE	\*ABS\*-0x4
+0+0244 <[^>]*> 00000000 	nop
+0+0248 <[^>]*> 20420000 	bovc	v0,v0,0+024c <[^>]*>
+[	]*248: R_MIPS_PC16	ext-0x4
+[	]*248: R_MIPS_NONE	\*ABS\*-0x4
+[	]*248: R_MIPS_NONE	\*ABS\*-0x4
+0+024c <[^>]*> 00000000 	nop
+0+0250 <[^>]*> 20420000 	bovc	v0,v0,0+0254 <[^>]*>
+[	]*250: R_MIPS_PC16	L0.-0x20000
+[	]*250: R_MIPS_NONE	\*ABS\*-0x20000
+[	]*250: R_MIPS_NONE	\*ABS\*-0x20000
+0+0254 <[^>]*> 00000000 	nop
+0+0258 <[^>]*> 20020000 	beqzalc	v0,0+025c <[^>]*>
+[	]*258: R_MIPS_PC16	ext-0x4
+[	]*258: R_MIPS_NONE	\*ABS\*-0x4
+[	]*258: R_MIPS_NONE	\*ABS\*-0x4
+0+025c <[^>]*> 00000000 	nop
+0+0260 <[^>]*> 20020000 	beqzalc	v0,0+0264 <[^>]*>
+[	]*260: R_MIPS_PC16	L0.-0x20000
+[	]*260: R_MIPS_NONE	\*ABS\*-0x20000
+[	]*260: R_MIPS_NONE	\*ABS\*-0x20000
+0+0264 <[^>]*> 00000000 	nop
+0+0268 <[^>]*> 20020000 	beqzalc	v0,0+026c <[^>]*>
+[	]*268: R_MIPS_PC16	L0.\+0x1fffc
+[	]*268: R_MIPS_NONE	\*ABS\*\+0x1fffc
+[	]*268: R_MIPS_NONE	\*ABS\*\+0x1fffc
+0+026c <[^>]*> 00000000 	nop
+0+0270 <[^>]*> 20020000 	beqzalc	v0,0+0274 <[^>]*>
+[	]*270: R_MIPS_PC16	.L1.2-0x4
+[	]*270: R_MIPS_NONE	\*ABS\*-0x4
+[	]*270: R_MIPS_NONE	\*ABS\*-0x4
+0+0274 <[^>]*> 00000000 	nop
+0+0278 <[^>]*> 20430000 	beqc	v0,v1,0+027c <[^>]*>
+[	]*278: R_MIPS_PC16	ext-0x4
+[	]*278: R_MIPS_NONE	\*ABS\*-0x4
+[	]*278: R_MIPS_NONE	\*ABS\*-0x4
+0+027c <[^>]*> 00000000 	nop
+0+0280 <[^>]*> 20430000 	beqc	v0,v1,0+0284 <[^>]*>
+[	]*280: R_MIPS_PC16	ext-0x4
+[	]*280: R_MIPS_NONE	\*ABS\*-0x4
+[	]*280: R_MIPS_NONE	\*ABS\*-0x4
+0+0284 <[^>]*> 00000000 	nop
+0+0288 <[^>]*> 20430000 	beqc	v0,v1,0+028c <[^>]*>
+[	]*288: R_MIPS_PC16	L0.-0x20000
+[	]*288: R_MIPS_NONE	\*ABS\*-0x20000
+[	]*288: R_MIPS_NONE	\*ABS\*-0x20000
+0+028c <[^>]*> 00000000 	nop
+0+0290 <[^>]*> 20430000 	beqc	v0,v1,0+0294 <[^>]*>
+[	]*290: R_MIPS_PC16	L0.\+0x1fffc
+[	]*290: R_MIPS_NONE	\*ABS\*\+0x1fffc
+[	]*290: R_MIPS_NONE	\*ABS\*\+0x1fffc
+0+0294 <[^>]*> 00000000 	nop
+0+0298 <[^>]*> 20430000 	beqc	v0,v1,0+029c <[^>]*>
+[	]*298: R_MIPS_PC16	.L1.2-0x4
+[	]*298: R_MIPS_NONE	\*ABS\*-0x4
+[	]*298: R_MIPS_NONE	\*ABS\*-0x4
+0+029c <[^>]*> 00000000 	nop
+0+02a0 <[^>]*> 60000000 	bnvc	zero,zero,0+02a4 <[^>]*>
+[	]*2a0: R_MIPS_PC16	ext-0x4
+[	]*2a0: R_MIPS_NONE	\*ABS\*-0x4
+[	]*2a0: R_MIPS_NONE	\*ABS\*-0x4
+0+02a4 <[^>]*> 00000000 	nop
+0+02a8 <[^>]*> 60400000 	bnvc	v0,zero,0+02ac <[^>]*>
+[	]*2a8: R_MIPS_PC16	ext-0x4
+[	]*2a8: R_MIPS_NONE	\*ABS\*-0x4
+[	]*2a8: R_MIPS_NONE	\*ABS\*-0x4
+0+02ac <[^>]*> 00000000 	nop
+0+02b0 <[^>]*> 60400000 	bnvc	v0,zero,0+02b4 <[^>]*>
+[	]*2b0: R_MIPS_PC16	ext-0x4
+[	]*2b0: R_MIPS_NONE	\*ABS\*-0x4
+[	]*2b0: R_MIPS_NONE	\*ABS\*-0x4
+0+02b4 <[^>]*> 00000000 	nop
+0+02b8 <[^>]*> 60820000 	bnvc	a0,v0,0+02bc <[^>]*>
+[	]*2b8: R_MIPS_PC16	ext-0x4
+[	]*2b8: R_MIPS_NONE	\*ABS\*-0x4
+[	]*2b8: R_MIPS_NONE	\*ABS\*-0x4
+0+02bc <[^>]*> 00000000 	nop
+0+02c0 <[^>]*> 60820000 	bnvc	a0,v0,0+02c4 <[^>]*>
+[	]*2c0: R_MIPS_PC16	ext-0x4
+[	]*2c0: R_MIPS_NONE	\*ABS\*-0x4
+[	]*2c0: R_MIPS_NONE	\*ABS\*-0x4
+0+02c4 <[^>]*> 00000000 	nop
+0+02c8 <[^>]*> 60820000 	bnvc	a0,v0,0+02cc <[^>]*>
+[	]*2c8: R_MIPS_PC16	L0.-0x20000
+[	]*2c8: R_MIPS_NONE	\*ABS\*-0x20000
+[	]*2c8: R_MIPS_NONE	\*ABS\*-0x20000
+0+02cc <[^>]*> 00000000 	nop
+0+02d0 <[^>]*> 60820000 	bnvc	a0,v0,0+02d4 <[^>]*>
+[	]*2d0: R_MIPS_PC16	L0.\+0x1fffc
+[	]*2d0: R_MIPS_NONE	\*ABS\*\+0x1fffc
+[	]*2d0: R_MIPS_NONE	\*ABS\*\+0x1fffc
+0+02d4 <[^>]*> 00000000 	nop
+0+02d8 <[^>]*> 60820000 	bnvc	a0,v0,0+02dc <[^>]*>
+[	]*2d8: R_MIPS_PC16	.L1.2-0x4
+[	]*2d8: R_MIPS_NONE	\*ABS\*-0x4
+[	]*2d8: R_MIPS_NONE	\*ABS\*-0x4
+0+02dc <[^>]*> 00000000 	nop
+0+02e0 <[^>]*> 60420000 	bnvc	v0,v0,0+02e4 <[^>]*>
+[	]*2e0: R_MIPS_PC16	ext-0x4
+[	]*2e0: R_MIPS_NONE	\*ABS\*-0x4
+[	]*2e0: R_MIPS_NONE	\*ABS\*-0x4
+0+02e4 <[^>]*> 00000000 	nop
+0+02e8 <[^>]*> 60420000 	bnvc	v0,v0,0+02ec <[^>]*>
+[	]*2e8: R_MIPS_PC16	L0.-0x20000
+[	]*2e8: R_MIPS_NONE	\*ABS\*-0x20000
+[	]*2e8: R_MIPS_NONE	\*ABS\*-0x20000
+0+02ec <[^>]*> 00000000 	nop
+0+02f0 <[^>]*> 60020000 	bnezalc	v0,0+02f4 <[^>]*>
+[	]*2f0: R_MIPS_PC16	ext-0x4
+[	]*2f0: R_MIPS_NONE	\*ABS\*-0x4
+[	]*2f0: R_MIPS_NONE	\*ABS\*-0x4
+0+02f4 <[^>]*> 00000000 	nop
+0+02f8 <[^>]*> 60020000 	bnezalc	v0,0+02fc <[^>]*>
+[	]*2f8: R_MIPS_PC16	L0.-0x20000
+[	]*2f8: R_MIPS_NONE	\*ABS\*-0x20000
+[	]*2f8: R_MIPS_NONE	\*ABS\*-0x20000
+0+02fc <[^>]*> 00000000 	nop
+0+0300 <[^>]*> 60020000 	bnezalc	v0,0+0304 <[^>]*>
+[	]*300: R_MIPS_PC16	L0.\+0x1fffc
+[	]*300: R_MIPS_NONE	\*ABS\*\+0x1fffc
+[	]*300: R_MIPS_NONE	\*ABS\*\+0x1fffc
+0+0304 <[^>]*> 00000000 	nop
+0+0308 <[^>]*> 60020000 	bnezalc	v0,0+030c <[^>]*>
+[	]*308: R_MIPS_PC16	.L1.2-0x4
+[	]*308: R_MIPS_NONE	\*ABS\*-0x4
+[	]*308: R_MIPS_NONE	\*ABS\*-0x4
+0+030c <[^>]*> 00000000 	nop
+0+0310 <[^>]*> 60430000 	bnec	v0,v1,0+0314 <[^>]*>
+[	]*310: R_MIPS_PC16	ext-0x4
+[	]*310: R_MIPS_NONE	\*ABS\*-0x4
+[	]*310: R_MIPS_NONE	\*ABS\*-0x4
+0+0314 <[^>]*> 00000000 	nop
+0+0318 <[^>]*> 60430000 	bnec	v0,v1,0+031c <[^>]*>
+[	]*318: R_MIPS_PC16	ext-0x4
+[	]*318: R_MIPS_NONE	\*ABS\*-0x4
+[	]*318: R_MIPS_NONE	\*ABS\*-0x4
+0+031c <[^>]*> 00000000 	nop
+0+0320 <[^>]*> 60430000 	bnec	v0,v1,0+0324 <[^>]*>
+[	]*320: R_MIPS_PC16	L0.-0x20000
+[	]*320: R_MIPS_NONE	\*ABS\*-0x20000
+[	]*320: R_MIPS_NONE	\*ABS\*-0x20000
+0+0324 <[^>]*> 00000000 	nop
+0+0328 <[^>]*> 60430000 	bnec	v0,v1,0+032c <[^>]*>
+[	]*328: R_MIPS_PC16	L0.\+0x1fffc
+[	]*328: R_MIPS_NONE	\*ABS\*\+0x1fffc
+[	]*328: R_MIPS_NONE	\*ABS\*\+0x1fffc
+0+032c <[^>]*> 00000000 	nop
+0+0330 <[^>]*> 60430000 	bnec	v0,v1,0+0334 <[^>]*>
+[	]*330: R_MIPS_PC16	.L1.2-0x4
+[	]*330: R_MIPS_NONE	\*ABS\*-0x4
+[	]*330: R_MIPS_NONE	\*ABS\*-0x4
+0+0334 <[^>]*> 00000000 	nop
+0+0338 <[^>]*> 58020000 	blezc	v0,0+033c <[^>]*>
+[	]*338: R_MIPS_PC16	ext-0x4
+[	]*338: R_MIPS_NONE	\*ABS\*-0x4
+[	]*338: R_MIPS_NONE	\*ABS\*-0x4
+0+033c <[^>]*> 00000000 	nop
+0+0340 <[^>]*> 58020000 	blezc	v0,0+0344 <[^>]*>
+[	]*340: R_MIPS_PC16	L0.-0x20000
+[	]*340: R_MIPS_NONE	\*ABS\*-0x20000
+[	]*340: R_MIPS_NONE	\*ABS\*-0x20000
+0+0344 <[^>]*> 00000000 	nop
+0+0348 <[^>]*> 58020000 	blezc	v0,0+034c <[^>]*>
+[	]*348: R_MIPS_PC16	L0.\+0x1fffc
+[	]*348: R_MIPS_NONE	\*ABS\*\+0x1fffc
+[	]*348: R_MIPS_NONE	\*ABS\*\+0x1fffc
+0+034c <[^>]*> 00000000 	nop
+0+0350 <[^>]*> 58020000 	blezc	v0,0+0354 <[^>]*>
+[	]*350: R_MIPS_PC16	.L1.2-0x4
+[	]*350: R_MIPS_NONE	\*ABS\*-0x4
+[	]*350: R_MIPS_NONE	\*ABS\*-0x4
+0+0354 <[^>]*> 00000000 	nop
+0+0358 <[^>]*> 58420000 	bgezc	v0,0+035c <[^>]*>
+[	]*358: R_MIPS_PC16	ext-0x4
+[	]*358: R_MIPS_NONE	\*ABS\*-0x4
+[	]*358: R_MIPS_NONE	\*ABS\*-0x4
+0+035c <[^>]*> 00000000 	nop
+0+0360 <[^>]*> 58420000 	bgezc	v0,0+0364 <[^>]*>
+[	]*360: R_MIPS_PC16	L0.-0x20000
+[	]*360: R_MIPS_NONE	\*ABS\*-0x20000
+[	]*360: R_MIPS_NONE	\*ABS\*-0x20000
+0+0364 <[^>]*> 00000000 	nop
+0+0368 <[^>]*> 58420000 	bgezc	v0,0+036c <[^>]*>
+[	]*368: R_MIPS_PC16	L0.\+0x1fffc
+[	]*368: R_MIPS_NONE	\*ABS\*\+0x1fffc
+[	]*368: R_MIPS_NONE	\*ABS\*\+0x1fffc
+0+036c <[^>]*> 00000000 	nop
+0+0370 <[^>]*> 58420000 	bgezc	v0,0+0374 <[^>]*>
+[	]*370: R_MIPS_PC16	.L1.2-0x4
+[	]*370: R_MIPS_NONE	\*ABS\*-0x4
+[	]*370: R_MIPS_NONE	\*ABS\*-0x4
+0+0374 <[^>]*> 00000000 	nop
+0+0378 <[^>]*> 58430000 	bgec	v0,v1,0+037c <[^>]*>
+[	]*378: R_MIPS_PC16	ext-0x4
+[	]*378: R_MIPS_NONE	\*ABS\*-0x4
+[	]*378: R_MIPS_NONE	\*ABS\*-0x4
+0+037c <[^>]*> 00000000 	nop
+0+0380 <[^>]*> 58430000 	bgec	v0,v1,0+0384 <[^>]*>
+[	]*380: R_MIPS_PC16	L0.-0x20000
+[	]*380: R_MIPS_NONE	\*ABS\*-0x20000
+[	]*380: R_MIPS_NONE	\*ABS\*-0x20000
+0+0384 <[^>]*> 00000000 	nop
+0+0388 <[^>]*> 58430000 	bgec	v0,v1,0+038c <[^>]*>
+[	]*388: R_MIPS_PC16	L0.\+0x1fffc
+[	]*388: R_MIPS_NONE	\*ABS\*\+0x1fffc
+[	]*388: R_MIPS_NONE	\*ABS\*\+0x1fffc
+0+038c <[^>]*> 00000000 	nop
+0+0390 <[^>]*> 58430000 	bgec	v0,v1,0+0394 <[^>]*>
+[	]*390: R_MIPS_PC16	.L1.2-0x4
+[	]*390: R_MIPS_NONE	\*ABS\*-0x4
+[	]*390: R_MIPS_NONE	\*ABS\*-0x4
+0+0394 <[^>]*> 00000000 	nop
+0+0398 <[^>]*> 58620000 	bgec	v1,v0,0+039c <[^>]*>
+[	]*398: R_MIPS_PC16	.L1.2-0x4
+[	]*398: R_MIPS_NONE	\*ABS\*-0x4
+[	]*398: R_MIPS_NONE	\*ABS\*-0x4
+0+039c <[^>]*> 00000000 	nop
+0+03a0 <[^>]*> 5c020000 	bgtzc	v0,0+03a4 <[^>]*>
+[	]*3a0: R_MIPS_PC16	ext-0x4
+[	]*3a0: R_MIPS_NONE	\*ABS\*-0x4
+[	]*3a0: R_MIPS_NONE	\*ABS\*-0x4
+0+03a4 <[^>]*> 00000000 	nop
+0+03a8 <[^>]*> 5c020000 	bgtzc	v0,0+03ac <[^>]*>
+[	]*3a8: R_MIPS_PC16	L0.-0x20000
+[	]*3a8: R_MIPS_NONE	\*ABS\*-0x20000
+[	]*3a8: R_MIPS_NONE	\*ABS\*-0x20000
+0+03ac <[^>]*> 00000000 	nop
+0+03b0 <[^>]*> 5c020000 	bgtzc	v0,0+03b4 <[^>]*>
+[	]*3b0: R_MIPS_PC16	L0.\+0x1fffc
+[	]*3b0: R_MIPS_NONE	\*ABS\*\+0x1fffc
+[	]*3b0: R_MIPS_NONE	\*ABS\*\+0x1fffc
+0+03b4 <[^>]*> 00000000 	nop
+0+03b8 <[^>]*> 5c020000 	bgtzc	v0,0+03bc <[^>]*>
+[	]*3b8: R_MIPS_PC16	.L1.2-0x4
+[	]*3b8: R_MIPS_NONE	\*ABS\*-0x4
+[	]*3b8: R_MIPS_NONE	\*ABS\*-0x4
+0+03bc <[^>]*> 00000000 	nop
+0+03c0 <[^>]*> 5c420000 	bltzc	v0,0+03c4 <[^>]*>
+[	]*3c0: R_MIPS_PC16	ext-0x4
+[	]*3c0: R_MIPS_NONE	\*ABS\*-0x4
+[	]*3c0: R_MIPS_NONE	\*ABS\*-0x4
+0+03c4 <[^>]*> 00000000 	nop
+0+03c8 <[^>]*> 5c420000 	bltzc	v0,0+03cc <[^>]*>
+[	]*3c8: R_MIPS_PC16	L0.-0x20000
+[	]*3c8: R_MIPS_NONE	\*ABS\*-0x20000
+[	]*3c8: R_MIPS_NONE	\*ABS\*-0x20000
+0+03cc <[^>]*> 00000000 	nop
+0+03d0 <[^>]*> 5c420000 	bltzc	v0,0+03d4 <[^>]*>
+[	]*3d0: R_MIPS_PC16	L0.\+0x1fffc
+[	]*3d0: R_MIPS_NONE	\*ABS\*\+0x1fffc
+[	]*3d0: R_MIPS_NONE	\*ABS\*\+0x1fffc
+0+03d4 <[^>]*> 00000000 	nop
+0+03d8 <[^>]*> 5c420000 	bltzc	v0,0+03dc <[^>]*>
+[	]*3d8: R_MIPS_PC16	.L1.2-0x4
+[	]*3d8: R_MIPS_NONE	\*ABS\*-0x4
+[	]*3d8: R_MIPS_NONE	\*ABS\*-0x4
+0+03dc <[^>]*> 00000000 	nop
+0+03e0 <[^>]*> 5c430000 	bltc	v0,v1,0+03e4 <[^>]*>
+[	]*3e0: R_MIPS_PC16	ext-0x4
+[	]*3e0: R_MIPS_NONE	\*ABS\*-0x4
+[	]*3e0: R_MIPS_NONE	\*ABS\*-0x4
+0+03e4 <[^>]*> 00000000 	nop
+0+03e8 <[^>]*> 5c430000 	bltc	v0,v1,0+03ec <[^>]*>
+[	]*3e8: R_MIPS_PC16	L0.-0x20000
+[	]*3e8: R_MIPS_NONE	\*ABS\*-0x20000
+[	]*3e8: R_MIPS_NONE	\*ABS\*-0x20000
+0+03ec <[^>]*> 00000000 	nop
+0+03f0 <[^>]*> 5c430000 	bltc	v0,v1,0+03f4 <[^>]*>
+[	]*3f0: R_MIPS_PC16	L0.\+0x1fffc
+[	]*3f0: R_MIPS_NONE	\*ABS\*\+0x1fffc
+[	]*3f0: R_MIPS_NONE	\*ABS\*\+0x1fffc
+0+03f4 <[^>]*> 00000000 	nop
+0+03f8 <[^>]*> 5c430000 	bltc	v0,v1,0+03fc <[^>]*>
+[	]*3f8: R_MIPS_PC16	.L1.2-0x4
+[	]*3f8: R_MIPS_NONE	\*ABS\*-0x4
+[	]*3f8: R_MIPS_NONE	\*ABS\*-0x4
+0+03fc <[^>]*> 00000000 	nop
+0+0400 <[^>]*> 5c620000 	bltc	v1,v0,0+0404 <[^>]*>
+[	]*400: R_MIPS_PC16	.L1.2-0x4
+[	]*400: R_MIPS_NONE	\*ABS\*-0x4
+[	]*400: R_MIPS_NONE	\*ABS\*-0x4
+0+0404 <[^>]*> 00000000 	nop
+0+0408 <[^>]*> 18020000 	blezalc	v0,0+040c <[^>]*>
+[	]*408: R_MIPS_PC16	ext-0x4
+[	]*408: R_MIPS_NONE	\*ABS\*-0x4
+[	]*408: R_MIPS_NONE	\*ABS\*-0x4
+0+040c <[^>]*> 00000000 	nop
+0+0410 <[^>]*> 18020000 	blezalc	v0,0+0414 <[^>]*>
+[	]*410: R_MIPS_PC16	L0.-0x20000
+[	]*410: R_MIPS_NONE	\*ABS\*-0x20000
+[	]*410: R_MIPS_NONE	\*ABS\*-0x20000
+0+0414 <[^>]*> 00000000 	nop
+0+0418 <[^>]*> 18020000 	blezalc	v0,0+041c <[^>]*>
+[	]*418: R_MIPS_PC16	L0.\+0x1fffc
+[	]*418: R_MIPS_NONE	\*ABS\*\+0x1fffc
+[	]*418: R_MIPS_NONE	\*ABS\*\+0x1fffc
+0+041c <[^>]*> 00000000 	nop
+0+0420 <[^>]*> 18020000 	blezalc	v0,0+0424 <[^>]*>
+[	]*420: R_MIPS_PC16	.L1.2-0x4
+[	]*420: R_MIPS_NONE	\*ABS\*-0x4
+[	]*420: R_MIPS_NONE	\*ABS\*-0x4
+0+0424 <[^>]*> 00000000 	nop
+0+0428 <[^>]*> 18420000 	bgezalc	v0,0+042c <[^>]*>
+[	]*428: R_MIPS_PC16	ext-0x4
+[	]*428: R_MIPS_NONE	\*ABS\*-0x4
+[	]*428: R_MIPS_NONE	\*ABS\*-0x4
+0+042c <[^>]*> 00000000 	nop
+0+0430 <[^>]*> 18420000 	bgezalc	v0,0+0434 <[^>]*>
+[	]*430: R_MIPS_PC16	L0.-0x20000
+[	]*430: R_MIPS_NONE	\*ABS\*-0x20000
+[	]*430: R_MIPS_NONE	\*ABS\*-0x20000
+0+0434 <[^>]*> 00000000 	nop
+0+0438 <[^>]*> 18420000 	bgezalc	v0,0+043c <[^>]*>
+[	]*438: R_MIPS_PC16	L0.\+0x1fffc
+[	]*438: R_MIPS_NONE	\*ABS\*\+0x1fffc
+[	]*438: R_MIPS_NONE	\*ABS\*\+0x1fffc
+0+043c <[^>]*> 00000000 	nop
+0+0440 <[^>]*> 18420000 	bgezalc	v0,0+0444 <[^>]*>
+[	]*440: R_MIPS_PC16	.L1.2-0x4
+[	]*440: R_MIPS_NONE	\*ABS\*-0x4
+[	]*440: R_MIPS_NONE	\*ABS\*-0x4
+0+0444 <[^>]*> 00000000 	nop
+0+0448 <[^>]*> 18430000 	bgeuc	v0,v1,0+044c <[^>]*>
+[	]*448: R_MIPS_PC16	ext-0x4
+[	]*448: R_MIPS_NONE	\*ABS\*-0x4
+[	]*448: R_MIPS_NONE	\*ABS\*-0x4
+0+044c <[^>]*> 00000000 	nop
+0+0450 <[^>]*> 18430000 	bgeuc	v0,v1,0+0454 <[^>]*>
+[	]*450: R_MIPS_PC16	L0.-0x20000
+[	]*450: R_MIPS_NONE	\*ABS\*-0x20000
+[	]*450: R_MIPS_NONE	\*ABS\*-0x20000
+0+0454 <[^>]*> 00000000 	nop
+0+0458 <[^>]*> 18430000 	bgeuc	v0,v1,0+045c <[^>]*>
+[	]*458: R_MIPS_PC16	L0.\+0x1fffc
+[	]*458: R_MIPS_NONE	\*ABS\*\+0x1fffc
+[	]*458: R_MIPS_NONE	\*ABS\*\+0x1fffc
+0+045c <[^>]*> 00000000 	nop
+0+0460 <[^>]*> 18430000 	bgeuc	v0,v1,0+0464 <[^>]*>
+[	]*460: R_MIPS_PC16	.L1.2-0x4
+[	]*460: R_MIPS_NONE	\*ABS\*-0x4
+[	]*460: R_MIPS_NONE	\*ABS\*-0x4
+0+0464 <[^>]*> 00000000 	nop
+0+0468 <[^>]*> 18620000 	bgeuc	v1,v0,0+046c <[^>]*>
+[	]*468: R_MIPS_PC16	.L1.2-0x4
+[	]*468: R_MIPS_NONE	\*ABS\*-0x4
+[	]*468: R_MIPS_NONE	\*ABS\*-0x4
+0+046c <[^>]*> 00000000 	nop
+0+0470 <[^>]*> 1c020000 	bgtzalc	v0,0+0474 <[^>]*>
+[	]*470: R_MIPS_PC16	ext-0x4
+[	]*470: R_MIPS_NONE	\*ABS\*-0x4
+[	]*470: R_MIPS_NONE	\*ABS\*-0x4
+0+0474 <[^>]*> 00000000 	nop
+0+0478 <[^>]*> 1c020000 	bgtzalc	v0,0+047c <[^>]*>
+[	]*478: R_MIPS_PC16	L0.-0x20000
+[	]*478: R_MIPS_NONE	\*ABS\*-0x20000
+[	]*478: R_MIPS_NONE	\*ABS\*-0x20000
+0+047c <[^>]*> 00000000 	nop
+0+0480 <[^>]*> 1c020000 	bgtzalc	v0,0+0484 <[^>]*>
+[	]*480: R_MIPS_PC16	L0.\+0x1fffc
+[	]*480: R_MIPS_NONE	\*ABS\*\+0x1fffc
+[	]*480: R_MIPS_NONE	\*ABS\*\+0x1fffc
+0+0484 <[^>]*> 00000000 	nop
+0+0488 <[^>]*> 1c020000 	bgtzalc	v0,0+048c <[^>]*>
+[	]*488: R_MIPS_PC16	.L1.2-0x4
+[	]*488: R_MIPS_NONE	\*ABS\*-0x4
+[	]*488: R_MIPS_NONE	\*ABS\*-0x4
+0+048c <[^>]*> 00000000 	nop
+0+0490 <[^>]*> 1c420000 	bltzalc	v0,0+0494 <[^>]*>
+[	]*490: R_MIPS_PC16	ext-0x4
+[	]*490: R_MIPS_NONE	\*ABS\*-0x4
+[	]*490: R_MIPS_NONE	\*ABS\*-0x4
+0+0494 <[^>]*> 00000000 	nop
+0+0498 <[^>]*> 1c420000 	bltzalc	v0,0+049c <[^>]*>
+[	]*498: R_MIPS_PC16	L0.-0x20000
+[	]*498: R_MIPS_NONE	\*ABS\*-0x20000
+[	]*498: R_MIPS_NONE	\*ABS\*-0x20000
+0+049c <[^>]*> 00000000 	nop
+0+04a0 <[^>]*> 1c420000 	bltzalc	v0,0+04a4 <[^>]*>
+[	]*4a0: R_MIPS_PC16	L0.\+0x1fffc
+[	]*4a0: R_MIPS_NONE	\*ABS\*\+0x1fffc
+[	]*4a0: R_MIPS_NONE	\*ABS\*\+0x1fffc
+0+04a4 <[^>]*> 00000000 	nop
+0+04a8 <[^>]*> 1c420000 	bltzalc	v0,0+04ac <[^>]*>
+[	]*4a8: R_MIPS_PC16	.L1.2-0x4
+[	]*4a8: R_MIPS_NONE	\*ABS\*-0x4
+[	]*4a8: R_MIPS_NONE	\*ABS\*-0x4
+0+04ac <[^>]*> 00000000 	nop
+0+04b0 <[^>]*> 1c430000 	bltuc	v0,v1,0+04b4 <[^>]*>
+[	]*4b0: R_MIPS_PC16	ext-0x4
+[	]*4b0: R_MIPS_NONE	\*ABS\*-0x4
+[	]*4b0: R_MIPS_NONE	\*ABS\*-0x4
+0+04b4 <[^>]*> 00000000 	nop
+0+04b8 <[^>]*> 1c430000 	bltuc	v0,v1,0+04bc <[^>]*>
+[	]*4b8: R_MIPS_PC16	L0.-0x20000
+[	]*4b8: R_MIPS_NONE	\*ABS\*-0x20000
+[	]*4b8: R_MIPS_NONE	\*ABS\*-0x20000
+0+04bc <[^>]*> 00000000 	nop
+0+04c0 <[^>]*> 1c430000 	bltuc	v0,v1,0+04c4 <[^>]*>
+[	]*4c0: R_MIPS_PC16	L0.\+0x1fffc
+[	]*4c0: R_MIPS_NONE	\*ABS\*\+0x1fffc
+[	]*4c0: R_MIPS_NONE	\*ABS\*\+0x1fffc
+0+04c4 <[^>]*> 00000000 	nop
+0+04c8 <[^>]*> 1c430000 	bltuc	v0,v1,0+04cc <[^>]*>
+[	]*4c8: R_MIPS_PC16	.L1.2-0x4
+[	]*4c8: R_MIPS_NONE	\*ABS\*-0x4
+[	]*4c8: R_MIPS_NONE	\*ABS\*-0x4
+0+04cc <[^>]*> 00000000 	nop
+0+04d0 <[^>]*> 1c620000 	bltuc	v1,v0,0+04d4 <[^>]*>
+[	]*4d0: R_MIPS_PC16	.L1.2-0x4
+[	]*4d0: R_MIPS_NONE	\*ABS\*-0x4
+[	]*4d0: R_MIPS_NONE	\*ABS\*-0x4
+0+04d4 <[^>]*> 00000000 	nop
+0+04d8 <[^>]*> c8000000 	bc	0+04dc <[^>]*>
+[	]*4d8: R_MIPS_PC26_S2	ext-0x4
+[	]*4d8: R_MIPS_NONE	\*ABS\*-0x4
+[	]*4d8: R_MIPS_NONE	\*ABS\*-0x4
+0+04dc <[^>]*> c8000000 	bc	0+04e0 <[^>]*>
+[	]*4dc: R_MIPS_PC26_S2	L0.-0x8000000
+[	]*4dc: R_MIPS_NONE	\*ABS\*-0x8000000
+[	]*4dc: R_MIPS_NONE	\*ABS\*-0x8000000
+0+04e0 <[^>]*> c8000000 	bc	0+04e4 <[^>]*>
+[	]*4e0: R_MIPS_PC26_S2	L0.\+0x7fffffc
+[	]*4e0: R_MIPS_NONE	\*ABS\*\+0x7fffffc
+[	]*4e0: R_MIPS_NONE	\*ABS\*\+0x7fffffc
+0+04e4 <[^>]*> c8000000 	bc	0+04e8 <[^>]*>
+[	]*4e4: R_MIPS_PC26_S2	.L1.2-0x4
+[	]*4e4: R_MIPS_NONE	\*ABS\*-0x4
+[	]*4e4: R_MIPS_NONE	\*ABS\*-0x4
+0+04e8 <[^>]*> e8000000 	balc	0+04ec <[^>]*>
+[	]*4e8: R_MIPS_PC26_S2	ext-0x4
+[	]*4e8: R_MIPS_NONE	\*ABS\*-0x4
+[	]*4e8: R_MIPS_NONE	\*ABS\*-0x4
+0+04ec <[^>]*> e8000000 	balc	0+04f0 <[^>]*>
+[	]*4ec: R_MIPS_PC26_S2	L0.-0x8000000
+[	]*4ec: R_MIPS_NONE	\*ABS\*-0x8000000
+[	]*4ec: R_MIPS_NONE	\*ABS\*-0x8000000
+0+04f0 <[^>]*> e8000000 	balc	0+04f4 <[^>]*>
+[	]*4f0: R_MIPS_PC26_S2	L0.\+0x7fffffc
+[	]*4f0: R_MIPS_NONE	\*ABS\*\+0x7fffffc
+[	]*4f0: R_MIPS_NONE	\*ABS\*\+0x7fffffc
+0+04f4 <[^>]*> e8000000 	balc	0+04f8 <[^>]*>
+[	]*4f4: R_MIPS_PC26_S2	.L1.2-0x4
+[	]*4f4: R_MIPS_NONE	\*ABS\*-0x4
+[	]*4f4: R_MIPS_NONE	\*ABS\*-0x4
+0+04f8 <[^>]*> d8400000 	beqzc	v0,0+04fc <[^>]*>
+[	]*4f8: R_MIPS_PC21_S2	ext-0x4
+[	]*4f8: R_MIPS_NONE	\*ABS\*-0x4
+[	]*4f8: R_MIPS_NONE	\*ABS\*-0x4
+0+04fc <[^>]*> 00000000 	nop
+0+0500 <[^>]*> d8400000 	beqzc	v0,0+0504 <[^>]*>
+[	]*500: R_MIPS_PC21_S2	L0.-0x400000
+[	]*500: R_MIPS_NONE	\*ABS\*-0x400000
+[	]*500: R_MIPS_NONE	\*ABS\*-0x400000
+0+0504 <[^>]*> 00000000 	nop
+0+0508 <[^>]*> d8400000 	beqzc	v0,0+050c <[^>]*>
+[	]*508: R_MIPS_PC21_S2	L0.\+0x3ffffc
+[	]*508: R_MIPS_NONE	\*ABS\*\+0x3ffffc
+[	]*508: R_MIPS_NONE	\*ABS\*\+0x3ffffc
+0+050c <[^>]*> 00000000 	nop
+0+0510 <[^>]*> d8400000 	beqzc	v0,0+0514 <[^>]*>
+[	]*510: R_MIPS_PC21_S2	.L1.2-0x4
+[	]*510: R_MIPS_NONE	\*ABS\*-0x4
+[	]*510: R_MIPS_NONE	\*ABS\*-0x4
+0+0514 <[^>]*> 00000000 	nop
+0+0518 <[^>]*> d8038000 	jic	v1,-32768
+0+051c <[^>]*> d8037fff 	jic	v1,32767
+0+0520 <[^>]*> d81f0000 	jrc	ra
+0+0524 <[^>]*> f8400000 	bnezc	v0,0+0528 <[^>]*>
+[	]*524: R_MIPS_PC21_S2	ext-0x4
+[	]*524: R_MIPS_NONE	\*ABS\*-0x4
+[	]*524: R_MIPS_NONE	\*ABS\*-0x4
+0+0528 <[^>]*> 00000000 	nop
+0+052c <[^>]*> f8400000 	bnezc	v0,0+0530 <[^>]*>
+[	]*52c: R_MIPS_PC21_S2	L0.-0x400000
+[	]*52c: R_MIPS_NONE	\*ABS\*-0x400000
+[	]*52c: R_MIPS_NONE	\*ABS\*-0x400000
+0+0530 <[^>]*> 00000000 	nop
+0+0534 <[^>]*> f8400000 	bnezc	v0,0+0538 <[^>]*>
+[	]*534: R_MIPS_PC21_S2	L0.\+0x3ffffc
+[	]*534: R_MIPS_NONE	\*ABS\*\+0x3ffffc
+[	]*534: R_MIPS_NONE	\*ABS\*\+0x3ffffc
+0+0538 <[^>]*> 00000000 	nop
+0+053c <[^>]*> f8400000 	bnezc	v0,0+0540 <[^>]*>
+[	]*53c: R_MIPS_PC21_S2	.L1.2-0x4
+[	]*53c: R_MIPS_NONE	\*ABS\*-0x4
+[	]*53c: R_MIPS_NONE	\*ABS\*-0x4
+0+0540 <[^>]*> 00000000 	nop
+0+0544 <[^>]*> f8038000 	jialc	v1,-32768
+0+0548 <[^>]*> f8037fff 	jialc	v1,32767
+0+054c <[^>]*> 3c43ffff 	aui	v1,v0,0xffff
+0+0550 <[^>]*> ec600000 	lapc	v1,0+0550 <[^>]*>
+[	]*550: R_MIPS_PC19_S2	.L1.2
+[	]*550: R_MIPS_NONE	\*ABS\*
+[	]*550: R_MIPS_NONE	\*ABS\*
+0+0554 <[^>]*> ec800000 	lapc	a0,0+0554 <[^>]*>
+[	]*554: R_MIPS_PC19_S2	L0.-0x100000
+[	]*554: R_MIPS_NONE	\*ABS\*-0x100000
+[	]*554: R_MIPS_NONE	\*ABS\*-0x100000
+0+0558 <[^>]*> ec800000 	lapc	a0,0+0558 <[^>]*>
+[	]*558: R_MIPS_PC19_S2	L0.\+0xffffc
+[	]*558: R_MIPS_NONE	\*ABS\*\+0xffffc
+[	]*558: R_MIPS_NONE	\*ABS\*\+0xffffc
+0+055c <[^>]*> ec840000 	lapc	a0,f+ffff0055c <[^>]*>
+0+0560 <[^>]*> ec83ffff 	lapc	a0,000000000010055c <[^>]*>
+0+0564 <[^>]*> ec7effff 	auipc	v1,0xffff
+0+0568 <[^>]*> ec7fffff 	aluipc	v1,0xffff
+0+056c <[^>]*> ec880000 	lwpc	a0,0+056c <[^>]*>
+[	]*56c: R_MIPS_PC19_S2	.L1.2
+[	]*56c: R_MIPS_NONE	\*ABS\*
+[	]*56c: R_MIPS_NONE	\*ABS\*
+0+0570 <[^>]*> ec880000 	lwpc	a0,0+0570 <[^>]*>
+[	]*570: R_MIPS_PC19_S2	L0.-0x100000
+[	]*570: R_MIPS_NONE	\*ABS\*-0x100000
+[	]*570: R_MIPS_NONE	\*ABS\*-0x100000
+0+0574 <[^>]*> ec880000 	lwpc	a0,0+0574 <[^>]*>
+[	]*574: R_MIPS_PC19_S2	L0.\+0xffffc
+[	]*574: R_MIPS_NONE	\*ABS\*\+0xffffc
+[	]*574: R_MIPS_NONE	\*ABS\*\+0xffffc
+0+0578 <[^>]*> ec8c0000 	lwpc	a0,f+ffff00578 <[^>]*>
+0+057c <[^>]*> ec8bffff 	lwpc	a0,0000000000100578 <[^>]*>
+0+0580 <[^>]*> 00000000 	nop
+0+0584 <[^>]*> ec83ffff 	lapc	a0,0000000000100580 <[^>]*>
+	\.\.\.
diff --git a/gas/testsuite/gas/mips/r6-removed.l b/gas/testsuite/gas/mips/r6-removed.l
new file mode 100644
index 00000000000..fc998c4fc49
--- /dev/null
+++ b/gas/testsuite/gas/mips/r6-removed.l
@@ -0,0 +1,196 @@
+.*: Assembler messages:
+.*:3: Error: opcode not supported on this processor: .* \(.*\) `abs.ps \$f0,\$f2'
+.*:4: Error: opcode not supported on this processor: .* \(.*\) `add.ps \$f0,\$f2,\$f2'
+.*:5: Error: opcode not supported on this processor: .* \(.*\) `addi \$15,\$16,256'
+.*:6: Error: opcode not supported on this processor: .* \(.*\) `alnv.ps \$f0,\$f2,\$f2,\$3'
+.*:7: Error: opcode not supported on this processor: .* \(.*\) `bc0f 1f'
+.*:8: Error: opcode not supported on this processor: .* \(.*\) `bc0fl 1f'
+.*:9: Error: opcode not supported on this processor: .* \(.*\) `bc0t 1f'
+.*:10: Error: opcode not supported on this processor: .* \(.*\) `bc0tl 1f'
+.*:11: Error: opcode not supported on this processor: .* \(.*\) `bc1f 1f'
+.*:12: Error: opcode not supported on this processor: .* \(.*\) `bc1fl 1f'
+.*:13: Error: opcode not supported on this processor: .* \(.*\) `bc1t 1f'
+.*:14: Error: opcode not supported on this processor: .* \(.*\) `bc1tl 1f'
+.*:15: Error: opcode not supported on this processor: .* \(.*\) `bc2f 1f'
+.*:16: Error: opcode not supported on this processor: .* \(.*\) `bc2fl 1f'
+.*:17: Error: opcode not supported on this processor: .* \(.*\) `bc2t 1f'
+.*:18: Error: opcode not supported on this processor: .* \(.*\) `bc2tl 1f'
+.*:19: Error: opcode not supported on this processor: .* \(.*\) `bc3f 1f'
+.*:20: Error: opcode not supported on this processor: .* \(.*\) `bc3fl 1f'
+.*:21: Error: opcode not supported on this processor: .* \(.*\) `bc3t 1f'
+.*:22: Error: opcode not supported on this processor: .* \(.*\) `bc3tl 1f'
+.*:23: Error: opcode not supported on this processor: .* \(.*\) `beql \$28,\$29,1f'
+.*:24: Error: opcode not supported on this processor: .* \(.*\) `bgezal \$4,1f'
+.*:25: Error: opcode not supported on this processor: .* \(.*\) `bgezall \$28,1f'
+.*:26: Error: opcode not supported on this processor: .* \(.*\) `bgezl \$28,1f'
+.*:27: Error: opcode not supported on this processor: .* \(.*\) `bgtzl \$28,1f'
+.*:28: Error: opcode not supported on this processor: .* \(.*\) `blezl \$28,1f'
+.*:29: Error: opcode not supported on this processor: .* \(.*\) `bltzal \$4,1f'
+.*:30: Error: opcode not supported on this processor: .* \(.*\) `bltzall \$28,1f'
+.*:31: Error: opcode not supported on this processor: .* \(.*\) `bltzl \$28,1f'
+.*:32: Error: opcode not supported on this processor: .* \(.*\) `bnel \$28,\$29,1f'
+.*:33: Error: opcode not supported on this processor: .* \(.*\) `c.f.s \$f0,\$f2'
+.*:34: Error: opcode not supported on this processor: .* \(.*\) `c.un.s \$f0,\$f2'
+.*:35: Error: opcode not supported on this processor: .* \(.*\) `c.eq.s \$f0,\$f2'
+.*:36: Error: opcode not supported on this processor: .* \(.*\) `c.ueq.s \$f0,\$f2'
+.*:37: Error: opcode not supported on this processor: .* \(.*\) `c.olt.s \$f0,\$f2'
+.*:38: Error: opcode not supported on this processor: .* \(.*\) `c.ult.s \$f0,\$f2'
+.*:39: Error: opcode not supported on this processor: .* \(.*\) `c.ole.s \$f0,\$f2'
+.*:40: Error: opcode not supported on this processor: .* \(.*\) `c.ule.s \$f0,\$f2'
+.*:41: Error: opcode not supported on this processor: .* \(.*\) `c.sf.s \$f0,\$f2'
+.*:42: Error: opcode not supported on this processor: .* \(.*\) `c.ngle.s \$f0,\$f2'
+.*:43: Error: opcode not supported on this processor: .* \(.*\) `c.seq.s \$f0,\$f2'
+.*:44: Error: opcode not supported on this processor: .* \(.*\) `c.ngl.s \$f0,\$f2'
+.*:45: Error: opcode not supported on this processor: .* \(.*\) `c.lt.s \$f0,\$f2'
+.*:46: Error: opcode not supported on this processor: .* \(.*\) `c.nge.s \$f0,\$f2'
+.*:47: Error: opcode not supported on this processor: .* \(.*\) `c.le.s \$f0,\$f2'
+.*:48: Error: opcode not supported on this processor: .* \(.*\) `c.ngt.s \$f0,\$f2'
+.*:49: Error: opcode not supported on this processor: .* \(.*\) `c.f.ps \$f0,\$f2'
+.*:50: Error: opcode not supported on this processor: .* \(.*\) `c.un.ps \$f0,\$f2'
+.*:51: Error: opcode not supported on this processor: .* \(.*\) `c.eq.ps \$f0,\$f2'
+.*:52: Error: opcode not supported on this processor: .* \(.*\) `c.ueq.ps \$f0,\$f2'
+.*:53: Error: opcode not supported on this processor: .* \(.*\) `c.olt.ps \$f0,\$f2'
+.*:54: Error: opcode not supported on this processor: .* \(.*\) `c.ult.ps \$f0,\$f2'
+.*:55: Error: opcode not supported on this processor: .* \(.*\) `c.ole.ps \$f0,\$f2'
+.*:56: Error: opcode not supported on this processor: .* \(.*\) `c.ule.ps \$f0,\$f2'
+.*:57: Error: opcode not supported on this processor: .* \(.*\) `c.sf.ps \$f0,\$f2'
+.*:58: Error: opcode not supported on this processor: .* \(.*\) `c.ngle.ps \$f0,\$f2'
+.*:59: Error: opcode not supported on this processor: .* \(.*\) `c.seq.ps \$f0,\$f2'
+.*:60: Error: opcode not supported on this processor: .* \(.*\) `c.ngl.ps \$f0,\$f2'
+.*:61: Error: opcode not supported on this processor: .* \(.*\) `c.lt.ps \$f0,\$f2'
+.*:62: Error: opcode not supported on this processor: .* \(.*\) `c.nge.ps \$f0,\$f2'
+.*:63: Error: opcode not supported on this processor: .* \(.*\) `c.le.ps \$f0,\$f2'
+.*:64: Error: opcode not supported on this processor: .* \(.*\) `c.ngt.ps \$f0,\$f2'
+.*:65: Error: opcode not supported on this processor: .* \(.*\) `c.f.d \$f0,\$f2'
+.*:66: Error: opcode not supported on this processor: .* \(.*\) `c.un.d \$f0,\$f2'
+.*:67: Error: opcode not supported on this processor: .* \(.*\) `c.eq.d \$f0,\$f2'
+.*:68: Error: opcode not supported on this processor: .* \(.*\) `c.ueq.d \$f0,\$f2'
+.*:69: Error: opcode not supported on this processor: .* \(.*\) `c.olt.d \$f0,\$f2'
+.*:70: Error: opcode not supported on this processor: .* \(.*\) `c.ult.d \$f0,\$f2'
+.*:71: Error: opcode not supported on this processor: .* \(.*\) `c.ole.d \$f0,\$f2'
+.*:72: Error: opcode not supported on this processor: .* \(.*\) `c.ule.d \$f0,\$f2'
+.*:73: Error: opcode not supported on this processor: .* \(.*\) `c.sf.d \$f0,\$f2'
+.*:74: Error: opcode not supported on this processor: .* \(.*\) `c.ngle.d \$f0,\$f2'
+.*:75: Error: opcode not supported on this processor: .* \(.*\) `c.seq.d \$f0,\$f2'
+.*:76: Error: opcode not supported on this processor: .* \(.*\) `c.ngl.d \$f0,\$f2'
+.*:77: Error: opcode not supported on this processor: .* \(.*\) `c.lt.d \$f0,\$f2'
+.*:78: Error: opcode not supported on this processor: .* \(.*\) `c.nge.d \$f0,\$f2'
+.*:79: Error: opcode not supported on this processor: .* \(.*\) `c.le.d \$f0,\$f2'
+.*:80: Error: opcode not supported on this processor: .* \(.*\) `c.ngt.d \$f0,\$f2'
+.*:81: Error: opcode not supported on this processor: .* \(.*\) `c.f.s \$fcc2,\$f0,\$f2'
+.*:82: Error: opcode not supported on this processor: .* \(.*\) `c.un.s \$fcc2,\$f0,\$f2'
+.*:83: Error: opcode not supported on this processor: .* \(.*\) `c.eq.s \$fcc2,\$f0,\$f2'
+.*:84: Error: opcode not supported on this processor: .* \(.*\) `c.ueq.s \$fcc2,\$f0,\$f2'
+.*:85: Error: opcode not supported on this processor: .* \(.*\) `c.olt.s \$fcc2,\$f0,\$f2'
+.*:86: Error: opcode not supported on this processor: .* \(.*\) `c.ult.s \$fcc2,\$f0,\$f2'
+.*:87: Error: opcode not supported on this processor: .* \(.*\) `c.ole.s \$fcc2,\$f0,\$f2'
+.*:88: Error: opcode not supported on this processor: .* \(.*\) `c.ule.s \$fcc2,\$f0,\$f2'
+.*:89: Error: opcode not supported on this processor: .* \(.*\) `c.sf.s \$fcc2,\$f0,\$f2'
+.*:90: Error: opcode not supported on this processor: .* \(.*\) `c.ngle.s \$fcc2,\$f0,\$f2'
+.*:91: Error: opcode not supported on this processor: .* \(.*\) `c.seq.s \$fcc2,\$f0,\$f2'
+.*:92: Error: opcode not supported on this processor: .* \(.*\) `c.ngl.s \$fcc2,\$f0,\$f2'
+.*:93: Error: opcode not supported on this processor: .* \(.*\) `c.lt.s \$fcc2,\$f0,\$f2'
+.*:94: Error: opcode not supported on this processor: .* \(.*\) `c.nge.s \$fcc2,\$f0,\$f2'
+.*:95: Error: opcode not supported on this processor: .* \(.*\) `c.le.s \$fcc2,\$f0,\$f2'
+.*:96: Error: opcode not supported on this processor: .* \(.*\) `c.ngt.s \$fcc2,\$f0,\$f2'
+.*:97: Error: opcode not supported on this processor: .* \(.*\) `c.f.ps \$fcc2,\$f0,\$f2'
+.*:98: Error: opcode not supported on this processor: .* \(.*\) `c.un.ps \$fcc2,\$f0,\$f2'
+.*:99: Error: opcode not supported on this processor: .* \(.*\) `c.eq.ps \$fcc2,\$f0,\$f2'
+.*:100: Error: opcode not supported on this processor: .* \(.*\) `c.ueq.ps \$fcc2,\$f0,\$f2'
+.*:101: Error: opcode not supported on this processor: .* \(.*\) `c.olt.ps \$fcc2,\$f0,\$f2'
+.*:102: Error: opcode not supported on this processor: .* \(.*\) `c.ult.ps \$fcc2,\$f0,\$f2'
+.*:103: Error: opcode not supported on this processor: .* \(.*\) `c.ole.ps \$fcc2,\$f0,\$f2'
+.*:104: Error: opcode not supported on this processor: .* \(.*\) `c.ule.ps \$fcc2,\$f0,\$f2'
+.*:105: Error: opcode not supported on this processor: .* \(.*\) `c.sf.ps \$fcc2,\$f0,\$f2'
+.*:106: Error: opcode not supported on this processor: .* \(.*\) `c.ngle.ps \$fcc2,\$f0,\$f2'
+.*:107: Error: opcode not supported on this processor: .* \(.*\) `c.seq.ps \$fcc2,\$f0,\$f2'
+.*:108: Error: opcode not supported on this processor: .* \(.*\) `c.ngl.ps \$fcc2,\$f0,\$f2'
+.*:109: Error: opcode not supported on this processor: .* \(.*\) `c.lt.ps \$fcc2,\$f0,\$f2'
+.*:110: Error: opcode not supported on this processor: .* \(.*\) `c.nge.ps \$fcc2,\$f0,\$f2'
+.*:111: Error: opcode not supported on this processor: .* \(.*\) `c.le.ps \$fcc2,\$f0,\$f2'
+.*:112: Error: opcode not supported on this processor: .* \(.*\) `c.ngt.ps \$fcc2,\$f0,\$f2'
+.*:113: Error: opcode not supported on this processor: .* \(.*\) `c.f.d \$fcc2,\$f0,\$f2'
+.*:114: Error: opcode not supported on this processor: .* \(.*\) `c.un.d \$fcc2,\$f0,\$f2'
+.*:115: Error: opcode not supported on this processor: .* \(.*\) `c.eq.d \$fcc2,\$f0,\$f2'
+.*:116: Error: opcode not supported on this processor: .* \(.*\) `c.ueq.d \$fcc2,\$f0,\$f2'
+.*:117: Error: opcode not supported on this processor: .* \(.*\) `c.olt.d \$fcc2,\$f0,\$f2'
+.*:118: Error: opcode not supported on this processor: .* \(.*\) `c.ult.d \$fcc2,\$f0,\$f2'
+.*:119: Error: opcode not supported on this processor: .* \(.*\) `c.ole.d \$fcc2,\$f0,\$f2'
+.*:120: Error: opcode not supported on this processor: .* \(.*\) `c.ule.d \$fcc2,\$f0,\$f2'
+.*:121: Error: opcode not supported on this processor: .* \(.*\) `c.sf.d \$fcc2,\$f0,\$f2'
+.*:122: Error: opcode not supported on this processor: .* \(.*\) `c.ngle.d \$fcc2,\$f0,\$f2'
+.*:123: Error: opcode not supported on this processor: .* \(.*\) `c.seq.d \$fcc2,\$f0,\$f2'
+.*:124: Error: opcode not supported on this processor: .* \(.*\) `c.ngl.d \$fcc2,\$f0,\$f2'
+.*:125: Error: opcode not supported on this processor: .* \(.*\) `c.lt.d \$fcc2,\$f0,\$f2'
+.*:126: Error: opcode not supported on this processor: .* \(.*\) `c.nge.d \$fcc2,\$f0,\$f2'
+.*:127: Error: opcode not supported on this processor: .* \(.*\) `c.le.d \$fcc2,\$f0,\$f2'
+.*:128: Error: opcode not supported on this processor: .* \(.*\) `c.ngt.d \$fcc2,\$f0,\$f2'
+.*:129: Error: opcode not supported on this processor: .* \(.*\) `cvt.ps.s \$f2,\$f3,\$f4'
+.*:130: Error: opcode not supported on this processor: .* \(.*\) `jalx 1f'
+.*:131: Error: opcode not supported on this processor: .* \(.*\) `ldxc1 \$f0,\$0\(\$2\)'
+.*:132: Error: opcode not supported on this processor: .* \(.*\) `luxc1 \$f0,\$0\(\$2\)'
+.*:133: Error: opcode not supported on this processor: .* \(.*\) `lwl \$2,1\(\$3\)'
+.*:134: Error: opcode not supported on this processor: .* \(.*\) `lwle \$4,0\(\$6\)'
+.*:135: Error: opcode not supported on this processor: .* \(.*\) `lwr \$2,1\(\$3\)'
+.*:136: Error: opcode not supported on this processor: .* \(.*\) `lwre \$4,0\(\$6\)'
+.*:137: Error: opcode not supported on this processor: .* \(.*\) `lwxc1 \$f0,\$0\(\$2\)'
+.*:138: Error: opcode not supported on this processor: .* \(.*\) `madd \$2,\$3'
+.*:139: Error: opcode not supported on this processor: .* \(.*\) `maddu \$2,\$3'
+.*:140: Error: opcode not supported on this processor: .* \(.*\) `madd.s \$f5,\$f6,\$f7,\$f8'
+.*:141: Error: opcode not supported on this processor: .* \(.*\) `madd.d \$f6,\$f8,\$f10,\$f12'
+.*:142: Error: opcode not supported on this processor: .* \(.*\) `madd.ps \$f6,\$f8,\$f10,\$f12'
+.*:143: Error: opcode not supported on this processor: .* \(.*\) `mfhi \$2'
+.*:144: Error: opcode not supported on this processor: .* \(.*\) `mflo \$2'
+.*:145: Error: opcode not supported on this processor: .* \(.*\) `mov.ps \$f10,\$f20'
+.*:146: Error: opcode not supported on this processor: .* \(.*\) `movf \$8,\$9,\$fcc0'
+.*:147: Error: opcode not supported on this processor: .* \(.*\) `movf.s \$f8,\$f9,\$fcc0'
+.*:148: Error: opcode not supported on this processor: .* \(.*\) `movf.d \$f8,\$f10,\$fcc0'
+.*:149: Error: opcode not supported on this processor: .* \(.*\) `movf.ps \$f8,\$f10,\$fcc0'
+.*:150: Error: opcode not supported on this processor: .* \(.*\) `movn \$2,\$3,\$4'
+.*:151: Error: opcode not supported on this processor: .* \(.*\) `movn.s \$f0,\$f2,\$10'
+.*:152: Error: opcode not supported on this processor: .* \(.*\) `movn.d \$f0,\$f2,\$10'
+.*:153: Error: opcode not supported on this processor: .* \(.*\) `movn.ps \$f0,\$f2,\$10'
+.*:154: Error: opcode not supported on this processor: .* \(.*\) `movt \$10,\$11,\$fcc2'
+.*:155: Error: opcode not supported on this processor: .* \(.*\) `movt.s \$f20,\$f21,\$fcc2'
+.*:156: Error: opcode not supported on this processor: .* \(.*\) `movt.d \$f20,\$f22,\$fcc2'
+.*:157: Error: opcode not supported on this processor: .* \(.*\) `movt.ps \$f20,\$f22,\$fcc2'
+.*:158: Error: opcode not supported on this processor: .* \(.*\) `movz \$5,\$6,\$7'
+.*:159: Error: opcode not supported on this processor: .* \(.*\) `movz.s \$f0,\$f2,\$10'
+.*:160: Error: opcode not supported on this processor: .* \(.*\) `movz.d \$f0,\$f2,\$10'
+.*:161: Error: opcode not supported on this processor: .* \(.*\) `movz.ps \$f0,\$f2,\$10'
+.*:162: Error: opcode not supported on this processor: .* \(.*\) `msub \$2,\$3'
+.*:163: Error: opcode not supported on this processor: .* \(.*\) `msubu \$2,\$3'
+.*:164: Error: opcode not supported on this processor: .* \(.*\) `msub.s \$f5,\$f6,\$f7,\$f8'
+.*:165: Error: opcode not supported on this processor: .* \(.*\) `msub.d \$f6,\$f8,\$f10,\$f12'
+.*:166: Error: opcode not supported on this processor: .* \(.*\) `msub.ps \$f6,\$f8,\$f10,\$f12'
+.*:167: Error: opcode not supported on this processor: .* \(.*\) `mthi \$2'
+.*:168: Error: opcode not supported on this processor: .* \(.*\) `mtlo \$2'
+.*:169: Error: opcode not supported on this processor: .* \(.*\) `mul.ps \$f10,\$f20,\$f22'
+.*:170: Error: opcode not supported on this processor: .* \(.*\) `mult \$2,\$3'
+.*:171: Error: opcode not supported on this processor: .* \(.*\) `multu \$2,\$3'
+.*:172: Error: opcode not supported on this processor: .* \(.*\) `neg.ps \$f22,\$f24'
+.*:173: Error: opcode not supported on this processor: .* \(.*\) `nmadd.s \$f5,\$f6,\$f7,\$f8'
+.*:174: Error: opcode not supported on this processor: .* \(.*\) `nmadd.d \$f6,\$f8,\$f10,\$f12'
+.*:175: Error: opcode not supported on this processor: .* \(.*\) `nmadd.ps \$f6,\$f8,\$f10,\$f12'
+.*:176: Error: opcode not supported on this processor: .* \(.*\) `nmsub.s \$f5,\$f6,\$f7,\$f8'
+.*:177: Error: opcode not supported on this processor: .* \(.*\) `nmsub.d \$f6,\$f8,\$f10,\$f12'
+.*:178: Error: opcode not supported on this processor: .* \(.*\) `nmsub.ps \$f6,\$f8,\$f10,\$f12'
+.*:179: Error: opcode not supported on this processor: .* \(.*\) `pll.ps \$f24,\$f20,\$f26'
+.*:180: Error: opcode not supported on this processor: .* \(.*\) `plu.ps \$f24,\$f20,\$f26'
+.*:181: Error: opcode not supported on this processor: .* \(.*\) `pul.ps \$f24,\$f20,\$f26'
+.*:182: Error: opcode not supported on this processor: .* \(.*\) `puu.ps \$f24,\$f20,\$f26'
+.*:183: Error: opcode not supported on this processor: .* \(.*\) `prefx 5,\$3\(\$5\)'
+.*:184: Error: opcode not supported on this processor: .* \(.*\) `sdxc1 \$f0,\$0\(\$2\)'
+.*:185: Error: opcode not supported on this processor: .* \(.*\) `sub.ps \$f20,\$f28,\$f26'
+.*:186: Error: opcode not supported on this processor: .* \(.*\) `suxc1 \$f0,\$0\(\$2\)'
+.*:187: Error: opcode not supported on this processor: .* \(.*\) `swl \$2,1\(\$3\)'
+.*:188: Error: opcode not supported on this processor: .* \(.*\) `swle \$4,0\(\$6\)'
+.*:189: Error: opcode not supported on this processor: .* \(.*\) `swr \$2,1\(\$3\)'
+.*:190: Error: opcode not supported on this processor: .* \(.*\) `swre \$4,0\(\$6\)'
+.*:191: Error: opcode not supported on this processor: .* \(.*\) `swxc1 \$f0,\$0\(\$2\)'
+.*:192: Error: opcode not supported on this processor: .* \(.*\) `teqi \$11,1024'
+.*:193: Error: opcode not supported on this processor: .* \(.*\) `tgei \$11,1024'
+.*:194: Error: opcode not supported on this processor: .* \(.*\) `tgeiu \$11,1024'
+.*:195: Error: opcode not supported on this processor: .* \(.*\) `tlti \$11,1024'
+.*:196: Error: opcode not supported on this processor: .* \(.*\) `tltiu \$11,1024'
+.*:197: Error: opcode not supported on this processor: .* \(.*\) `tnei \$11,1024'
diff --git a/gas/testsuite/gas/mips/r6-removed.s b/gas/testsuite/gas/mips/r6-removed.s
new file mode 100644
index 00000000000..00b044cb010
--- /dev/null
+++ b/gas/testsuite/gas/mips/r6-removed.s
@@ -0,0 +1,198 @@
+	.set	reorder
+	.set	eva
+	abs.ps	$f0,$f2
+	add.ps	$f0,$f2,$f2
+	addi	$15,$16,256
+	alnv.ps	$f0,$f2,$f2,$3
+	bc0f	1f
+	bc0fl	1f
+	bc0t	1f
+	bc0tl	1f
+	bc1f	1f
+	bc1fl	1f
+	bc1t	1f
+	bc1tl	1f
+	bc2f	1f
+	bc2fl	1f
+	bc2t	1f
+	bc2tl	1f
+	bc3f	1f
+	bc3fl	1f
+	bc3t	1f
+	bc3tl	1f
+	beql	$28,$29,1f
+	bgezal	$4,1f
+	bgezall	$28,1f
+	bgezl	$28,1f
+	bgtzl	$28,1f
+	blezl	$28,1f
+	bltzal	$4,1f
+	bltzall	$28,1f
+	bltzl	$28,1f
+	bnel	$28,$29,1f
+	c.f.s	$f0,$f2
+	c.un.s	$f0,$f2
+	c.eq.s	$f0,$f2
+	c.ueq.s	$f0,$f2
+	c.olt.s	$f0,$f2
+	c.ult.s	$f0,$f2
+	c.ole.s	$f0,$f2
+	c.ule.s	$f0,$f2
+	c.sf.s	$f0,$f2
+	c.ngle.s	$f0,$f2
+	c.seq.s	$f0,$f2
+	c.ngl.s	$f0,$f2
+	c.lt.s	$f0,$f2
+	c.nge.s	$f0,$f2
+	c.le.s	$f0,$f2
+	c.ngt.s	$f0,$f2
+	c.f.ps	$f0,$f2
+	c.un.ps	$f0,$f2
+	c.eq.ps	$f0,$f2
+	c.ueq.ps	$f0,$f2
+	c.olt.ps	$f0,$f2
+	c.ult.ps	$f0,$f2
+	c.ole.ps	$f0,$f2
+	c.ule.ps	$f0,$f2
+	c.sf.ps	$f0,$f2
+	c.ngle.ps	$f0,$f2
+	c.seq.ps	$f0,$f2
+	c.ngl.ps	$f0,$f2
+	c.lt.ps	$f0,$f2
+	c.nge.ps	$f0,$f2
+	c.le.ps	$f0,$f2
+	c.ngt.ps	$f0,$f2
+	c.f.d	$f0,$f2
+	c.un.d	$f0,$f2
+	c.eq.d	$f0,$f2
+	c.ueq.d	$f0,$f2
+	c.olt.d	$f0,$f2
+	c.ult.d	$f0,$f2
+	c.ole.d	$f0,$f2
+	c.ule.d	$f0,$f2
+	c.sf.d	$f0,$f2
+	c.ngle.d	$f0,$f2
+	c.seq.d		$f0,$f2
+	c.ngl.d		$f0,$f2
+	c.lt.d	$f0,$f2
+	c.nge.d	$f0,$f2
+	c.le.d	$f0,$f2
+	c.ngt.d	$f0,$f2
+	c.f.s	$fcc2, $f0,$f2
+	c.un.s	$fcc2, $f0,$f2
+	c.eq.s	$fcc2, $f0,$f2
+	c.ueq.s	$fcc2, $f0,$f2
+	c.olt.s	$fcc2, $f0,$f2
+	c.ult.s	$fcc2, $f0,$f2
+	c.ole.s	$fcc2, $f0,$f2
+	c.ule.s	$fcc2, $f0,$f2
+	c.sf.s	$fcc2, $f0,$f2
+	c.ngle.s	$fcc2, $f0,$f2
+	c.seq.s	$fcc2, $f0,$f2
+	c.ngl.s	$fcc2, $f0,$f2
+	c.lt.s	$fcc2, $f0,$f2
+	c.nge.s	$fcc2, $f0,$f2
+	c.le.s	$fcc2, $f0,$f2
+	c.ngt.s	$fcc2, $f0,$f2
+	c.f.ps	$fcc2, $f0,$f2
+	c.un.ps	$fcc2, $f0,$f2
+	c.eq.ps	$fcc2, $f0,$f2
+	c.ueq.ps	$fcc2, $f0,$f2
+	c.olt.ps	$fcc2, $f0,$f2
+	c.ult.ps	$fcc2, $f0,$f2
+	c.ole.ps	$fcc2, $f0,$f2
+	c.ule.ps	$fcc2, $f0,$f2
+	c.sf.ps	$fcc2, $f0,$f2
+	c.ngle.ps	$fcc2, $f0,$f2
+	c.seq.ps	$fcc2, $f0,$f2
+	c.ngl.ps	$fcc2, $f0,$f2
+	c.lt.ps	$fcc2, $f0,$f2
+	c.nge.ps	$fcc2, $f0,$f2
+	c.le.ps	$fcc2, $f0,$f2
+	c.ngt.ps	$fcc2, $f0,$f2
+	c.f.d	$fcc2, $f0,$f2
+	c.un.d	$fcc2, $f0,$f2
+	c.eq.d	$fcc2, $f0,$f2
+	c.ueq.d	$fcc2, $f0,$f2
+	c.olt.d	$fcc2, $f0,$f2
+	c.ult.d	$fcc2, $f0,$f2
+	c.ole.d	$fcc2, $f0,$f2
+	c.ule.d	$fcc2, $f0,$f2
+	c.sf.d	$fcc2, $f0,$f2
+	c.ngle.d	$fcc2, $f0,$f2
+	c.seq.d		$fcc2, $f0,$f2
+	c.ngl.d		$fcc2, $f0,$f2
+	c.lt.d	$fcc2, $f0,$f2
+	c.nge.d	$fcc2, $f0,$f2
+	c.le.d	$fcc2, $f0,$f2
+	c.ngt.d	$fcc2, $f0,$f2
+	cvt.ps.s	$f2,$f3,$f4
+	jalx	1f
+	ldxc1	$f0,$0($2)
+	luxc1	$f0,$0($2)
+	lwl	$2, 1($3)
+	lwle	$4,0($6)
+	lwr	$2, 1($3)
+	lwre	$4,0($6)
+	lwxc1	$f0,$0($2)
+	madd	$2,$3
+	maddu	$2,$3
+	madd.s	$f5,$f6,$f7,$f8
+	madd.d	$f6,$f8,$f10,$f12
+	madd.ps	$f6,$f8,$f10,$f12
+	mfhi	$2
+	mflo	$2
+	mov.ps	$f10,$f20
+	movf	$8,$9,$fcc0
+	movf.s	$f8,$f9,$fcc0
+	movf.d	$f8,$f10,$fcc0
+	movf.ps	$f8,$f10,$fcc0
+	movn	$2,$3,$4
+	movn.s	$f0,$f2,$10
+	movn.d	$f0,$f2,$10
+	movn.ps	$f0,$f2,$10
+	movt	$10,$11,$fcc2
+	movt.s	$f20,$f21,$fcc2
+	movt.d	$f20,$f22,$fcc2
+	movt.ps	$f20,$f22,$fcc2
+	movz	$5,$6,$7
+	movz.s	$f0,$f2,$10
+	movz.d	$f0,$f2,$10
+	movz.ps	$f0,$f2,$10
+	msub	$2,$3
+	msubu	$2,$3
+	msub.s	$f5,$f6,$f7,$f8
+	msub.d	$f6,$f8,$f10,$f12
+	msub.ps	$f6,$f8,$f10,$f12
+	mthi	$2
+	mtlo	$2
+	mul.ps	$f10,$f20,$f22
+	mult	$2,$3
+	multu	$2,$3
+	neg.ps	$f22,$f24
+	nmadd.s	$f5,$f6,$f7,$f8
+	nmadd.d	$f6,$f8,$f10,$f12
+	nmadd.ps	$f6,$f8,$f10,$f12
+	nmsub.s	$f5,$f6,$f7,$f8
+	nmsub.d	$f6,$f8,$f10,$f12
+	nmsub.ps	$f6,$f8,$f10,$f12
+	pll.ps	$f24,$f20,$f26
+	plu.ps	$f24,$f20,$f26
+	pul.ps	$f24,$f20,$f26
+	puu.ps	$f24,$f20,$f26
+	prefx   5, $3($5)
+	sdxc1	$f0,$0($2)
+	sub.ps	$f20,$f28,$f26
+	suxc1	$f0,$0($2)
+	swl	$2, 1($3)
+	swle	$4,0($6)
+	swr	$2, 1($3)
+	swre	$4,0($6)
+	swxc1	$f0,$0($2)
+	teqi	$11,1024
+	tgei	$11,1024
+	tgeiu	$11,1024
+	tlti	$11,1024
+	tltiu	$11,1024
+	tnei	$11,1024
+1:
diff --git a/gas/testsuite/gas/mips/r6.d b/gas/testsuite/gas/mips/r6.d
new file mode 100644
index 00000000000..0cfccb8c646
--- /dev/null
+++ b/gas/testsuite/gas/mips/r6.d
@@ -0,0 +1,492 @@
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS MIPSR6 instructions
+#as: -32
+
+# Check MIPSR6 instructions
+
+.*: +file format .*mips.*
+
+Disassembly of section .text:
+0+0000 <[^>]*> 46020818 	maddf.s	\$f0,\$f1,\$f2
+0+0004 <[^>]*> 462520d8 	maddf.d	\$f3,\$f4,\$f5
+0+0008 <[^>]*> 46083999 	msubf.s	\$f6,\$f7,\$f8
+0+000c <[^>]*> 462b5259 	msubf.d	\$f9,\$f10,\$f11
+0+0010 <[^>]*> 46820800 	cmp.af.s	\$f0,\$f1,\$f2
+0+0014 <[^>]*> 46a20800 	cmp.af.d	\$f0,\$f1,\$f2
+0+0018 <[^>]*> 46820801 	cmp.un.s	\$f0,\$f1,\$f2
+0+001c <[^>]*> 46a20801 	cmp.un.d	\$f0,\$f1,\$f2
+0+0020 <[^>]*> 46820802 	cmp.eq.s	\$f0,\$f1,\$f2
+0+0024 <[^>]*> 46a20802 	cmp.eq.d	\$f0,\$f1,\$f2
+0+0028 <[^>]*> 46820803 	cmp.ueq.s	\$f0,\$f1,\$f2
+0+002c <[^>]*> 46a20803 	cmp.ueq.d	\$f0,\$f1,\$f2
+0+0030 <[^>]*> 46820804 	cmp.lt.s	\$f0,\$f1,\$f2
+0+0034 <[^>]*> 46a20804 	cmp.lt.d	\$f0,\$f1,\$f2
+0+0038 <[^>]*> 46820805 	cmp.ult.s	\$f0,\$f1,\$f2
+0+003c <[^>]*> 46a20805 	cmp.ult.d	\$f0,\$f1,\$f2
+0+0040 <[^>]*> 46820806 	cmp.le.s	\$f0,\$f1,\$f2
+0+0044 <[^>]*> 46a20806 	cmp.le.d	\$f0,\$f1,\$f2
+0+0048 <[^>]*> 46820807 	cmp.ule.s	\$f0,\$f1,\$f2
+0+004c <[^>]*> 46a20807 	cmp.ule.d	\$f0,\$f1,\$f2
+0+0050 <[^>]*> 46820808 	cmp.saf.s	\$f0,\$f1,\$f2
+0+0054 <[^>]*> 46a20808 	cmp.saf.d	\$f0,\$f1,\$f2
+0+0058 <[^>]*> 46820809 	cmp.sun.s	\$f0,\$f1,\$f2
+0+005c <[^>]*> 46a20809 	cmp.sun.d	\$f0,\$f1,\$f2
+0+0060 <[^>]*> 4682080a 	cmp.seq.s	\$f0,\$f1,\$f2
+0+0064 <[^>]*> 46a2080a 	cmp.seq.d	\$f0,\$f1,\$f2
+0+0068 <[^>]*> 4682080b 	cmp.sueq.s	\$f0,\$f1,\$f2
+0+006c <[^>]*> 46a2080b 	cmp.sueq.d	\$f0,\$f1,\$f2
+0+0070 <[^>]*> 4682080c 	cmp.slt.s	\$f0,\$f1,\$f2
+0+0074 <[^>]*> 46a2080c 	cmp.slt.d	\$f0,\$f1,\$f2
+0+0078 <[^>]*> 4682080d 	cmp.sult.s	\$f0,\$f1,\$f2
+0+007c <[^>]*> 46a2080d 	cmp.sult.d	\$f0,\$f1,\$f2
+0+0080 <[^>]*> 4682080e 	cmp.sle.s	\$f0,\$f1,\$f2
+0+0084 <[^>]*> 46a2080e 	cmp.sle.d	\$f0,\$f1,\$f2
+0+0088 <[^>]*> 4682080f 	cmp.sule.s	\$f0,\$f1,\$f2
+0+008c <[^>]*> 46a2080f 	cmp.sule.d	\$f0,\$f1,\$f2
+0+0090 <[^>]*> 46820811 	cmp.or.s	\$f0,\$f1,\$f2
+0+0094 <[^>]*> 46a20811 	cmp.or.d	\$f0,\$f1,\$f2
+0+0098 <[^>]*> 46820812 	cmp.une.s	\$f0,\$f1,\$f2
+0+009c <[^>]*> 46a20812 	cmp.une.d	\$f0,\$f1,\$f2
+0+00a0 <[^>]*> 46820813 	cmp.ne.s	\$f0,\$f1,\$f2
+0+00a4 <[^>]*> 46a20813 	cmp.ne.d	\$f0,\$f1,\$f2
+0+00a8 <[^>]*> 46820819 	cmp.sor.s	\$f0,\$f1,\$f2
+0+00ac <[^>]*> 46a20819 	cmp.sor.d	\$f0,\$f1,\$f2
+0+00b0 <[^>]*> 4682081a 	cmp.sune.s	\$f0,\$f1,\$f2
+0+00b4 <[^>]*> 46a2081a 	cmp.sune.d	\$f0,\$f1,\$f2
+0+00b8 <[^>]*> 4682081b 	cmp.sne.s	\$f0,\$f1,\$f2
+0+00bc <[^>]*> 46a2081b 	cmp.sne.d	\$f0,\$f1,\$f2
+0+00c0 <[^>]*> 4520ffff 	bc1eqz	\$f0,000000c0 <[^>]*>
+[	]*c0: R_MIPS_PC16	.L1.1
+0+00c4 <[^>]*> 00000000 	nop
+0+00c8 <[^>]*> 453fffff 	bc1eqz	\$f31,000000c8 <[^>]*>
+[	]*c8: R_MIPS_PC16	.L1.1
+0+00cc <[^>]*> 00000000 	nop
+0+00d0 <[^>]*> 453fffff 	bc1eqz	\$f31,000000d0 <[^>]*>
+[	]*d0: R_MIPS_PC16	new
+0+00d4 <[^>]*> 00000000 	nop
+0+00d8 <[^>]*> 453fffff 	bc1eqz	\$f31,000000d8 <[^>]*>
+[	]*d8: R_MIPS_PC16	external_label
+0+00dc <[^>]*> 00000000 	nop
+0+00e0 <[^>]*> 45a0ffff 	bc1nez	\$f0,000000e0 <[^>]*>
+[	]*e0: R_MIPS_PC16	.L1.1
+0+00e4 <[^>]*> 00000000 	nop
+0+00e8 <[^>]*> 45bfffff 	bc1nez	\$f31,000000e8 <[^>]*>
+[	]*e8: R_MIPS_PC16	.L1.1
+0+00ec <[^>]*> 00000000 	nop
+0+00f0 <[^>]*> 45bfffff 	bc1nez	\$f31,000000f0 <[^>]*>
+[	]*f0: R_MIPS_PC16	new
+0+00f4 <[^>]*> 00000000 	nop
+0+00f8 <[^>]*> 45bfffff 	bc1nez	\$f31,000000f8 <[^>]*>
+[	]*f8: R_MIPS_PC16	external_label
+0+00fc <[^>]*> 00000000 	nop
+0+0100 <[^>]*> 4920ffff 	bc2eqz	\$0,00000100 <[^>]*>
+[	]*100: R_MIPS_PC16	.L1.1
+0+0104 <[^>]*> 00000000 	nop
+0+0108 <[^>]*> 493fffff 	bc2eqz	\$31,00000108 <[^>]*>
+[	]*108: R_MIPS_PC16	.L1.1
+0+010c <[^>]*> 00000000 	nop
+0+0110 <[^>]*> 493fffff 	bc2eqz	\$31,00000110 <[^>]*>
+[	]*110: R_MIPS_PC16	new
+0+0114 <[^>]*> 00000000 	nop
+0+0118 <[^>]*> 493fffff 	bc2eqz	\$31,00000118 <[^>]*>
+[	]*118: R_MIPS_PC16	external_label
+0+011c <[^>]*> 00000000 	nop
+0+0120 <[^>]*> 49a0ffff 	bc2nez	\$0,00000120 <[^>]*>
+[	]*120: R_MIPS_PC16	.L1.1
+0+0124 <[^>]*> 00000000 	nop
+0+0128 <[^>]*> 49bfffff 	bc2nez	\$31,00000128 <[^>]*>
+[	]*128: R_MIPS_PC16	.L1.1
+0+012c <[^>]*> 00000000 	nop
+0+0130 <[^>]*> 49bfffff 	bc2nez	\$31,00000130 <[^>]*>
+[	]*130: R_MIPS_PC16	new
+0+0134 <[^>]*> 00000000 	nop
+0+0138 <[^>]*> 49bfffff 	bc2nez	\$31,00000138 <[^>]*>
+[	]*138: R_MIPS_PC16	external_label
+0+013c <[^>]*> 00000000 	nop
+0+0140 <[^>]*> 46020810 	sel.s	\$f0,\$f1,\$f2
+0+0144 <[^>]*> 46220810 	sel.d	\$f0,\$f1,\$f2
+0+0148 <[^>]*> 46020814 	seleqz.s	\$f0,\$f1,\$f2
+0+014c <[^>]*> 46220814 	seleqz.d	\$f0,\$f1,\$f2
+0+0150 <[^>]*> 46020817 	selnez.s	\$f0,\$f1,\$f2
+0+0154 <[^>]*> 46220817 	selnez.d	\$f0,\$f1,\$f2
+0+0158 <[^>]*> 00641035 	seleqz	v0,v1,a0
+0+015c <[^>]*> 00641037 	selnez	v0,v1,a0
+0+0160 <[^>]*> 00641098 	mul	v0,v1,a0
+0+0164 <[^>]*> 006410d8 	muh	v0,v1,a0
+0+0168 <[^>]*> 00641099 	mulu	v0,v1,a0
+0+016c <[^>]*> 006410d9 	muhu	v0,v1,a0
+0+0170 <[^>]*> 0064109a 	div	v0,v1,a0
+0+0174 <[^>]*> 006410da 	mod	v0,v1,a0
+0+0178 <[^>]*> 0064109b 	divu	v0,v1,a0
+0+017c <[^>]*> 006410db 	modu	v0,v1,a0
+0+0180 <[^>]*> 49422000 	lwc2	\$2,0\(a0\)
+0+0184 <[^>]*> 49422400 	lwc2	\$2,-1024\(a0\)
+0+0188 <[^>]*> 494223ff 	lwc2	\$2,1023\(a0\)
+0+018c <[^>]*> 49622000 	swc2	\$2,0\(a0\)
+0+0190 <[^>]*> 49622400 	swc2	\$2,-1024\(a0\)
+0+0194 <[^>]*> 496223ff 	swc2	\$2,1023\(a0\)
+0+0198 <[^>]*> 49c22000 	ldc2	\$2,0\(a0\)
+0+019c <[^>]*> 49c22400 	ldc2	\$2,-1024\(a0\)
+0+01a0 <[^>]*> 49c223ff 	ldc2	\$2,1023\(a0\)
+0+01a4 <[^>]*> 49e22000 	sdc2	\$2,0\(a0\)
+0+01a8 <[^>]*> 49e22400 	sdc2	\$2,-1024\(a0\)
+0+01ac <[^>]*> 49e223ff 	sdc2	\$2,1023\(a0\)
+0+01b0 <[^>]*> 00641005 	lsa	v0,v1,a0,0x1
+0+01b4 <[^>]*> 006410c5 	lsa	v0,v1,a0,0x4
+0+01b8 <[^>]*> 00601050 	clz	v0,v1
+0+01bc <[^>]*> 00601051 	clo	v0,v1
+0+01c0 <[^>]*> 0000000e 	sdbbp
+0+01c4 <[^>]*> 0000000e 	sdbbp
+0+01c8 <[^>]*> 0000004e 	sdbbp	0x1
+0+01cc <[^>]*> 03ffffce 	sdbbp	0xfffff
+0+01d0 <[^>]*> 3c02ffff 	lui	v0,0xffff
+0+01d4 <[^>]*> 7c008035 	pref	0x0,-256\(zero\)
+0+01d8 <[^>]*> 7fff7fb5 	pref	0x1f,255\(ra\)
+0+01dc <[^>]*> 7c628036 	ll	v0,-256\(v1\)
+0+01e0 <[^>]*> 7c627fb6 	ll	v0,255\(v1\)
+0+01e4 <[^>]*> 7c628026 	sc	v0,-256\(v1\)
+0+01e8 <[^>]*> 7c627fa6 	sc	v0,255\(v1\)
+0+01ec <[^>]*> 7c608025 	cache	0x0,-256\(v1\)
+0+01f0 <[^>]*> 7c7f7fa5 	cache	0x1f,255\(v1\)
+0+01f4 <[^>]*> 7c432220 	align	a0,v0,v1,0
+0+01f8 <[^>]*> 7c432260 	align	a0,v0,v1,1
+0+01fc <[^>]*> 7c4322a0 	align	a0,v0,v1,2
+0+0200 <[^>]*> 7c4322e0 	align	a0,v0,v1,3
+0+0204 <[^>]*> 7c022020 	bitswap	a0,v0
+0+0208 <[^>]*> 2000ffff 	bovc	zero,zero,00000208 <[^>]*>
+[	]*208: R_MIPS_PC16	ext
+0+020c <[^>]*> 00000000 	nop
+0+0210 <[^>]*> 2040ffff 	bovc	v0,zero,00000210 <[^>]*>
+[	]*210: R_MIPS_PC16	ext
+0+0214 <[^>]*> 00000000 	nop
+0+0218 <[^>]*> 2040ffff 	bovc	v0,zero,00000218 <[^>]*>
+[	]*218: R_MIPS_PC16	ext
+0+021c <[^>]*> 00000000 	nop
+0+0220 <[^>]*> 2082ffff 	bovc	a0,v0,00000220 <[^>]*>
+[	]*220: R_MIPS_PC16	ext
+0+0224 <[^>]*> 00000000 	nop
+0+0228 <[^>]*> 2082ffff 	bovc	a0,v0,00000228 <[^>]*>
+[	]*228: R_MIPS_PC16	ext
+0+022c <[^>]*> 00000000 	nop
+0+0230 <[^>]*> 20828000 	bovc	a0,v0,fffe0234 <[^>]*>
+[	]*230: R_MIPS_PC16	L0.
+0+0234 <[^>]*> 00000000 	nop
+0+0238 <[^>]*> 20827fff 	bovc	a0,v0,00020238 <[^>]*>
+[	]*238: R_MIPS_PC16	L0.
+0+023c <[^>]*> 00000000 	nop
+0+0240 <[^>]*> 2082ffff 	bovc	a0,v0,00000240 <[^>]*>
+[	]*240: R_MIPS_PC16	.L1.2
+0+0244 <[^>]*> 00000000 	nop
+0+0248 <[^>]*> 2042ffff 	bovc	v0,v0,00000248 <[^>]*>
+[	]*248: R_MIPS_PC16	ext
+0+024c <[^>]*> 00000000 	nop
+0+0250 <[^>]*> 20428000 	bovc	v0,v0,fffe0254 <[^>]*>
+[	]*250: R_MIPS_PC16	L0.
+0+0254 <[^>]*> 00000000 	nop
+0+0258 <[^>]*> 2002ffff 	beqzalc	v0,00000258 <[^>]*>
+[	]*258: R_MIPS_PC16	ext
+0+025c <[^>]*> 00000000 	nop
+0+0260 <[^>]*> 20028000 	beqzalc	v0,fffe0264 <[^>]*>
+[	]*260: R_MIPS_PC16	L0.
+0+0264 <[^>]*> 00000000 	nop
+0+0268 <[^>]*> 20027fff 	beqzalc	v0,00020268 <[^>]*>
+[	]*268: R_MIPS_PC16	L0.
+0+026c <[^>]*> 00000000 	nop
+0+0270 <[^>]*> 2002ffff 	beqzalc	v0,00000270 <[^>]*>
+[	]*270: R_MIPS_PC16	.L1.2
+0+0274 <[^>]*> 00000000 	nop
+0+0278 <[^>]*> 2043ffff 	beqc	v0,v1,00000278 <[^>]*>
+[	]*278: R_MIPS_PC16	ext
+0+027c <[^>]*> 00000000 	nop
+0+0280 <[^>]*> 2043ffff 	beqc	v0,v1,00000280 <[^>]*>
+[	]*280: R_MIPS_PC16	ext
+0+0284 <[^>]*> 00000000 	nop
+0+0288 <[^>]*> 20438000 	beqc	v0,v1,fffe028c <[^>]*>
+[	]*288: R_MIPS_PC16	L0.
+0+028c <[^>]*> 00000000 	nop
+0+0290 <[^>]*> 20437fff 	beqc	v0,v1,00020290 <[^>]*>
+[	]*290: R_MIPS_PC16	L0.
+0+0294 <[^>]*> 00000000 	nop
+0+0298 <[^>]*> 2043ffff 	beqc	v0,v1,00000298 <[^>]*>
+[	]*298: R_MIPS_PC16	.L1.2
+0+029c <[^>]*> 00000000 	nop
+0+02a0 <[^>]*> 6000ffff 	bnvc	zero,zero,000002a0 <[^>]*>
+[	]*2a0: R_MIPS_PC16	ext
+0+02a4 <[^>]*> 00000000 	nop
+0+02a8 <[^>]*> 6040ffff 	bnvc	v0,zero,000002a8 <[^>]*>
+[	]*2a8: R_MIPS_PC16	ext
+0+02ac <[^>]*> 00000000 	nop
+0+02b0 <[^>]*> 6040ffff 	bnvc	v0,zero,000002b0 <[^>]*>
+[	]*2b0: R_MIPS_PC16	ext
+0+02b4 <[^>]*> 00000000 	nop
+0+02b8 <[^>]*> 6082ffff 	bnvc	a0,v0,000002b8 <[^>]*>
+[	]*2b8: R_MIPS_PC16	ext
+0+02bc <[^>]*> 00000000 	nop
+0+02c0 <[^>]*> 6082ffff 	bnvc	a0,v0,000002c0 <[^>]*>
+[	]*2c0: R_MIPS_PC16	ext
+0+02c4 <[^>]*> 00000000 	nop
+0+02c8 <[^>]*> 60828000 	bnvc	a0,v0,fffe02cc <[^>]*>
+[	]*2c8: R_MIPS_PC16	L0.
+0+02cc <[^>]*> 00000000 	nop
+0+02d0 <[^>]*> 60827fff 	bnvc	a0,v0,000202d0 <[^>]*>
+[	]*2d0: R_MIPS_PC16	L0.
+0+02d4 <[^>]*> 00000000 	nop
+0+02d8 <[^>]*> 6082ffff 	bnvc	a0,v0,000002d8 <[^>]*>
+[	]*2d8: R_MIPS_PC16	.L1.2
+0+02dc <[^>]*> 00000000 	nop
+0+02e0 <[^>]*> 6042ffff 	bnvc	v0,v0,000002e0 <[^>]*>
+[	]*2e0: R_MIPS_PC16	ext
+0+02e4 <[^>]*> 00000000 	nop
+0+02e8 <[^>]*> 60428000 	bnvc	v0,v0,fffe02ec <[^>]*>
+[	]*2e8: R_MIPS_PC16	L0.
+0+02ec <[^>]*> 00000000 	nop
+0+02f0 <[^>]*> 6002ffff 	bnezalc	v0,000002f0 <[^>]*>
+[	]*2f0: R_MIPS_PC16	ext
+0+02f4 <[^>]*> 00000000 	nop
+0+02f8 <[^>]*> 60028000 	bnezalc	v0,fffe02fc <[^>]*>
+[	]*2f8: R_MIPS_PC16	L0.
+0+02fc <[^>]*> 00000000 	nop
+0+0300 <[^>]*> 60027fff 	bnezalc	v0,00020300 <[^>]*>
+[	]*300: R_MIPS_PC16	L0.
+0+0304 <[^>]*> 00000000 	nop
+0+0308 <[^>]*> 6002ffff 	bnezalc	v0,00000308 <[^>]*>
+[	]*308: R_MIPS_PC16	.L1.2
+0+030c <[^>]*> 00000000 	nop
+0+0310 <[^>]*> 6043ffff 	bnec	v0,v1,00000310 <[^>]*>
+[	]*310: R_MIPS_PC16	ext
+0+0314 <[^>]*> 00000000 	nop
+0+0318 <[^>]*> 6043ffff 	bnec	v0,v1,00000318 <[^>]*>
+[	]*318: R_MIPS_PC16	ext
+0+031c <[^>]*> 00000000 	nop
+0+0320 <[^>]*> 60438000 	bnec	v0,v1,fffe0324 <[^>]*>
+[	]*320: R_MIPS_PC16	L0.
+0+0324 <[^>]*> 00000000 	nop
+0+0328 <[^>]*> 60437fff 	bnec	v0,v1,00020328 <[^>]*>
+[	]*328: R_MIPS_PC16	L0.
+0+032c <[^>]*> 00000000 	nop
+0+0330 <[^>]*> 6043ffff 	bnec	v0,v1,00000330 <[^>]*>
+[	]*330: R_MIPS_PC16	.L1.2
+0+0334 <[^>]*> 00000000 	nop
+0+0338 <[^>]*> 5802ffff 	blezc	v0,00000338 <[^>]*>
+[	]*338: R_MIPS_PC16	ext
+0+033c <[^>]*> 00000000 	nop
+0+0340 <[^>]*> 58028000 	blezc	v0,fffe0344 <[^>]*>
+[	]*340: R_MIPS_PC16	L0.
+0+0344 <[^>]*> 00000000 	nop
+0+0348 <[^>]*> 58027fff 	blezc	v0,00020348 <[^>]*>
+[	]*348: R_MIPS_PC16	L0.
+0+034c <[^>]*> 00000000 	nop
+0+0350 <[^>]*> 5802ffff 	blezc	v0,00000350 <[^>]*>
+[	]*350: R_MIPS_PC16	.L1.2
+0+0354 <[^>]*> 00000000 	nop
+0+0358 <[^>]*> 5842ffff 	bgezc	v0,00000358 <[^>]*>
+[	]*358: R_MIPS_PC16	ext
+0+035c <[^>]*> 00000000 	nop
+0+0360 <[^>]*> 58428000 	bgezc	v0,fffe0364 <[^>]*>
+[	]*360: R_MIPS_PC16	L0.
+0+0364 <[^>]*> 00000000 	nop
+0+0368 <[^>]*> 58427fff 	bgezc	v0,00020368 <[^>]*>
+[	]*368: R_MIPS_PC16	L0.
+0+036c <[^>]*> 00000000 	nop
+0+0370 <[^>]*> 5842ffff 	bgezc	v0,00000370 <[^>]*>
+[	]*370: R_MIPS_PC16	.L1.2
+0+0374 <[^>]*> 00000000 	nop
+0+0378 <[^>]*> 5843ffff 	bgec	v0,v1,00000378 <[^>]*>
+[	]*378: R_MIPS_PC16	ext
+0+037c <[^>]*> 00000000 	nop
+0+0380 <[^>]*> 58438000 	bgec	v0,v1,fffe0384 <[^>]*>
+[	]*380: R_MIPS_PC16	L0.
+0+0384 <[^>]*> 00000000 	nop
+0+0388 <[^>]*> 58437fff 	bgec	v0,v1,00020388 <[^>]*>
+[	]*388: R_MIPS_PC16	L0.
+0+038c <[^>]*> 00000000 	nop
+0+0390 <[^>]*> 5843ffff 	bgec	v0,v1,00000390 <[^>]*>
+[	]*390: R_MIPS_PC16	.L1.2
+0+0394 <[^>]*> 00000000 	nop
+0+0398 <[^>]*> 5862ffff 	bgec	v1,v0,00000398 <[^>]*>
+[	]*398: R_MIPS_PC16	.L1.2
+0+039c <[^>]*> 00000000 	nop
+0+03a0 <[^>]*> 5c02ffff 	bgtzc	v0,000003a0 <[^>]*>
+[	]*3a0: R_MIPS_PC16	ext
+0+03a4 <[^>]*> 00000000 	nop
+0+03a8 <[^>]*> 5c028000 	bgtzc	v0,fffe03ac <[^>]*>
+[	]*3a8: R_MIPS_PC16	L0.
+0+03ac <[^>]*> 00000000 	nop
+0+03b0 <[^>]*> 5c027fff 	bgtzc	v0,000203b0 <[^>]*>
+[	]*3b0: R_MIPS_PC16	L0.
+0+03b4 <[^>]*> 00000000 	nop
+0+03b8 <[^>]*> 5c02ffff 	bgtzc	v0,000003b8 <[^>]*>
+[	]*3b8: R_MIPS_PC16	.L1.2
+0+03bc <[^>]*> 00000000 	nop
+0+03c0 <[^>]*> 5c42ffff 	bltzc	v0,000003c0 <[^>]*>
+[	]*3c0: R_MIPS_PC16	ext
+0+03c4 <[^>]*> 00000000 	nop
+0+03c8 <[^>]*> 5c428000 	bltzc	v0,fffe03cc <[^>]*>
+[	]*3c8: R_MIPS_PC16	L0.
+0+03cc <[^>]*> 00000000 	nop
+0+03d0 <[^>]*> 5c427fff 	bltzc	v0,000203d0 <[^>]*>
+[	]*3d0: R_MIPS_PC16	L0.
+0+03d4 <[^>]*> 00000000 	nop
+0+03d8 <[^>]*> 5c42ffff 	bltzc	v0,000003d8 <[^>]*>
+[	]*3d8: R_MIPS_PC16	.L1.2
+0+03dc <[^>]*> 00000000 	nop
+0+03e0 <[^>]*> 5c43ffff 	bltc	v0,v1,000003e0 <[^>]*>
+[	]*3e0: R_MIPS_PC16	ext
+0+03e4 <[^>]*> 00000000 	nop
+0+03e8 <[^>]*> 5c438000 	bltc	v0,v1,fffe03ec <[^>]*>
+[	]*3e8: R_MIPS_PC16	L0.
+0+03ec <[^>]*> 00000000 	nop
+0+03f0 <[^>]*> 5c437fff 	bltc	v0,v1,000203f0 <[^>]*>
+[	]*3f0: R_MIPS_PC16	L0.
+0+03f4 <[^>]*> 00000000 	nop
+0+03f8 <[^>]*> 5c43ffff 	bltc	v0,v1,000003f8 <[^>]*>
+[	]*3f8: R_MIPS_PC16	.L1.2
+0+03fc <[^>]*> 00000000 	nop
+0+0400 <[^>]*> 5c62ffff 	bltc	v1,v0,00000400 <[^>]*>
+[	]*400: R_MIPS_PC16	.L1.2
+0+0404 <[^>]*> 00000000 	nop
+0+0408 <[^>]*> 1802ffff 	blezalc	v0,00000408 <[^>]*>
+[	]*408: R_MIPS_PC16	ext
+0+040c <[^>]*> 00000000 	nop
+0+0410 <[^>]*> 18028000 	blezalc	v0,fffe0414 <[^>]*>
+[	]*410: R_MIPS_PC16	L0.
+0+0414 <[^>]*> 00000000 	nop
+0+0418 <[^>]*> 18027fff 	blezalc	v0,00020418 <[^>]*>
+[	]*418: R_MIPS_PC16	L0.
+0+041c <[^>]*> 00000000 	nop
+0+0420 <[^>]*> 1802ffff 	blezalc	v0,00000420 <[^>]*>
+[	]*420: R_MIPS_PC16	.L1.2
+0+0424 <[^>]*> 00000000 	nop
+0+0428 <[^>]*> 1842ffff 	bgezalc	v0,00000428 <[^>]*>
+[	]*428: R_MIPS_PC16	ext
+0+042c <[^>]*> 00000000 	nop
+0+0430 <[^>]*> 18428000 	bgezalc	v0,fffe0434 <[^>]*>
+[	]*430: R_MIPS_PC16	L0.
+0+0434 <[^>]*> 00000000 	nop
+0+0438 <[^>]*> 18427fff 	bgezalc	v0,00020438 <[^>]*>
+[	]*438: R_MIPS_PC16	L0.
+0+043c <[^>]*> 00000000 	nop
+0+0440 <[^>]*> 1842ffff 	bgezalc	v0,00000440 <[^>]*>
+[	]*440: R_MIPS_PC16	.L1.2
+0+0444 <[^>]*> 00000000 	nop
+0+0448 <[^>]*> 1843ffff 	bgeuc	v0,v1,00000448 <[^>]*>
+[	]*448: R_MIPS_PC16	ext
+0+044c <[^>]*> 00000000 	nop
+0+0450 <[^>]*> 18438000 	bgeuc	v0,v1,fffe0454 <[^>]*>
+[	]*450: R_MIPS_PC16	L0.
+0+0454 <[^>]*> 00000000 	nop
+0+0458 <[^>]*> 18437fff 	bgeuc	v0,v1,00020458 <[^>]*>
+[	]*458: R_MIPS_PC16	L0.
+0+045c <[^>]*> 00000000 	nop
+0+0460 <[^>]*> 1843ffff 	bgeuc	v0,v1,00000460 <[^>]*>
+[	]*460: R_MIPS_PC16	.L1.2
+0+0464 <[^>]*> 00000000 	nop
+0+0468 <[^>]*> 1862ffff 	bgeuc	v1,v0,00000468 <[^>]*>
+[	]*468: R_MIPS_PC16	.L1.2
+0+046c <[^>]*> 00000000 	nop
+0+0470 <[^>]*> 1c02ffff 	bgtzalc	v0,00000470 <[^>]*>
+[	]*470: R_MIPS_PC16	ext
+0+0474 <[^>]*> 00000000 	nop
+0+0478 <[^>]*> 1c028000 	bgtzalc	v0,fffe047c <[^>]*>
+[	]*478: R_MIPS_PC16	L0.
+0+047c <[^>]*> 00000000 	nop
+0+0480 <[^>]*> 1c027fff 	bgtzalc	v0,00020480 <[^>]*>
+[	]*480: R_MIPS_PC16	L0.
+0+0484 <[^>]*> 00000000 	nop
+0+0488 <[^>]*> 1c02ffff 	bgtzalc	v0,00000488 <[^>]*>
+[	]*488: R_MIPS_PC16	.L1.2
+0+048c <[^>]*> 00000000 	nop
+0+0490 <[^>]*> 1c42ffff 	bltzalc	v0,00000490 <[^>]*>
+[	]*490: R_MIPS_PC16	ext
+0+0494 <[^>]*> 00000000 	nop
+0+0498 <[^>]*> 1c428000 	bltzalc	v0,fffe049c <[^>]*>
+[	]*498: R_MIPS_PC16	L0.
+0+049c <[^>]*> 00000000 	nop
+0+04a0 <[^>]*> 1c427fff 	bltzalc	v0,000204a0 <[^>]*>
+[	]*4a0: R_MIPS_PC16	L0.
+0+04a4 <[^>]*> 00000000 	nop
+0+04a8 <[^>]*> 1c42ffff 	bltzalc	v0,000004a8 <[^>]*>
+[	]*4a8: R_MIPS_PC16	.L1.2
+0+04ac <[^>]*> 00000000 	nop
+0+04b0 <[^>]*> 1c43ffff 	bltuc	v0,v1,000004b0 <[^>]*>
+[	]*4b0: R_MIPS_PC16	ext
+0+04b4 <[^>]*> 00000000 	nop
+0+04b8 <[^>]*> 1c438000 	bltuc	v0,v1,fffe04bc <[^>]*>
+[	]*4b8: R_MIPS_PC16	L0.
+0+04bc <[^>]*> 00000000 	nop
+0+04c0 <[^>]*> 1c437fff 	bltuc	v0,v1,000204c0 <[^>]*>
+[	]*4c0: R_MIPS_PC16	L0.
+0+04c4 <[^>]*> 00000000 	nop
+0+04c8 <[^>]*> 1c43ffff 	bltuc	v0,v1,000004c8 <[^>]*>
+[	]*4c8: R_MIPS_PC16	.L1.2
+0+04cc <[^>]*> 00000000 	nop
+0+04d0 <[^>]*> 1c62ffff 	bltuc	v1,v0,000004d0 <[^>]*>
+[	]*4d0: R_MIPS_PC16	.L1.2
+0+04d4 <[^>]*> 00000000 	nop
+0+04d8 <[^>]*> cbffffff 	bc	000004d8 <[^>]*>
+[	]*4d8: R_MIPS_PC26_S2	ext
+0+04dc <[^>]*> ca000000 	bc	f80004e0 <[^>]*>
+[	]*4dc: R_MIPS_PC26_S2	L0.
+0+04e0 <[^>]*> c9ffffff 	bc	080004e0 <[^>]*>
+[	]*4e0: R_MIPS_PC26_S2	L0.
+0+04e4 <[^>]*> cbffffff 	bc	000004e4 <[^>]*>
+[	]*4e4: R_MIPS_PC26_S2	.L1.2
+0+04e8 <[^>]*> ebffffff 	balc	000004e8 <[^>]*>
+[	]*4e8: R_MIPS_PC26_S2	ext
+0+04ec <[^>]*> ea000000 	balc	f80004f0 <[^>]*>
+[	]*4ec: R_MIPS_PC26_S2	L0.
+0+04f0 <[^>]*> e9ffffff 	balc	080004f0 <[^>]*>
+[	]*4f0: R_MIPS_PC26_S2	L0.
+0+04f4 <[^>]*> ebffffff 	balc	000004f4 <[^>]*>
+[	]*4f4: R_MIPS_PC26_S2	.L1.2
+0+04f8 <[^>]*> d85fffff 	beqzc	v0,000004f8 <[^>]*>
+[	]*4f8: R_MIPS_PC21_S2	ext
+0+04fc <[^>]*> 00000000 	nop
+0+0500 <[^>]*> d8500000 	beqzc	v0,ffc00504 <[^>]*>
+[	]*500: R_MIPS_PC21_S2	L0.
+0+0504 <[^>]*> 00000000 	nop
+0+0508 <[^>]*> d84fffff 	beqzc	v0,00400508 <[^>]*>
+[	]*508: R_MIPS_PC21_S2	L0.
+0+050c <[^>]*> 00000000 	nop
+0+0510 <[^>]*> d85fffff 	beqzc	v0,00000510 <[^>]*>
+[	]*510: R_MIPS_PC21_S2	.L1.2
+0+0514 <[^>]*> 00000000 	nop
+0+0518 <[^>]*> d8038000 	jic	v1,-32768
+0+051c <[^>]*> d8037fff 	jic	v1,32767
+0+0520 <[^>]*> d81f0000 	jrc	ra
+0+0524 <[^>]*> f85fffff 	bnezc	v0,00000524 <[^>]*>
+[	]*524: R_MIPS_PC21_S2	ext
+0+0528 <[^>]*> 00000000 	nop
+0+052c <[^>]*> f8500000 	bnezc	v0,ffc00530 <[^>]*>
+[	]*52c: R_MIPS_PC21_S2	L0.
+0+0530 <[^>]*> 00000000 	nop
+0+0534 <[^>]*> f84fffff 	bnezc	v0,00400534 <[^>]*>
+[	]*534: R_MIPS_PC21_S2	L0.
+0+0538 <[^>]*> 00000000 	nop
+0+053c <[^>]*> f85fffff 	bnezc	v0,0000053c <[^>]*>
+[	]*53c: R_MIPS_PC21_S2	.L1.2
+0+0540 <[^>]*> 00000000 	nop
+0+0544 <[^>]*> f8038000 	jialc	v1,-32768
+0+0548 <[^>]*> f8037fff 	jialc	v1,32767
+0+054c <[^>]*> 3c43ffff 	aui	v1,v0,0xffff
+0+0550 <[^>]*> ec600000 	lapc	v1,00000550 <[^>]*>
+[	]*550: R_MIPS_PC19_S2	.L1.2
+0+0554 <[^>]*> ec840000 	lapc	a0,fff00554 <[^>]*>
+[	]*554: R_MIPS_PC19_S2	L0.
+0+0558 <[^>]*> ec83ffff 	lapc	a0,00100554 <[^>]*>
+[	]*558: R_MIPS_PC19_S2	L0.
+0+055c <[^>]*> ec840000 	lapc	a0,fff0055c <[^>]*>
+0+0560 <[^>]*> ec83ffff 	lapc	a0,0010055c <[^>]*>
+0+0564 <[^>]*> ec7effff 	auipc	v1,0xffff
+0+0568 <[^>]*> ec7fffff 	aluipc	v1,0xffff
+0+056c <[^>]*> ec880000 	lwpc	a0,0000056c <[^>]*>
+[	]*56c: R_MIPS_PC19_S2	.L1.2
+0+0570 <[^>]*> ec8c0000 	lwpc	a0,fff00570 <[^>]*>
+[	]*570: R_MIPS_PC19_S2	L0.
+0+0574 <[^>]*> ec8bffff 	lwpc	a0,00100570 <[^>]*>
+[	]*574: R_MIPS_PC19_S2	L0.
+0+0578 <[^>]*> ec8c0000 	lwpc	a0,fff00578 <[^>]*>
+0+057c <[^>]*> ec8bffff 	lwpc	a0,00100578 <[^>]*>
+0+0580 <[^>]*> 00000000 	nop
+0+0584 <[^>]*> ec83ffff 	lapc	a0,00100580 <[^>]*>
+	\.\.\.
diff --git a/gas/testsuite/gas/mips/r6.s b/gas/testsuite/gas/mips/r6.s
new file mode 100644
index 00000000000..73308ade68e
--- /dev/null
+++ b/gas/testsuite/gas/mips/r6.s
@@ -0,0 +1,263 @@
+	.text
+	.set	reorder
+new:	maddf.s	$f0,$f1,$f2
+	maddf.d	$f3,$f4,$f5
+	msubf.s	$f6,$f7,$f8
+	msubf.d	$f9,$f10,$f11
+	cmp.af.s	$f0,$f1,$f2
+	cmp.af.d	$f0,$f1,$f2
+	cmp.un.s	$f0,$f1,$f2
+	cmp.un.d	$f0,$f1,$f2
+	cmp.eq.s	$f0,$f1,$f2
+	cmp.eq.d	$f0,$f1,$f2
+	cmp.ueq.s	$f0,$f1,$f2
+	cmp.ueq.d	$f0,$f1,$f2
+	cmp.lt.s	$f0,$f1,$f2
+	cmp.lt.d	$f0,$f1,$f2
+	cmp.ult.s	$f0,$f1,$f2
+	cmp.ult.d	$f0,$f1,$f2
+	cmp.le.s	$f0,$f1,$f2
+	cmp.le.d	$f0,$f1,$f2
+	cmp.ule.s	$f0,$f1,$f2
+	cmp.ule.d	$f0,$f1,$f2
+	cmp.saf.s	$f0,$f1,$f2
+	cmp.saf.d	$f0,$f1,$f2
+	cmp.sun.s	$f0,$f1,$f2
+	cmp.sun.d	$f0,$f1,$f2
+	cmp.seq.s	$f0,$f1,$f2
+	cmp.seq.d	$f0,$f1,$f2
+	cmp.sueq.s	$f0,$f1,$f2
+	cmp.sueq.d	$f0,$f1,$f2
+	cmp.slt.s	$f0,$f1,$f2
+	cmp.slt.d	$f0,$f1,$f2
+	cmp.sult.s	$f0,$f1,$f2
+	cmp.sult.d	$f0,$f1,$f2
+	cmp.sle.s	$f0,$f1,$f2
+	cmp.sle.d	$f0,$f1,$f2
+	cmp.sule.s	$f0,$f1,$f2
+	cmp.sule.d	$f0,$f1,$f2
+	cmp.or.s	$f0,$f1,$f2
+	cmp.or.d	$f0,$f1,$f2
+	cmp.une.s	$f0,$f1,$f2
+	cmp.une.d	$f0,$f1,$f2
+	cmp.ne.s	$f0,$f1,$f2
+	cmp.ne.d	$f0,$f1,$f2
+	cmp.sor.s	$f0,$f1,$f2
+	cmp.sor.d	$f0,$f1,$f2
+	cmp.sune.s	$f0,$f1,$f2
+	cmp.sune.d	$f0,$f1,$f2
+	cmp.sne.s	$f0,$f1,$f2
+	cmp.sne.d	$f0,$f1,$f2
+	bc1eqz	$f0,1f
+	bc1eqz	$f31,1f
+	bc1eqz	$f31,new
+	bc1eqz	$f31,external_label
+	bc1nez	$f0,1f
+	bc1nez	$f31,1f
+	bc1nez	$f31,new
+	bc1nez	$f31,external_label
+	bc2eqz	$0,1f
+	bc2eqz	$31,1f
+	bc2eqz	$31,new
+	bc2eqz	$31,external_label
+	bc2nez	$0,1f
+	bc2nez	$31,1f
+	bc2nez	$31,new
+	bc2nez	$31,external_label
+1:	sel.s	$f0,$f1,$f2
+	sel.d	$f0,$f1,$f2
+	seleqz.s	$f0,$f1,$f2
+	seleqz.d	$f0,$f1,$f2
+	selnez.s	$f0,$f1,$f2
+	selnez.d	$f0,$f1,$f2
+	seleqz	$2,$3,$4
+	selnez	$2,$3,$4
+	mul	$2,$3,$4
+	muh	$2,$3,$4
+	mulu	$2,$3,$4
+	muhu	$2,$3,$4
+	div	$2,$3,$4
+	mod	$2,$3,$4
+	divu	$2,$3,$4
+	modu	$2,$3,$4
+	lwc2	$2,0($4)
+	lwc2	$2,-1024($4)
+	lwc2	$2,1023($4)
+	swc2	$2,0($4)
+	swc2	$2,-1024($4)
+	swc2	$2,1023($4)
+	ldc2	$2,0($4)
+	ldc2	$2,-1024($4)
+	ldc2	$2,1023($4)
+	sdc2	$2,0($4)
+	sdc2	$2,-1024($4)
+	sdc2	$2,1023($4)
+	lsa	$2,$3,$4,1
+	lsa	$2,$3,$4,4
+	clz	$2,$3
+	clo	$2,$3
+	sdbbp
+	sdbbp	0
+	sdbbp	1
+	sdbbp	1048575
+	lui	$2,0xffff
+	pref	0, -256($0)
+	pref	31, 255($31)
+	ll	$2,-256($3)
+	ll	$2,255($3)
+	sc	$2,-256($3)
+	sc	$2,255($3)
+	cache	0,-256($3)
+	cache	31,255($3)
+
+
+        align   $4, $2, $3, 0
+        align   $4, $2, $3, 1
+        align   $4, $2, $3, 2
+        align   $4, $2, $3, 3
+
+
+        bitswap  $4, $2
+
+        bovc     $0, $0, ext
+        bovc     $2, $0, ext
+        bovc     $0, $2, ext
+        bovc     $2, $4, ext
+        bovc     $4, $2, ext
+        bovc     $2, $4, . + 4 + (-32768 << 2)
+        bovc     $2, $4, . + 4 + (32767 << 2)
+        bovc     $2, $4, 1f
+        bovc     $2, $2, ext
+        bovc     $2, $2, . + 4 + (-32768 << 2)
+        beqzalc $2, ext
+        beqzalc $2, . + 4 + (-32768 << 2)
+        beqzalc $2, . + 4 + (32767 << 2)
+        beqzalc $2, 1f
+        beqc    $3, $2, ext
+        beqc    $2, $3, ext
+        beqc    $3, $2, . + 4 + (-32768 << 2)
+        beqc    $3, $2, . + 4 + (32767 << 2)
+        beqc    $3, $2, 1f
+
+        bnvc     $0, $0, ext
+        bnvc     $2, $0, ext
+        bnvc     $0, $2, ext
+        bnvc     $2, $4, ext
+        bnvc     $4, $2, ext
+        bnvc     $2, $4, . + 4 + (-32768 << 2)
+        bnvc     $2, $4, . + 4 + (32767 << 2)
+        bnvc     $2, $4, 1f
+        bnvc     $2, $2, ext
+        bnvc     $2, $2, . + 4 + (-32768 << 2)
+        bnezalc $2, ext
+        bnezalc $2, . + 4 + (-32768 << 2)
+        bnezalc $2, . + 4 + (32767 << 2)
+        bnezalc $2, 1f
+        bnec    $3, $2, ext
+        bnec    $2, $3, ext
+        bnec    $3, $2, . + 4 + (-32768 << 2)
+        bnec    $3, $2, . + 4 + (32767 << 2)
+        bnec    $3, $2, 1f
+
+        blezc   $2, ext
+        blezc   $2, . + 4 + (-32768 << 2)
+        blezc   $2, . + 4 + (32767 << 2)
+        blezc   $2, 1f
+        bgezc   $2, ext
+        bgezc   $2, . + 4 + (-32768 << 2)
+        bgezc   $2, . + 4 + (32767 << 2)
+        bgezc   $2, 1f
+        bgec    $2, $3, ext
+        bgec    $2, $3, . + 4 + (-32768 << 2)
+        bgec    $2, $3, . + 4 + (32767 << 2)
+        bgec    $2, $3, 1f
+        bgec    $3, $2, 1f
+
+        bgtzc   $2, ext
+        bgtzc   $2, . + 4 + (-32768 << 2)
+        bgtzc   $2, . + 4 + (32767 << 2)
+        bgtzc   $2, 1f
+        bltzc   $2, ext
+        bltzc   $2, . + 4 + (-32768 << 2)
+        bltzc   $2, . + 4 + (32767 << 2)
+        bltzc   $2, 1f
+        bltc    $2, $3, ext
+        bltc    $2, $3, . + 4 + (-32768 << 2)
+        bltc    $2, $3, . + 4 + (32767 << 2)
+        bltc    $2, $3, 1f
+        bltc    $3, $2, 1f
+
+        blezalc $2, ext
+        blezalc $2, . + 4 + (-32768 << 2)
+        blezalc $2, . + 4 + (32767 << 2)
+        blezalc $2, 1f
+        bgezalc $2, ext
+        bgezalc $2, . + 4 + (-32768 << 2)
+        bgezalc $2, . + 4 + (32767 << 2)
+        bgezalc $2, 1f
+        bgeuc    $2, $3, ext
+        bgeuc    $2, $3, . + 4 + (-32768 << 2)
+        bgeuc    $2, $3, . + 4 + (32767 << 2)
+        bgeuc    $2, $3, 1f
+        bgeuc    $3, $2, 1f
+
+        bgtzalc $2, ext
+        bgtzalc $2, . + 4 + (-32768 << 2)
+        bgtzalc $2, . + 4 + (32767 << 2)
+        bgtzalc $2, 1f
+        bltzalc $2, ext
+        bltzalc $2, . + 4 + (-32768 << 2)
+        bltzalc $2, . + 4 + (32767 << 2)
+        bltzalc $2, 1f
+        bltuc   $2, $3, ext
+        bltuc   $2, $3, . + 4 + (-32768 << 2)
+        bltuc   $2, $3, . + 4 + (32767 << 2)
+        bltuc   $2, $3, 1f
+        bltuc   $3, $2, 1f
+
+        bc      ext
+        bc      . + 4 + (-33554432 << 2)
+        bc      . + 4 + (33554431 << 2)
+        bc      1f
+        balc    ext
+        balc    . + 4 + (-33554432 << 2)
+        balc    . + 4 + (33554431 << 2)
+        balc    1f
+
+        beqzc   $2, ext
+        beqzc   $2, . + 4 + (-1048576 << 2)
+        beqzc   $2, . + 4 + (1048575 << 2)
+        beqzc   $2, 1f
+	jic	$3,-32768
+	jic	$3,32767
+	jrc	$31
+
+        bnezc   $2, ext
+        bnezc   $2, . + 4 + (-1048576 << 2)
+        bnezc   $2, . + 4 + (1048575 << 2)
+        bnezc   $2, 1f
+	jialc	$3,-32768
+	jialc	$3,32767
+
+
+        aui      $3, $2, 0xffff
+
+        lapc        $3, 1f
+        lapc   $4, .+(-262144 << 2)
+        lapc   $4, .+(262143 << 2)
+        addiupc   $4, (-262144 << 2)
+        addiupc   $4, (262143 << 2)
+        auipc      $3, 0xffff
+        aluipc     $3, 0xffff
+        lwpc      $4, 1f
+        lwpc      $4, .+(-262144 << 2)
+        lwpc      $4, .+(262143 << 2)
+        lw      $4, (-262144 << 2)($pc)
+        lw      $4, (262143 << 2)($pc)
+1:
+        nop
+	addiu	$4, $pc, (262143 << 2)
+
+# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
+	.align  2
+	.space  8
diff --git a/include/elf/ChangeLog b/include/elf/ChangeLog
index b76588f7c9a..ab0a5425483 100644
--- a/include/elf/ChangeLog
+++ b/include/elf/ChangeLog
@@ -1,3 +1,11 @@
+2014-09-15  Andrew Bennett  <andrew.bennett@imgtec.com>
+	    Matthew Fortune  <matthew.fortune@imgtec.com>
+
+	* mips.h: Add relocs: R_MIPS_PC21_S2, R_MIPS_PC26_S2, R_MIPS_PC18_S3,
+	R_MIPS_PC19_S2, R_MIPS_PCHI16 and R_MIPS_PCLO16.
+	(E_MIPS_ARCH_32R6): New define.
+	(E_MIPS_ARCH_64R6): New define.
+
 2014-08-26  DJ Delorie  <dj@redhat.com>
 
 	* rl78.h (RL78_RELAXA_MASK): New.  Relax types are enums, not bits
diff --git a/include/elf/mips.h b/include/elf/mips.h
index 24c238011be..1fa69c15c31 100644
--- a/include/elf/mips.h
+++ b/include/elf/mips.h
@@ -87,7 +87,14 @@ START_RELOC_NUMBERS (elf_mips_reloc_type)
   RELOC_NUMBER (R_MIPS_TLS_TPREL_HI16, 49)
   RELOC_NUMBER (R_MIPS_TLS_TPREL_LO16, 50)
   RELOC_NUMBER (R_MIPS_GLOB_DAT, 51)
-  FAKE_RELOC (R_MIPS_max, 52)
+  /* Space to grow */
+  RELOC_NUMBER (R_MIPS_PC21_S2, 60)
+  RELOC_NUMBER (R_MIPS_PC26_S2, 61)
+  RELOC_NUMBER (R_MIPS_PC18_S3, 62)
+  RELOC_NUMBER (R_MIPS_PC19_S2, 63)
+  RELOC_NUMBER (R_MIPS_PCHI16, 64)
+  RELOC_NUMBER (R_MIPS_PCLO16, 65)
+  FAKE_RELOC (R_MIPS_max, 66)
   /* These relocs are used for the mips16.  */
   FAKE_RELOC (R_MIPS16_min, 100)
   RELOC_NUMBER (R_MIPS16_26, 100)
@@ -237,6 +244,12 @@ END_RELOC_NUMBERS (R_MIPS_maxext)
 /* -mips64r2 code.  */
 #define E_MIPS_ARCH_64R2        0x80000000
 
+/* -mips32r6 code.  */
+#define E_MIPS_ARCH_32R6        0x90000000
+
+/* -mips64r6 code.  */
+#define E_MIPS_ARCH_64R6        0xa0000000
+
 /* The ABI of the file.  Also see EF_MIPS_ABI2 above. */
 #define EF_MIPS_ABI		0x0000F000
 
diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog
index 58d9f99955d..c7425bbcaca 100644
--- a/include/opcode/ChangeLog
+++ b/include/opcode/ChangeLog
@@ -1,3 +1,23 @@
+2014-09-15  Andrew Bennett  <andrew.bennett@imgtec.com>
+	    Matthew Fortune  <matthew.fortune@imgtec.com>
+
+	* mips.h (mips_operand_type): Add new entries: OP_SAME_RS_RT,
+	OP_CHECK_PREV and OP_NON_ZERO_REG.  Add descriptions for the MIPS R6
+	instruction arguments: -a, -b, -d, -s, -t, -u, -v, -w, -x, -y, -A, -B,
+	 +I, +O, +R, +:, +\, +", +;
+	(mips_check_prev_operand): New struct.
+	(INSN2_FORBIDDEN_SLOT): New define.
+	(INSN_ISA32R6): New define.
+	(INSN_ISA64R6): New define.
+	(INSN_UPTO32R6): New define.
+	(INSN_UPTO64R6): New define.
+	(mips_isa_table): Add INSN_UPTO32R6 and INSN_UPTO64R6.
+	(ISA_MIPS32R6): New define.
+	(ISA_MIPS64R6): New define.
+	(CPU_MIPS32R6): New define.
+	(CPU_MIPS64R6): New define.
+	(cpu_is_member): Add cases for CPU_MIPS32R6, and CPU_MIPS64R6.
+
 2014-09-03  Jiong Wang  <jiong.wang@arm.com>
 
 	* aarch64.h (AARCH64_FEATURE_LSE): New feature added.
diff --git a/include/opcode/mips.h b/include/opcode/mips.h
index aa1528ffae9..ef2616743f2 100644
--- a/include/opcode/mips.h
+++ b/include/opcode/mips.h
@@ -417,7 +417,17 @@ enum mips_operand_type {
   OP_IMM_INDEX,
 
   /* An index selected by a register, e.g. [$2].  */
-  OP_REG_INDEX
+  OP_REG_INDEX,
+
+  /* The operand spans two 5-bit register fields, both of which must be set to
+     the source register.  */
+  OP_SAME_RS_RT,
+
+  /* Described by mips_prev_operand.  */
+  OP_CHECK_PREV,
+
+  /* A register operand that must not be zero.  */
+  OP_NON_ZERO_REG
 };
 
 /* Enumerates the types of MIPS register.  */
@@ -553,6 +563,18 @@ struct mips_reg_operand
   const unsigned char *reg_map;
 };
 
+/* Describes an operand that which must match a condition based on the
+   previous operand.  */
+struct mips_check_prev_operand
+{
+  struct mips_operand root;
+
+  bfd_boolean greater_than_ok;
+  bfd_boolean less_than_ok;
+  bfd_boolean equal_ok;
+  bfd_boolean zero_ok;
+};
+
 /* Describes an operand that encodes a pair of registers.  */
 struct mips_reg_pair_operand
 {
@@ -927,6 +949,28 @@ struct mips_opcode
    "+*" 5-bit register vector element index at bit 16
    "+|" 8-bit mask at bit 16
 
+   MIPS R6:
+   "+:" 11-bit mask at bit 0
+   "+'" 26 bit PC relative branch target address
+   "+"" 21 bit PC relative branch target address
+   "+;" 5 bit same register in both OP_*_RS and OP_*_RT
+   "+I" 2bit unsigned bit position at bit 6
+   "+O" 3bit unsigned bit position at bit 6
+   "+R" must be program counter
+   "-a" (-262144 .. 262143) << 2 at bit 0
+   "-b" (-131072 .. 131071) << 3 at bit 0
+   "-d" Same as destination register GP
+   "-s" 5 bit source register specifier (OP_*_RS) not $0
+   "-t" 5 bit source register specifier (OP_*_RT) not $0
+   "-u" 5 bit source register specifier (OP_*_RT) greater than OP_*_RS
+   "-v" 5 bit source register specifier (OP_*_RT) not $0 not OP_*_RS
+   "-w" 5 bit source register specifier (OP_*_RT) less than or equal to OP_*_RS
+   "-x" 5 bit source register specifier (OP_*_RT) greater than or
+        equal to OP_*_RS
+   "-y" 5 bit source register specifier (OP_*_RT) not $0 less than OP_*_RS
+   "-A" symbolic offset (-262144 .. 262143) << 2 at bit 0
+   "-B" symbolic offset (-131072 .. 131071) << 3 at bit 0
+
    Other:
    "()" parens surrounding optional value
    ","  separates operands
@@ -934,16 +978,21 @@ struct mips_opcode
 
    Characters used so far, for quick reference when adding more:
    "1234567890"
-   "%[]<>(),+:'@!#$*&\~"
+   "%[]<>(),+-:'@!#$*&\~"
    "ABCDEFGHIJKLMNOPQRSTUVWXYZ"
    "abcdefghijklopqrstuvwxz"
 
    Extension character sequences used so far ("+" followed by the
    following), for quick reference when adding more:
    "1234567890"
-   "~!@#$%^&*|"
-   "ABCEFGHJKLMNPQSTUVWXZ"
+   "~!@#$%^&*|:'";"
+   "ABCEFGHIJKLMNOPQRSTUVWXZ"
    "abcdefghijklmnopqrstuvwxyz"
+
+   Extension character sequences used so far ("-" followed by the
+   following), for quick reference when adding more:
+   "AB"
+   "abdstuvwxy"
 */
 
 /* These are the bits which may be set in the pinfo field of an
@@ -1051,6 +1100,8 @@ struct mips_opcode
 #define INSN2_READ_GPR_16           0x00002000
 /* Has an "\.x?y?z?w?" suffix based on mips_vu0_channel_mask.  */
 #define INSN2_VU0_CHANNEL_SUFFIX    0x00004000
+/* Instruction has a forbidden slot.  */
+#define INSN2_FORBIDDEN_SLOT        0x00008000
 
 /* Masks used to mark instructions to indicate which MIPS ISA level
    they were introduced in.  INSN_ISA_MASK masks an enumeration that
@@ -1070,10 +1121,12 @@ struct mips_opcode
 #define INSN_ISA32R2              7
 #define INSN_ISA32R3              8
 #define INSN_ISA32R5              9
+#define INSN_ISA32R6              10
 #define INSN_ISA64                11 
 #define INSN_ISA64R2              12
 #define INSN_ISA64R3              13
 #define INSN_ISA64R5              14
+#define INSN_ISA64R6              15
 /* Below this point the INSN_* values correspond to combinations of ISAs.
    They are only for use in the opcodes table to indicate membership of
    a combination of ISAs that cannot be expressed using the usual inclusion
@@ -1084,7 +1137,19 @@ struct mips_opcode
 #define INSN_ISA4_32R2            19
 #define INSN_ISA5_32R2            20
 
+/* The R6 definitions shown below state that they support all previous ISAs.
+   This is not actually true as some instructions are removed in R6.
+   The problem is that the removed instructions in R6 come from different
+   ISAs.  One approach to solve this would be to describe in the membership
+   field of the opcode table the different ISAs an instruction belongs to.
+   This would require us to create a large amount of different ISA
+   combinations which is hard to manage.  A cleaner approach (which is
+   implemented here) is to say that R6 is an extension of R5 and then to
+   deal with the removed instructions by adding instruction exclusions
+   for R6 in the opcode table.  */
+
 /* Bit INSN_ISA<X> - 1 of INSN_UPTO<Y> is set if ISA Y includes ISA X.  */
+
 #define ISAF(X) (1 << (INSN_ISA##X - 1))
 #define INSN_UPTO1    ISAF(1)
 #define INSN_UPTO2    INSN_UPTO1 | ISAF(2)
@@ -1096,10 +1161,12 @@ struct mips_opcode
 			| ISAF(3_32R2) | ISAF(4_32R2) | ISAF(5_32R2)
 #define INSN_UPTO32R3 INSN_UPTO32R2 | ISAF(32R3)
 #define INSN_UPTO32R5 INSN_UPTO32R3 | ISAF(32R5)
+#define INSN_UPTO32R6 INSN_UPTO32R5 | ISAF(32R6)
 #define INSN_UPTO64   INSN_UPTO5 | ISAF(64) | ISAF(32)
 #define INSN_UPTO64R2 INSN_UPTO64 | ISAF(64R2) | ISAF(32R2)
 #define INSN_UPTO64R3 INSN_UPTO64R2 | ISAF(64R3) | ISAF(32R3)
 #define INSN_UPTO64R5 INSN_UPTO64R3 | ISAF(64R5) | ISAF(32R5)
+#define INSN_UPTO64R6 INSN_UPTO64R5 | ISAF(64R6) | ISAF(32R6)
 
 /* The same information in table form: bit INSN_ISA<X> - 1 of index
    INSN_UPTO<Y> - 1 is set if ISA Y includes ISA X.  */
@@ -1113,11 +1180,12 @@ static const unsigned int mips_isa_table[] = {
   INSN_UPTO32R2,
   INSN_UPTO32R3,
   INSN_UPTO32R5,
-  0,
+  INSN_UPTO32R6,
   INSN_UPTO64,
   INSN_UPTO64R2,
   INSN_UPTO64R3,
-  INSN_UPTO64R5
+  INSN_UPTO64R5,
+  INSN_UPTO64R6
 };
 #undef ISAF
 
@@ -1207,6 +1275,8 @@ static const unsigned int mips_isa_table[] = {
 #define       ISA_MIPS64R3    INSN_ISA64R3
 #define       ISA_MIPS64R5    INSN_ISA64R5
 
+#define       ISA_MIPS32R6    INSN_ISA32R6
+#define       ISA_MIPS64R6    INSN_ISA64R6
 
 /* CPU defines, use instead of hardcoding processor number. Keep this
    in sync with bfd/archures.c in order for machine selection to work.  */
@@ -1239,11 +1309,13 @@ static const unsigned int mips_isa_table[] = {
 #define CPU_MIPS32R2	33
 #define CPU_MIPS32R3	34
 #define CPU_MIPS32R5	36
+#define CPU_MIPS32R6	37
 #define CPU_MIPS5       5
 #define CPU_MIPS64      64
 #define CPU_MIPS64R2	65
 #define CPU_MIPS64R3	66
 #define CPU_MIPS64R5	68
+#define CPU_MIPS64R6	69
 #define CPU_SB1         12310201        /* octal 'SB', 01.  */
 #define CPU_LOONGSON_2E 3001
 #define CPU_LOONGSON_2F 3002
@@ -1319,6 +1391,13 @@ cpu_is_member (int cpu, unsigned int mask)
     case CPU_XLR:
       return (mask & INSN_XLR) != 0;
 
+    case CPU_MIPS32R6:
+      return (mask & INSN_ISA_MASK) == INSN_ISA32R6;
+
+    case CPU_MIPS64R6:
+      return ((mask & INSN_ISA_MASK) == INSN_ISA32R6)
+	     || ((mask & INSN_ISA_MASK) == INSN_ISA64R6);
+
     default:
       return FALSE;
     }
@@ -2160,8 +2239,8 @@ extern const int bfd_mips16_num_opcodes;
 
    Characters used so far, for quick reference when adding more:
    "12345678 0"
-   "<>(),+.@\^|~"
-   "A CDEFGHI KLMN   RST V    "
+   "<>(),+-.@\^|~"
+   "ABCDEFGHI KLMN   RST V    "
    "abcd f hijklmnopqrstuvw yz"
 
    Extension character sequences used so far ("+" followed by the
@@ -2177,6 +2256,12 @@ extern const int bfd_mips16_num_opcodes;
    ""
    " BCDEFGHIJ LMNOPQ   U WXYZ"
    " bcdefghij lmn pq st   xyz"
+
+   Extension character sequences used so far ("-" followed by the
+   following), for quick reference when adding more:
+   ""
+   ""
+   <none so far>
 */
 
 extern const struct mips_operand *decode_micromips_operand (const char *);
diff --git a/ld/ChangeLog b/ld/ChangeLog
index ba4ad9722b2..d50a4562806 100644
--- a/ld/ChangeLog
+++ b/ld/ChangeLog
@@ -1,3 +1,8 @@
+2014-09-15  Andrew Bennett  <andrew.bennett@imgtec.com>
+	    Matthew Fortune  <matthew.fortune@imgtec.com>
+
+	* ldmain.c (get_emulation): Add support for -mips32r6 and -mips64r6.
+
 2014-09-12  Andrew Bennett  <andrew.bennett@imgtec.com>
 
 	* configure.tgt: Add mips*-img-elf* target triple.
diff --git a/ld/ldmain.c b/ld/ldmain.c
index 77235d52216..bc24957b2a2 100644
--- a/ld/ldmain.c
+++ b/ld/ldmain.c
@@ -611,8 +611,10 @@ get_emulation (int argc, char **argv)
 		   || strcmp (argv[i], "-mips5") == 0
 		   || strcmp (argv[i], "-mips32") == 0
 		   || strcmp (argv[i], "-mips32r2") == 0
+		   || strcmp (argv[i], "-mips32r6") == 0
 		   || strcmp (argv[i], "-mips64") == 0
-		   || strcmp (argv[i], "-mips64r2") == 0)
+		   || strcmp (argv[i], "-mips64r2") == 0
+		   || strcmp (argv[i], "-mips64r6") == 0)
 	    {
 	      /* FIXME: The arguments -mips1, -mips2, -mips3, etc. are
 		 passed to the linker by some MIPS compilers.  They
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 09fb297f5c5..ecab314ce8f 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,33 @@
+2014-09-15  Andrew Bennett  <andrew.bennett@imgtec.com>
+	    Matthew Fortune  <matthew.fortune@imgtec.com>
+
+	* mips-dis.c (mips_arch_choices): Add entries for mips32r6 and
+	mips64r6.
+	(parse_mips_dis_option): Allow MSA and virtualization support for
+	mips64r6.
+	(mips_print_arg_state): Add fields dest_regno and seen_dest.
+	(mips_seen_register): New function.
+	(print_insn_arg): Refactored code to use mips_seen_register
+	function.  Add support for OP_SAME_RS_RT, OP_CHECK_PREV and
+	OP_NON_ZERO_REG.  Changed OP_REPEAT_DEST_REG case to print out
+	the register rather than aborting.
+	(print_insn_args): Add length argument.  Add code to correctly
+	calculate the instruction address for pc relative instructions.
+	(validate_insn_args): New static function.
+	(print_insn_mips): Prevent jalx disassembling for r6.  Use
+	validate_insn_args.
+	(print_insn_micromips): Use validate_insn_args.
+	all the arguments are valid.
+	* mips-formats.h (PREV_CHECK): New define.
+	* mips-opc.c (decode_mips_operand): Add support for -a, -b, -d, -s,
+	-t, -u, -v, -w, -x, -y, -A, -B, +I, +O, +R, +:, +\, +", +;
+	(RD_pc): New define.
+	(FS): New define.
+	(I37): New define.
+	(I69): New define.
+	(mips_builtin_opcodes): Add MIPS R6 instructions.  Exclude recoded
+	MIPS R6 instructions from MIPS R2 instructions.
+
 2014-09-10  H.J. Lu  <hongjiu.lu@intel.com>
 
 	* i386-dis.c (dis386): Replace "P" with "%LP" for iret and sysret.
diff --git a/opcodes/mips-dis.c b/opcodes/mips-dis.c
index b797e5dad51..1eb1d45b1a3 100644
--- a/opcodes/mips-dis.c
+++ b/opcodes/mips-dis.c
@@ -572,6 +572,14 @@ const struct mips_arch_choice mips_arch_choices[] =
     mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
     mips_cp1_names_mips3264, mips_hwr_names_mips3264r2 },
 
+  { "mips32r6",	1, bfd_mach_mipsisa32r6, CPU_MIPS32R6,
+    ISA_MIPS32R6,
+    (ASE_EVA | ASE_MSA | ASE_VIRT | ASE_XPA | ASE_MCU | ASE_MT | ASE_DSP
+     | ASE_DSPR2),
+    mips_cp0_names_mips3264r2,
+    mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
+    mips_cp1_names_mips3264, mips_hwr_names_mips3264r2 },
+
   /* For stock MIPS64, disassemble all applicable MIPS-specified ASEs.  */
   { "mips64",	1, bfd_mach_mipsisa64, CPU_MIPS64,
     ISA_MIPS64,  ASE_MIPS3D | ASE_MDMX,
@@ -603,6 +611,14 @@ const struct mips_arch_choice mips_arch_choices[] =
     mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
     mips_cp1_names_mips3264, mips_hwr_names_mips3264r2 },
 
+  { "mips64r6",	1, bfd_mach_mipsisa64r6, CPU_MIPS64R6,
+    ISA_MIPS64R6,
+    (ASE_EVA | ASE_MSA | ASE_MSA64 | ASE_XPA | ASE_VIRT | ASE_VIRT64
+     | ASE_MCU | ASE_MT | ASE_DSP | ASE_DSPR2),
+    mips_cp0_names_mips3264r2,
+    mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
+    mips_cp1_names_mips3264, mips_hwr_names_mips3264r2 },
+
   { "sb1",	1, bfd_mach_mips_sb1, CPU_SB1,
     ISA_MIPS64 | INSN_SB1,  ASE_MIPS3D,
     mips_cp0_names_sb1,
@@ -832,7 +848,8 @@ parse_mips_dis_option (const char *option, unsigned int len)
       mips_ase |= ASE_MSA;
       if ((mips_isa & INSN_ISA_MASK) == ISA_MIPS64R2
 	   || (mips_isa & INSN_ISA_MASK) == ISA_MIPS64R3
-	   || (mips_isa & INSN_ISA_MASK) == ISA_MIPS64R5)
+	   || (mips_isa & INSN_ISA_MASK) == ISA_MIPS64R5
+	   || (mips_isa & INSN_ISA_MASK) == ISA_MIPS64R6)
 	  mips_ase |= ASE_MSA64;
       return;
     }
@@ -842,7 +859,8 @@ parse_mips_dis_option (const char *option, unsigned int len)
       mips_ase |= ASE_VIRT;
       if (mips_isa & ISA_MIPS64R2
 	  || mips_isa & ISA_MIPS64R3
-	  || mips_isa & ISA_MIPS64R5)
+	  || mips_isa & ISA_MIPS64R5
+	  || mips_isa & ISA_MIPS64R6)
 	mips_ase |= ASE_VIRT64;
       return;
     }
@@ -1084,6 +1102,8 @@ struct mips_print_arg_state {
      OP_REPEAT_DEST_REG and OP_REPEAT_PREV_REG.  */
   enum mips_reg_operand_type last_reg_type;
   unsigned int last_regno;
+  unsigned int dest_regno;
+  unsigned int seen_dest;
 };
 
 /* Initialize STATE for the start of an instruction.  */
@@ -1113,6 +1133,23 @@ print_vu0_channel (struct disassemble_info *info,
     abort ();
 }
 
+/* Record information about a register operand.  */
+
+static void
+mips_seen_register (struct mips_print_arg_state *state,
+		    unsigned int regno,
+		    enum mips_reg_operand_type reg_type)
+{
+  state->last_reg_type = reg_type;
+  state->last_regno = regno;
+
+  if (!state->seen_dest)
+    {
+      state->seen_dest = 1;
+      state->dest_regno = regno;
+    }
+}
+
 /* Print operand OPERAND of OPCODE, using STATE to track inter-operand state.
    UVAL is the encoding of the operand (shifted into bit 0) and BASE_PC is
    the base address for OP_PCREL operands.  */
@@ -1179,8 +1216,7 @@ print_insn_arg (struct disassemble_info *info,
 	uval = mips_decode_reg_operand (reg_op, uval);
 	print_reg (info, opcode, reg_op->reg_type, uval);
 
-	state->last_reg_type = reg_op->reg_type;
-	state->last_regno = uval;
+	mips_seen_register (state, uval, reg_op->reg_type);
       }
       break;
 
@@ -1246,6 +1282,15 @@ print_insn_arg (struct disassemble_info *info,
       }
       break;
 
+    case OP_SAME_RS_RT:
+    case OP_CHECK_PREV:
+    case OP_NON_ZERO_REG:
+      {
+	print_reg (info, opcode, OP_REG_GP, uval & 31);
+	mips_seen_register (state, uval, OP_REG_GP);
+      }
+      break;
+
     case OP_LWM_SWM_LIST:
       if (operand->size == 2)
 	{
@@ -1368,8 +1413,8 @@ print_insn_arg (struct disassemble_info *info,
       break;
 
     case OP_REPEAT_DEST_REG:
-      /* Should always match OP_REPEAT_PREV_REG first.  */
-      abort ();
+      print_reg (info, opcode, state->last_reg_type, state->dest_regno);
+      break;
 
     case OP_PC:
       infprintf (is, "$pc");
@@ -1392,15 +1437,130 @@ print_insn_arg (struct disassemble_info *info,
     }
 }
 
+/* Validate the arguments for INSN, which is described by OPCODE.
+   Use DECODE_OPERAND to get the encoding of each operand.  */
+
+static bfd_boolean
+validate_insn_args (const struct mips_opcode *opcode,
+		    const struct mips_operand *(*decode_operand) (const char *),
+		    unsigned int insn)
+{
+  struct mips_print_arg_state state;
+  const struct mips_operand *operand;
+  const char *s;
+  unsigned int uval;
+
+  init_print_arg_state (&state);
+  for (s = opcode->args; *s; ++s)
+    {
+      switch (*s)
+	{
+	case ',':
+	case '(':
+	case ')':
+	  break;
+
+	case '#':
+	  ++s;
+	  break;
+
+	default:
+	  operand = decode_operand (s);
+
+	  if (operand)
+	    {
+	      uval = mips_extract_operand (operand, insn);
+	      switch (operand->type)
+		{
+		case OP_REG:
+		case OP_OPTIONAL_REG:
+		  {
+		    const struct mips_reg_operand *reg_op;
+
+		    reg_op = (const struct mips_reg_operand *) operand;
+		    uval = mips_decode_reg_operand (reg_op, uval);
+		    mips_seen_register (&state, uval, reg_op->reg_type);
+		  }
+		break;
+
+		case OP_SAME_RS_RT:
+		  {
+		    unsigned int reg1, reg2;
+
+		    reg1 = uval & 31;
+		    reg2 = uval >> 5;
+
+		    if (reg1 != reg2 || reg1 == 0)
+		      return FALSE;
+		  }
+		break;
+
+		case OP_CHECK_PREV:
+		  {
+		    const struct mips_check_prev_operand *prev_op;
+
+		    prev_op = (const struct mips_check_prev_operand *) operand;
+
+		    if (!prev_op->zero_ok && uval == 0)
+		      return FALSE;
+
+		    if (((prev_op->less_than_ok && uval < state.last_regno)
+			|| (prev_op->greater_than_ok && uval > state.last_regno)
+			|| (prev_op->equal_ok && uval == state.last_regno)))
+		      break;
+
+		    return FALSE;
+		  }
+
+		case OP_NON_ZERO_REG:
+		  {
+		    if (uval == 0)
+		      return FALSE;
+		  }
+		break;
+
+		case OP_INT:
+		case OP_MAPPED_INT:
+		case OP_MSB:
+		case OP_REG_PAIR:
+		case OP_PCREL:
+		case OP_PERF_REG:
+		case OP_ADDIUSP_INT:
+		case OP_CLO_CLZ_DEST:
+		case OP_LWM_SWM_LIST:
+		case OP_ENTRY_EXIT_LIST:
+		case OP_MDMX_IMM_REG:
+		case OP_REPEAT_PREV_REG:
+		case OP_REPEAT_DEST_REG:
+		case OP_PC:
+		case OP_VU0_SUFFIX:
+		case OP_VU0_MATCH_SUFFIX:
+		case OP_IMM_INDEX:
+		case OP_REG_INDEX:
+		  break;
+
+		case OP_SAVE_RESTORE_LIST:
+		/* Should be handled by the caller due to extend behavior.  */
+		  abort ();
+		}
+	    }
+	  if (*s == 'm' || *s == '+' || *s == '-')
+	    ++s;
+	}
+    }
+  return TRUE;
+}
+
 /* Print the arguments for INSN, which is described by OPCODE.
    Use DECODE_OPERAND to get the encoding of each operand.  Use BASE_PC
-   as the base of OP_PCREL operands.  */
+   as the base of OP_PCREL operands, adjusting by LENGTH if the OP_PCREL
+   operand is for a branch or jump.  */
 
 static void
 print_insn_args (struct disassemble_info *info,
 		 const struct mips_opcode *opcode,
 		 const struct mips_operand *(*decode_operand) (const char *),
-		 unsigned int insn, bfd_vma base_pc)
+		 unsigned int insn, bfd_vma insn_pc, unsigned int length)
 {
   const fprintf_ftype infprintf = info->fprintf_func;
   void *is = info->stream;
@@ -1462,9 +1622,27 @@ print_insn_args (struct disassemble_info *info,
 		infprintf (is, "$%d,%d", reg, sel);
 	    }
 	  else
-	    print_insn_arg (info, &state, opcode, operand, base_pc,
-			    mips_extract_operand (operand, insn));
-	  if (*s == 'm' || *s == '+')
+	    {
+	      bfd_vma base_pc = insn_pc;
+
+	      /* Adjust the PC relative base so that branch/jump insns use
+		 the following PC as the base but genuinely PC relative
+		 operands use the current PC.  */
+	      if (operand->type == OP_PCREL)
+		{
+		  const struct mips_pcrel_operand *pcrel_op;
+
+		  pcrel_op = (const struct mips_pcrel_operand *) operand;
+		  /* The include_isa_bit flag is sufficient to distinguish
+		     branch/jump from other PC relative operands.  */
+		  if (pcrel_op->include_isa_bit)
+		    base_pc += length;
+		}
+
+	      print_insn_arg (info, &state, opcode, operand, base_pc,
+			      mips_extract_operand (operand, insn));
+	    }
+	  if (*s == 'm' || *s == '+' || *s == '-')
 	    ++s;
 	  break;
 	}
@@ -1530,9 +1708,11 @@ print_insn_mips (bfd_vma memaddr,
 	      && !(no_aliases && (op->pinfo2 & INSN2_ALIAS))
 	      && (word & op->mask) == op->match)
 	    {
-	      /* We always allow to disassemble the jalx instruction.  */
+	      /* We always disassemble the jalx instruction, except for MIPS r6.  */
 	      if (!opcode_is_member (op, mips_isa, mips_ase, mips_processor)
-		  && strcmp (op->name, "jalx"))
+		 && (strcmp (op->name, "jalx")
+		     || (mips_isa & INSN_ISA_MASK) == ISA_MIPS32R6
+		     || (mips_isa & INSN_ISA_MASK) == ISA_MIPS64R6))
 		continue;
 
 	      /* Figure out instruction type and branch delay information.  */
@@ -1557,6 +1737,9 @@ print_insn_mips (bfd_vma memaddr,
 				     | INSN_LOAD_MEMORY)) != 0)
 		info->insn_type = dis_dref;
 
+	      if (!validate_insn_args (op, decode_mips_operand, word))
+		continue;
+
 	      infprintf (is, "%s", op->name);
 	      if (op->pinfo2 & INSN2_VU0_CHANNEL_SUFFIX)
 		{
@@ -1571,7 +1754,7 @@ print_insn_mips (bfd_vma memaddr,
 		{
 		  infprintf (is, "\t");
 		  print_insn_args (info, op, decode_mips_operand, word,
-				   memaddr + 4);
+				   memaddr, 4);
 		}
 
 	      return INSNLEN;
@@ -2077,13 +2260,16 @@ print_insn_micromips (bfd_vma memaddr, struct disassemble_info *info)
 	  && ((length == 2 && (op->mask & 0xffff0000) == 0)
 	      || (length == 4 && (op->mask & 0xffff0000) != 0)))
 	{
+	  if (!validate_insn_args (op, decode_micromips_operand, insn))
+	    continue;
+
 	  infprintf (is, "%s", op->name);
 
 	  if (op->args[0])
 	    {
 	      infprintf (is, "\t");
 	      print_insn_args (info, op, decode_micromips_operand, insn,
-			       memaddr + length + 1);
+			       memaddr + 1, length);
 	    }
 
 	  /* Figure out instruction type and branch delay information.  */
diff --git a/opcodes/mips-formats.h b/opcodes/mips-formats.h
index afc9e4a6b73..116d7c880e6 100644
--- a/opcodes/mips-formats.h
+++ b/opcodes/mips-formats.h
@@ -134,3 +134,11 @@
     static const struct mips_operand op = { OP_##TYPE, SIZE, LSB }; \
     return &op; \
   }
+
+#define PREV_CHECK(SIZE, LSB, GT_OK, LT_OK, EQ_OK, ZERO_OK) \
+  { \
+    static const struct mips_check_prev_operand op = { \
+      { OP_CHECK_PREV, SIZE, LSB }, GT_OK, LT_OK, EQ_OK, ZERO_OK \
+    }; \
+    return &op.root; \
+  }
diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c
index 6e3167f5e0a..0e9f716916e 100644
--- a/opcodes/mips-opc.c
+++ b/opcodes/mips-opc.c
@@ -40,6 +40,24 @@ decode_mips_operand (const char *p)
 {
   switch (p[0])
     {
+    case '-':
+      switch (p[1])
+	{
+	case 'a': INT_ADJ (19, 0, 262143, 2, FALSE);
+	case 'b': INT_ADJ (18, 0, 131071, 3, FALSE);
+	case 'd': SPECIAL (0, 0, REPEAT_DEST_REG);
+	case 's': SPECIAL (5, 21, NON_ZERO_REG);
+	case 't': SPECIAL (5, 16, NON_ZERO_REG);
+	case 'u': PREV_CHECK (5, 16, TRUE, FALSE, FALSE, TRUE);
+	case 'v': PREV_CHECK (5, 16, TRUE, TRUE, FALSE, FALSE);
+	case 'w': PREV_CHECK (5, 16, FALSE, TRUE, TRUE, TRUE);
+	case 'x': PREV_CHECK (5, 21, TRUE, FALSE, FALSE, TRUE);
+	case 'y': PREV_CHECK (5, 21, FALSE, TRUE, TRUE, FALSE);
+	case 'A': PCREL (19, 0, TRUE, 2, 2, FALSE, FALSE);
+	case 'B': PCREL (18, 0, TRUE, 3, 3, FALSE, FALSE);
+	}
+      break;
+
     case '+':
       switch (p[1])
 	{
@@ -61,13 +79,16 @@ decode_mips_operand (const char *p)
 	case 'F': MSB (5, 11, 33, TRUE, 64);	/* (33 .. 64), 64-bit op */
 	case 'G': MSB (5, 11, 33, FALSE, 64);	/* (33 .. 64), 64-bit op */
 	case 'H': MSB (5, 11, 1, FALSE, 64);	/* (1 .. 32), 64-bit op */
+	case 'I': UINT (2, 6);
 	case 'J': HINT (10, 11);
 	case 'K': SPECIAL (4, 21, VU0_MATCH_SUFFIX);
 	case 'L': SPECIAL (2, 21, VU0_SUFFIX);
 	case 'M': SPECIAL (2, 23, VU0_SUFFIX);
 	case 'N': SPECIAL (2, 0, VU0_MATCH_SUFFIX);
+	case 'O': UINT (3, 6);
 	case 'P': BIT (5, 6, 32);		/* (32 .. 63) */
 	case 'Q': SINT (10, 6);
+	case 'R': SPECIAL (0, 0, PC);
 	case 'S': MSB (5, 11, 0, FALSE, 63);	/* (0 .. 31), 64-bit op */
 	case 'T': INT_ADJ (10, 16, 511, 0, FALSE); /* (-512 .. 511) << 0 */
 	case 'U': INT_ADJ (10, 16, 511, 1, FALSE); /* (-512 .. 511) << 1 */
@@ -113,6 +134,10 @@ decode_mips_operand (const char *p)
 	case '&': SPECIAL (0, 0, IMM_INDEX);
 	case '*': SPECIAL (5, 16, REG_INDEX);
 	case '|': BIT (8, 16, 0);		/* (0 .. 255) */
+	case ':': SINT (11, 0);
+	case '\'': BRANCH (26, 0, 2);
+	case '"': BRANCH (21, 0, 2);
+	case ';': SPECIAL (10, 16, SAME_RS_RT);
 	}
       break;
 
@@ -241,6 +266,9 @@ decode_mips_operand (const char *p)
 #define WR_MACC INSN2_WRITE_MDMX_ACC
 #define RD_MACC INSN2_READ_MDMX_ACC
 
+#define RD_pc   INSN2_READ_PC
+#define FS      INSN2_FORBIDDEN_SLOT
+
 #define I1	INSN_ISA1
 #define I2	INSN_ISA2
 #define I3	INSN_ISA3
@@ -251,9 +279,11 @@ decode_mips_operand (const char *p)
 #define I33	INSN_ISA32R2
 #define I34	INSN_ISA32R3
 #define I36	INSN_ISA32R5
+#define I37	INSN_ISA32R6
 #define I65	INSN_ISA64R2
 #define I66	INSN_ISA64R3
 #define I68	INSN_ISA64R5
+#define I69	INSN_ISA64R6
 #define I3_32   INSN_ISA3_32
 #define I3_33   INSN_ISA3_32R2
 #define I4_32   INSN_ISA4_32
@@ -383,9 +413,10 @@ const struct mips_opcode mips_builtin_opcodes[] =
    them first.  The assemblers uses a hash table based on the
    instruction name anyhow.  */
 /* name,		args,		match,	    mask,	pinfo,          	pinfo2,		membership,	ase,	exclusions */
-{"pref",		"k,o(b)",	0xcc000000, 0xfc000000, RD_3|LM,           	0,		I4_32|G3,	0,	0 },
+{"pref",		"k,+j(b)",	0x7c000035, 0xfc00007f, RD_3,			0,		I37,		0,	0 },
+{"pref",		"k,o(b)",	0xcc000000, 0xfc000000, RD_3|LM,           	0,		I4_32|G3,	0,	I37 },
 {"pref",		"k,A(b)",	0,    (int) M_PREF_AB,	INSN_MACRO,		0,		I4_32|G3,	0,	0 },
-{"prefx",		"h,t(b)",	0x4c00000f, 0xfc0007ff, RD_2|RD_3|FP_S|LM,		0,		I4_33,		0,	0 },
+{"prefx",		"h,t(b)",	0x4c00000f, 0xfc0007ff, RD_2|RD_3|FP_S|LM,		0,		I4_33,		0,	I37 },
 {"nop",			"",		0x00000000, 0xffffffff, 0,              	INSN2_ALIAS,	I1,		0,	0 }, /* sll */
 {"ssnop",		"",		0x00000040, 0xffffffff, 0,              	INSN2_ALIAS,	I1,		0,	0 }, /* sll */
 {"ehb",			"",		0x000000c0, 0xffffffff, 0,              	INSN2_ALIAS,	I1,		0,	0 }, /* sll */
@@ -398,7 +429,12 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"move",		"d,s",		0x00000025, 0xfc1f07ff,	WR_1|RD_2,		INSN2_ALIAS,	I1,		0,	0 },/* or */
 {"b",			"p",		0x10000000, 0xffff0000,	UBD,			INSN2_ALIAS,	I1,		0,	0 },/* beq 0,0 */
 {"b",			"p",		0x04010000, 0xffff0000,	UBD,			INSN2_ALIAS,	I1,		0,	0 },/* bgez 0 */
+{"nal",			"p",		0x04100000, 0xffff0000,	WR_31|CBD,		INSN2_ALIAS,	I1,		0,	0 },/* bltzal 0 */
 {"bal",			"p",		0x04110000, 0xffff0000,	WR_31|UBD,		INSN2_ALIAS,	I1,		0,	0 },/* bgezal 0*/
+{"bc",			"+'",		0xc8000000, 0xfc000000,	NODS,			0,		I37,		0,	0 },
+{"balc",		"+'",		0xe8000000, 0xfc000000,	WR_31|NODS,		0,		I37,		0,	0 },
+{"lapc",		"s,-A",		0xec000000, 0xfc180000, WR_1,			RD_pc,		I37,		0,	0 },
+{"la",			"t,A(b)",	0,    (int) M_LA_AB,	INSN_MACRO,		0,		I1,		0,	0 },
 
 /* Loongson specific instructions.  Loongson 3A redefines the Coprocessor 2
    instructions.  Put them here so that disassembler will find them first.
@@ -592,26 +628,28 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"abs",			"d,v",		0,    (int) M_ABS,	INSN_MACRO,		0,		I1,		0,	0 },
 {"abs.s",		"D,V",		0x46000005, 0xffff003f,	WR_1|RD_2|FP_S,		0,		I1,		0,	0 },
 {"abs.d",		"D,V",		0x46200005, 0xffff003f,	WR_1|RD_2|FP_D,		0,		I1,		0,	SF },
-{"abs.ps",		"D,V",		0x46c00005, 0xffff003f,	WR_1|RD_2|FP_D,		0,		I5_33|IL2F,	0,	0 },
+{"abs.ps",		"D,V",		0x46c00005, 0xffff003f,	WR_1|RD_2|FP_D,		0,		I5_33|IL2F,	0,	I37 },
 {"abs.ps",		"D,V",		0x45600005, 0xffff003f,	WR_1|RD_2|FP_D,		0,		IL2E,		0,	0 },
 {"aclr",		"\\,~(b)",	0x04070000, 0xfc1f8000,	RD_3|LM|SM|NODS,	0,		0,		MC,	0 },
 {"aclr",		"\\,A(b)",	0,    (int) M_ACLR_AB,	INSN_MACRO,		0,		0,		MC,	0 },
 {"add",			"d,v,t",	0x00000020, 0xfc0007ff,	WR_1|RD_2|RD_3,		0,		I1,		0,	0 },
-{"add",			"t,r,I",	0,    (int) M_ADD_I,	INSN_MACRO,		0,		I1,		0,	0 },
+{"add",			"t,r,I",	0,    (int) M_ADD_I,	INSN_MACRO,		0,		I1,		0,	I37 },
 {"add",			"D,S,T",	0x45c00000, 0xffe0003f,	WR_1|RD_2|RD_3|FP_S,	0,		IL2E,		0,	0 },
 {"add",			"D,S,T",	0x4b40000c, 0xffe0003f,	WR_1|RD_2|RD_3|FP_S,	0,		IL2F|IL3A,	0,	0 },
 {"add.s",		"D,V,T",	0x46000000, 0xffe0003f,	WR_1|RD_2|RD_3|FP_S,	0,		I1,		0,	0 },
 {"add.d",		"D,V,T",	0x46200000, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		I1,		0,	SF },
 {"add.ob",		"X,Y,Q",	0x7800000b, 0xfc20003f,	WR_1|RD_2|RD_3|FP_D,	0,		SB1,		MX,	0 },
 {"add.ob",		"D,S,Q",	0x4800000b, 0xfc20003f,	WR_1|RD_2|RD_3|FP_D,	0,		N54,		0,	0 },
-{"add.ps",		"D,V,T",	0x46c00000, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		I5_33|IL2F,	0,	0 },
+{"add.ps",		"D,V,T",	0x46c00000, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		I5_33|IL2F,	0,	I37 },
 {"add.ps",		"D,V,T",	0x45600000, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2E,		0,	0 },
 {"add.qh",		"X,Y,Q",	0x7820000b, 0xfc20003f,	WR_1|RD_2|RD_3|FP_D,	0,		0,		MX,	0 },
 {"adda.ob",		"Y,Q",		0x78000037, 0xfc2007ff,	RD_1|RD_2|FP_D,		WR_MACC,	SB1,		MX,	0 },
 {"adda.qh",		"Y,Q",		0x78200037, 0xfc2007ff,	RD_1|RD_2|FP_D,		WR_MACC,	0,		MX,	0 },
 {"adda.s",		"S,T",		0x46000018, 0xffe007ff,	RD_1|RD_2|FP_S,		0,		EE,		0,	0 },
-{"addi",		"t,r,j",	0x20000000, 0xfc000000,	WR_1|RD_2,		0,		I1,		0,	0 },
+{"addi",		"t,r,j",	0x20000000, 0xfc000000,	WR_1|RD_2,		0,		I1,		0,	I37 },
 {"addiu",		"t,r,j",	0x24000000, 0xfc000000,	WR_1|RD_2,		0,		I1,		0,	0 },
+{"addiu",		"s,+R,-a",	0xec000000, 0xfc180000, WR_1,			RD_pc,		I37,		0,	0 },
+{"addiupc",		"s,-a",		0xec000000, 0xfc180000, WR_1,			RD_pc,		I37,		0,	0 },
 {"addl.ob",		"Y,Q",		0x78000437, 0xfc2007ff,	RD_1|RD_2|FP_D,		WR_MACC,	SB1,		MX,	0 },
 {"addl.qh",		"Y,Q",		0x78200437, 0xfc2007ff,	RD_1|RD_2|FP_D,		WR_MACC,	0,		MX,	0 },
 {"addr.ps",		"D,S,T",	0x46c00018, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		0,		M3D,	0 },
@@ -622,7 +660,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"alni.ob",		"X,Y,Z,O",	0x78000018, 0xff00003f,	WR_1|RD_2|RD_3|FP_D,	0,		SB1,		MX,	0 },
 {"alni.ob",		"D,S,T,%",	0x48000018, 0xff00003f,	WR_1|RD_2|RD_3|FP_D, 	0,		N54,		0,	0 },
 {"alni.qh",		"X,Y,Z,O",	0x7800001a, 0xff00003f,	WR_1|RD_2|RD_3|FP_D,	0,		0,		MX,	0 },
-{"alnv.ps",		"D,V,T,s",	0x4c00001e, 0xfc00003f,	WR_1|RD_2|RD_3|RD_4|FP_D, 0,		I5_33,		0,	0 },
+{"alnv.ps",		"D,V,T,s",	0x4c00001e, 0xfc00003f,	WR_1|RD_2|RD_3|RD_4|FP_D, 0,		I5_33,		0,	I37 },
 {"alnv.ob",		"X,Y,Z,s",	0x78000019, 0xfc00003f,	WR_1|RD_2|RD_3|RD_4|FP_D, 0,		SB1,		MX,	0 },
 {"alnv.qh",		"X,Y,Z,s",	0x7800001b, 0xfc00003f,	WR_1|RD_2|RD_3|RD_4|FP_D, 0,		0,		MX,	0 },
 {"and",			"d,v,t",	0x00000024, 0xfc0007ff,	WR_1|RD_2|RD_3,		0,		I1,		0,	0 },
@@ -649,198 +687,200 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"bc1any2t",		"N,p",		0x45210000, 0xffe30000,	RD_CC|CBD|FP_S,		0,		0,		M3D,	0 },
 {"bc1any4f",		"N,p",		0x45400000, 0xffe30000,	RD_CC|CBD|FP_S,		0,		0,		M3D,	0 },
 {"bc1any4t",		"N,p",		0x45410000, 0xffe30000,	RD_CC|CBD|FP_S,		0,		0,		M3D,	0 },
-{"bc1f",		"p",		0x45000000, 0xffff0000,	RD_CC|CBD|FP_S,		0,		I1,		0,	0 },
-{"bc1f",		"N,p",		0x45000000, 0xffe30000, RD_CC|CBD|FP_S, 	0,		I4_32,		0,	0 },
-{"bc1fl",		"p",		0x45020000, 0xffff0000,	RD_CC|CBL|FP_S,		0,		I2|T3,		0,	0 },
-{"bc1fl",		"N,p",		0x45020000, 0xffe30000, RD_CC|CBL|FP_S, 	0,		I4_32,		0,	0 },
-{"bc1t",		"p",		0x45010000, 0xffff0000,	RD_CC|CBD|FP_S,		0,		I1,		0,	0 },
-{"bc1t",		"N,p",		0x45010000, 0xffe30000, RD_CC|CBD|FP_S, 	0,		I4_32,		0,	0 },
-{"bc1tl",		"p",		0x45030000, 0xffff0000,	RD_CC|CBL|FP_S,		0,		I2|T3,		0,	0 },
-{"bc1tl",		"N,p",		0x45030000, 0xffe30000, RD_CC|CBL|FP_S, 	0,		I4_32,		0,	0 },
+{"bc1eqz",		"T,p",		0x45200000, 0xffe00000,	RD_1|CBD|FP_S,		0,		I37,		0,	0 },
+{"bc1f",		"p",		0x45000000, 0xffff0000,	RD_CC|CBD|FP_S,		0,		I1,		0,	I37 },
+{"bc1f",		"N,p",		0x45000000, 0xffe30000, RD_CC|CBD|FP_S, 	0,		I4_32,		0,	I37 },
+{"bc1fl",		"p",		0x45020000, 0xffff0000,	RD_CC|CBL|FP_S,		0,		I2|T3,		0,	I37 },
+{"bc1fl",		"N,p",		0x45020000, 0xffe30000, RD_CC|CBL|FP_S, 	0,		I4_32,		0,	I37 },
+{"bc1nez",		"T,p",		0x45a00000, 0xffe00000,	RD_1|CBD|FP_S,		0,		I37,		0,	0 },
+{"bc1t",		"p",		0x45010000, 0xffff0000,	RD_CC|CBD|FP_S,		0,		I1,		0,	I37 },
+{"bc1t",		"N,p",		0x45010000, 0xffe30000, RD_CC|CBD|FP_S, 	0,		I4_32,		0,	I37 },
+{"bc1tl",		"p",		0x45030000, 0xffff0000,	RD_CC|CBL|FP_S,		0,		I2|T3,		0,	I37 },
+{"bc1tl",		"N,p",		0x45030000, 0xffe30000, RD_CC|CBL|FP_S, 	0,		I4_32,		0,	I37 },
 /* bc2* are at the bottom of the table.  */
 /* bc3* are at the bottom of the table.  */
 {"beqz",		"s,p",		0x10000000, 0xfc1f0000,	RD_1|CBD,		0,		I1,		0,	0 },
-{"beqzl",		"s,p",		0x50000000, 0xfc1f0000,	RD_1|CBL,		0,		I2|T3,		0,	0 },
+{"beqzl",		"s,p",		0x50000000, 0xfc1f0000,	RD_1|CBL,		0,		I2|T3,		0,	I37 },
 {"beq",			"s,t,p",	0x10000000, 0xfc000000,	RD_1|RD_2|CBD,		0,		I1,		0,	0 },
 {"beq",			"s,I,p",	0,    (int) M_BEQ_I,	INSN_MACRO,		0,		I1,		0,	0 },
-{"beql",		"s,t,p",	0x50000000, 0xfc000000,	RD_1|RD_2|CBL,		0,		I2|T3,		0,	0 },
-{"beql",		"s,I,p",	0,    (int) M_BEQL_I,	INSN_MACRO,		0,		I2|T3,		0,	0 },
+{"beql",		"s,t,p",	0x50000000, 0xfc000000,	RD_1|RD_2|CBL,		0,		I2|T3,		0,	I37 },
+{"beql",		"s,I,p",	0,    (int) M_BEQL_I,	INSN_MACRO,		0,		I2|T3,		0,	I37 },
 {"bge",			"s,t,p",	0,    (int) M_BGE,	INSN_MACRO,		0,		I1,		0,	0 },
 {"bge",			"s,I,p",	0,    (int) M_BGE_I,	INSN_MACRO,		0,		I1,		0,	0 },
-{"bgel",		"s,t,p",	0,    (int) M_BGEL,	INSN_MACRO,		0,		I2|T3,		0,	0 },
-{"bgel",		"s,I,p",	0,    (int) M_BGEL_I,	INSN_MACRO,		0,		I2|T3,		0,	0 },
+{"bgel",		"s,t,p",	0,    (int) M_BGEL,	INSN_MACRO,		0,		I2|T3,		0,	I37 },
+{"bgel",		"s,I,p",	0,    (int) M_BGEL_I,	INSN_MACRO,		0,		I2|T3,		0,	I37 },
 {"bgeu",		"s,t,p",	0,    (int) M_BGEU,	INSN_MACRO,		0,		I1,		0,	0 },
 {"bgeu",		"s,I,p",	0,    (int) M_BGEU_I,	INSN_MACRO,		0,		I1,		0,	0 },
-{"bgeul",		"s,t,p",	0,    (int) M_BGEUL,	INSN_MACRO,		0,		I2|T3,		0,	0 },
-{"bgeul",		"s,I,p",	0,    (int) M_BGEUL_I,	INSN_MACRO,		0,		I2|T3,		0,	0 },
+{"bgeul",		"s,t,p",	0,    (int) M_BGEUL,	INSN_MACRO,		0,		I2|T3,		0,	I37 },
+{"bgeul",		"s,I,p",	0,    (int) M_BGEUL_I,	INSN_MACRO,		0,		I2|T3,		0,	I37 },
 {"bgez",		"s,p",		0x04010000, 0xfc1f0000,	RD_1|CBD,		0,		I1,		0,	0 },
-{"bgezl",		"s,p",		0x04030000, 0xfc1f0000,	RD_1|CBL,		0,		I2|T3,		0,	0 },
-{"bgezal",		"s,p",		0x04110000, 0xfc1f0000,	RD_1|WR_31|CBD,		0,		I1,		0,	0 },
-{"bgezall",		"s,p",		0x04130000, 0xfc1f0000,	RD_1|WR_31|CBL,		0,		I2|T3,		0,	0 },
+{"bgezl",		"s,p",		0x04030000, 0xfc1f0000,	RD_1|CBL,		0,		I2|T3,		0,	I37 },
+{"bgezal",		"s,p",		0x04110000, 0xfc1f0000,	RD_1|WR_31|CBD,		0,		I1,		0,	I37 },
+{"bgezall",		"s,p",		0x04130000, 0xfc1f0000,	RD_1|WR_31|CBL,		0,		I2|T3,		0,	I37 },
 {"bgt",			"s,t,p",	0,    (int) M_BGT,	INSN_MACRO,		0,		I1,		0,	0 },
 {"bgt",			"s,I,p",	0,    (int) M_BGT_I,	INSN_MACRO,		0,		I1,		0,	0 },
-{"bgtl",		"s,t,p",	0,    (int) M_BGTL,	INSN_MACRO,		0,		I2|T3,		0,	0 },
-{"bgtl",		"s,I,p",	0,    (int) M_BGTL_I,	INSN_MACRO,		0,		I2|T3,		0,	0 },
+{"bgtl",		"s,t,p",	0,    (int) M_BGTL,	INSN_MACRO,		0,		I2|T3,		0,	I37 },
+{"bgtl",		"s,I,p",	0,    (int) M_BGTL_I,	INSN_MACRO,		0,		I2|T3,		0,	I37 },
 {"bgtu",		"s,t,p",	0,    (int) M_BGTU,	INSN_MACRO,		0,		I1,		0,	0 },
 {"bgtu",		"s,I,p",	0,    (int) M_BGTU_I,	INSN_MACRO,		0,		I1,		0,	0 },
-{"bgtul",		"s,t,p",	0,    (int) M_BGTUL,	INSN_MACRO,		0,		I2|T3,		0,	0 },
-{"bgtul",		"s,I,p",	0,    (int) M_BGTUL_I,	INSN_MACRO,		0,		I2|T3,		0,	0 },
+{"bgtul",		"s,t,p",	0,    (int) M_BGTUL,	INSN_MACRO,		0,		I2|T3,		0,	I37 },
+{"bgtul",		"s,I,p",	0,    (int) M_BGTUL_I,	INSN_MACRO,		0,		I2|T3,		0,	I37 },
 {"bgtz",		"s,p",		0x1c000000, 0xfc1f0000,	RD_1|CBD,		0,		I1,		0,	0 },
-{"bgtzl",		"s,p",		0x5c000000, 0xfc1f0000,	RD_1|CBL,		0,		I2|T3,		0,	0 },
+{"bgtzl",		"s,p",		0x5c000000, 0xfc1f0000,	RD_1|CBL,		0,		I2|T3,		0,	I37 },
 {"ble",			"s,t,p",	0,    (int) M_BLE,	INSN_MACRO,		0,		I1,		0,	0 },
 {"ble",			"s,I,p",	0,    (int) M_BLE_I,	INSN_MACRO,		0,		I1,		0,	0 },
-{"blel",		"s,t,p",	0,    (int) M_BLEL,	INSN_MACRO,		0,		I2|T3,		0,	0 },
-{"blel",		"s,I,p",	0,    (int) M_BLEL_I,	INSN_MACRO,		0,		I2|T3,		0,	0 },
+{"blel",		"s,t,p",	0,    (int) M_BLEL,	INSN_MACRO,		0,		I2|T3,		0,	I37 },
+{"blel",		"s,I,p",	0,    (int) M_BLEL_I,	INSN_MACRO,		0,		I2|T3,		0,	I37 },
 {"bleu",		"s,t,p",	0,    (int) M_BLEU,	INSN_MACRO,		0,		I1,		0,	0 },
 {"bleu",		"s,I,p",	0,    (int) M_BLEU_I,	INSN_MACRO,		0,		I1,		0,	0 },
-{"bleul",		"s,t,p",	0,    (int) M_BLEUL,	INSN_MACRO,		0,		I2|T3,		0,	0 },
-{"bleul",		"s,I,p",	0,    (int) M_BLEUL_I,	INSN_MACRO,		0,		I2|T3,		0,	0 },
+{"bleul",		"s,t,p",	0,    (int) M_BLEUL,	INSN_MACRO,		0,		I2|T3,		0,	I37 },
+{"bleul",		"s,I,p",	0,    (int) M_BLEUL_I,	INSN_MACRO,		0,		I2|T3,		0,	I37 },
 {"blez",		"s,p",		0x18000000, 0xfc1f0000,	RD_1|CBD,		0,		I1,		0,	0 },
-{"blezl",		"s,p",		0x58000000, 0xfc1f0000,	RD_1|CBL,		0,		I2|T3,		0,	0 },
+{"blezl",		"s,p",		0x58000000, 0xfc1f0000,	RD_1|CBL,		0,		I2|T3,		0,	I37 },
 {"blt",			"s,t,p",	0,    (int) M_BLT,	INSN_MACRO,		0,		I1,		0,	0 },
 {"blt",			"s,I,p",	0,    (int) M_BLT_I,	INSN_MACRO,		0,		I1,		0,	0 },
-{"bltl",		"s,t,p",	0,    (int) M_BLTL,	INSN_MACRO,		0,		I2|T3,		0,	0 },
-{"bltl",		"s,I,p",	0,    (int) M_BLTL_I,	INSN_MACRO,		0,		I2|T3,		0,	0 },
+{"bltl",		"s,t,p",	0,    (int) M_BLTL,	INSN_MACRO,		0,		I2|T3,		0,	I37 },
+{"bltl",		"s,I,p",	0,    (int) M_BLTL_I,	INSN_MACRO,		0,		I2|T3,		0,	I37 },
 {"bltu",		"s,t,p",	0,    (int) M_BLTU,	INSN_MACRO,		0,		I1,		0,	0 },
 {"bltu",		"s,I,p",	0,    (int) M_BLTU_I,	INSN_MACRO,		0,		I1,		0,	0 },
-{"bltul",		"s,t,p",	0,    (int) M_BLTUL,	INSN_MACRO,		0,		I2|T3,		0,	0 },
-{"bltul",		"s,I,p",	0,    (int) M_BLTUL_I,	INSN_MACRO,		0,		I2|T3,		0,	0 },
+{"bltul",		"s,t,p",	0,    (int) M_BLTUL,	INSN_MACRO,		0,		I2|T3,		0,	I37 },
+{"bltul",		"s,I,p",	0,    (int) M_BLTUL_I,	INSN_MACRO,		0,		I2|T3,		0,	I37 },
 {"bltz",		"s,p",		0x04000000, 0xfc1f0000,	RD_1|CBD,		0,		I1,		0,	0 },
-{"bltzl",		"s,p",		0x04020000, 0xfc1f0000,	RD_1|CBL,		0,		I2|T3,		0,	0 },
-{"bltzal",		"s,p",		0x04100000, 0xfc1f0000,	RD_1|WR_31|CBD,		0,		I1,		0,	0 },
-{"bltzall",		"s,p",		0x04120000, 0xfc1f0000,	RD_1|WR_31|CBL,		0,		I2|T3,		0,	0 },
+{"bltzl",		"s,p",		0x04020000, 0xfc1f0000,	RD_1|CBL,		0,		I2|T3,		0,	I37 },
+{"bltzal",		"s,p",		0x04100000, 0xfc1f0000,	RD_1|WR_31|CBD,		0,		I1,		0,	I37 },
+{"bltzall",		"s,p",		0x04120000, 0xfc1f0000,	RD_1|WR_31|CBL,		0,		I2|T3,		0,	I37 },
 {"bnez",		"s,p",		0x14000000, 0xfc1f0000,	RD_1|CBD,		0,		I1,		0,	0 },
-{"bnezl",		"s,p",		0x54000000, 0xfc1f0000,	RD_1|CBL,		0,		I2|T3,		0,	0 },
+{"bnezl",		"s,p",		0x54000000, 0xfc1f0000,	RD_1|CBL,		0,		I2|T3,		0,	I37 },
 {"bne",			"s,t,p",	0x14000000, 0xfc000000,	RD_1|RD_2|CBD,		0,		I1,		0,	0 },
 {"bne",			"s,I,p",	0,    (int) M_BNE_I,	INSN_MACRO,		0,		I1,		0,	0 },
-{"bnel",		"s,t,p",	0x54000000, 0xfc000000,	RD_1|RD_2|CBL, 		0,		I2|T3,		0,	0 },
-{"bnel",		"s,I,p",	0,    (int) M_BNEL_I,	INSN_MACRO,		0,		I2|T3,		0,	0 },
+{"bnel",		"s,t,p",	0x54000000, 0xfc000000,	RD_1|RD_2|CBL, 		0,		I2|T3,		0,	I37 },
+{"bnel",		"s,I,p",	0,    (int) M_BNEL_I,	INSN_MACRO,		0,		I2|T3,		0,	I37 },
 {"break",		"",		0x0000000d, 0xffffffff,	TRAP,			0,		I1,		0,	0 },
 {"break",		"c",		0x0000000d, 0xfc00ffff,	TRAP,			0,		I1,		0,	0 },
 {"break",		"c,q",		0x0000000d, 0xfc00003f,	TRAP,			0,		I1,		0,	0 },
-{"c.f.d",		"S,T",		0x46200030, 0xffe007ff,	RD_1|RD_2|WR_CC|FP_D,	0,		I1,		0,	SF },
-{"c.f.d",		"M,S,T",	0x46200030, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D,   0,		I4_32,		0,	0 },
-{"c.f.s",		"S,T",      	0x46000030, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S,   0,		I1,		0,	0 },
-{"c.f.s",		"M,S,T",	0x46000030, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S,   0,		I4_32,		0,	0 },
-{"c.f.ps",		"S,T",		0x46c00030, 0xffe007ff,	RD_1|RD_2|WR_CC|FP_D,	0,		I5_33|IL2F,	0,	0 },
+{"c.f.d",		"S,T",		0x46200030, 0xffe007ff,	RD_1|RD_2|WR_CC|FP_D,	0,		I1,		0,	SF|I37 },
+{"c.f.d",		"M,S,T",	0x46200030, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D,   0,		I4_32,		0,	I37 },
+{"c.f.s",		"S,T",      	0x46000030, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S,   0,		I1,		0,	I37 },
+{"c.f.s",		"M,S,T",	0x46000030, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S,   0,		I4_32,		0,	I37 },
+{"c.f.ps",		"S,T",		0x46c00030, 0xffe007ff,	RD_1|RD_2|WR_CC|FP_D,	0,		I5_33|IL2F,	0,	I37 },
 {"c.f.ps",		"S,T",		0x45600030, 0xffe007ff,	RD_1|RD_2|WR_CC|FP_D,	0,		IL2E,		0,	0 },
-{"c.f.ps",		"M,S,T",	0x46c00030, 0xffe000ff,	RD_2|RD_3|WR_CC|FP_D,	0,		I5_33,		0,	0 },
-{"c.un.d",		"S,T",		0x46200031, 0xffe007ff,	RD_1|RD_2|WR_CC|FP_D,	0,		I1,		0,	SF },
-{"c.un.d",		"M,S,T",	0x46200031, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D,   0,		I4_32,		0,	0 },
-{"c.un.s",		"S,T",		0x46000031, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S,   0,		I1,		0,	EE },
-{"c.un.s",		"M,S,T",	0x46000031, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S,   0,		I4_32,		0,	0 },
-{"c.un.ps",		"S,T",		0x46c00031, 0xffe007ff,	RD_1|RD_2|WR_CC|FP_D,	0,		I5_33|IL2F,	0,	0 },
+{"c.f.ps",		"M,S,T",	0x46c00030, 0xffe000ff,	RD_2|RD_3|WR_CC|FP_D,	0,		I5_33,		0,	I37 },
+{"c.un.d",		"S,T",		0x46200031, 0xffe007ff,	RD_1|RD_2|WR_CC|FP_D,	0,		I1,		0,	SF|I37 },
+{"c.un.d",		"M,S,T",	0x46200031, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D,   0,		I4_32,		0,	I37 },
+{"c.un.s",		"S,T",		0x46000031, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S,   0,		I1,		0,	EE|I37 },
+{"c.un.s",		"M,S,T",	0x46000031, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S,   0,		I4_32,		0,	I37 },
+{"c.un.ps",		"S,T",		0x46c00031, 0xffe007ff,	RD_1|RD_2|WR_CC|FP_D,	0,		I5_33|IL2F,	0,	I37 },
 {"c.un.ps",		"S,T",		0x45600031, 0xffe007ff,	RD_1|RD_2|WR_CC|FP_D,	0,		IL2E,		0,	0 },
-{"c.un.ps",		"M,S,T",	0x46c00031, 0xffe000ff,	RD_2|RD_3|WR_CC|FP_D,	0,		I5_33,		0,	0 },
-{"c.eq.d",		"S,T",		0x46200032, 0xffe007ff,	RD_1|RD_2|WR_CC|FP_D,	0,		I1,		0,	SF },
-{"c.eq.d",		"M,S,T",	0x46200032, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D,   0,		I4_32,		0,	0 },
-{"c.eq.s",		"S,T",		0x46000032, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S,   0,		I1,		0,	0 },
-{"c.eq.s",		"M,S,T",	0x46000032, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S,   0,		I4_32,		0,	0 },
+{"c.un.ps",		"M,S,T",	0x46c00031, 0xffe000ff,	RD_2|RD_3|WR_CC|FP_D,	0,		I5_33,		0,	I37 },
+{"c.eq.d",		"S,T",		0x46200032, 0xffe007ff,	RD_1|RD_2|WR_CC|FP_D,	0,		I1,		0,	SF|I37 },
+{"c.eq.d",		"M,S,T",	0x46200032, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D,   0,		I4_32,		0,	I37 },
+{"c.eq.s",		"S,T",		0x46000032, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S,   0,		I1,		0,	I37 },
+{"c.eq.s",		"M,S,T",	0x46000032, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S,   0,		I4_32,		0,	I37 },
 {"c.eq.ob",		"Y,Q",		0x78000001, 0xfc2007ff,	RD_1|RD_2|WR_CC|FP_D,	0,		SB1,		MX,	0 },
 {"c.eq.ob",		"S,Q",		0x48000001, 0xfc2007ff,	RD_1|RD_2|WR_CC|FP_D,	0,		N54,		0,	0 },
-{"c.eq.ps",		"S,T",		0x46c00032, 0xffe007ff,	RD_1|RD_2|WR_CC|FP_D,	0,		I5_33|IL2F,	0,	0 },
+{"c.eq.ps",		"S,T",		0x46c00032, 0xffe007ff,	RD_1|RD_2|WR_CC|FP_D,	0,		I5_33|IL2F,	0,	I37 },
 {"c.eq.ps",		"S,T",		0x45600032, 0xffe007ff,	RD_1|RD_2|WR_CC|FP_D,	0,		IL2E,		0,	0 },
-{"c.eq.ps",		"M,S,T",	0x46c00032, 0xffe000ff,	RD_2|RD_3|WR_CC|FP_D,	0,		I5_33,		0,	0 },
+{"c.eq.ps",		"M,S,T",	0x46c00032, 0xffe000ff,	RD_2|RD_3|WR_CC|FP_D,	0,		I5_33,		0,	I37 },
 {"c.eq.qh",		"Y,Q",		0x78200001, 0xfc2007ff,	RD_1|RD_2|WR_CC|FP_D,	0,		0,		MX,	0 },
-{"c.ueq.d",		"S,T",		0x46200033, 0xffe007ff,	RD_1|RD_2|WR_CC|FP_D,	0,		I1,		0,	SF },
-{"c.ueq.d",		"M,S,T",	0x46200033, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D,   0,		I4_32,		0,	0 },
-{"c.ueq.s",		"S,T",		0x46000033, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S,   0,		I1,		0,	EE },
-{"c.ueq.s",		"M,S,T",	0x46000033, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S,   0,		I4_32,		0,	0 },
-{"c.ueq.ps",		"S,T",		0x46c00033, 0xffe007ff,	RD_1|RD_2|WR_CC|FP_D,	0,		I5_33|IL2F,	0,	0 },
+{"c.ueq.d",		"S,T",		0x46200033, 0xffe007ff,	RD_1|RD_2|WR_CC|FP_D,	0,		I1,		0,	SF|I37 },
+{"c.ueq.d",		"M,S,T",	0x46200033, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D,   0,		I4_32,		0,	I37 },
+{"c.ueq.s",		"S,T",		0x46000033, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S,   0,		I1,		0,	EE|I37 },
+{"c.ueq.s",		"M,S,T",	0x46000033, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S,   0,		I4_32,		0,	I37 },
+{"c.ueq.ps",		"S,T",		0x46c00033, 0xffe007ff,	RD_1|RD_2|WR_CC|FP_D,	0,		I5_33|IL2F,	0,	I37 },
 {"c.ueq.ps",		"S,T",		0x45600033, 0xffe007ff,	RD_1|RD_2|WR_CC|FP_D,	0,		IL2E,		0,	0 },
-{"c.ueq.ps",		"M,S,T",	0x46c00033, 0xffe000ff,	RD_2|RD_3|WR_CC|FP_D,	0,		I5_33,		0,	0 },
-{"c.olt.d",		"S,T",		0x46200034, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,		I1,		0,	SF },
-{"c.olt.d",		"M,S,T",	0x46200034, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D,   0,		I4_32,		0,	0 },
-{"c.olt.s",		"S,T",		0x46000034, 0xffe007ff,	RD_1|RD_2|WR_CC|FP_S,	0,		I1,		0,	EE },
-{"c.olt.s",		"M,S,T",	0x46000034, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S,   0,		I4_32,		0,	0 },
-{"c.olt.ps",		"S,T",		0x46c00034, 0xffe007ff,	RD_1|RD_2|WR_CC|FP_D,	0,		I5_33|IL2F,	0,	0 },
+{"c.ueq.ps",		"M,S,T",	0x46c00033, 0xffe000ff,	RD_2|RD_3|WR_CC|FP_D,	0,		I5_33,		0,	I37 },
+{"c.olt.d",		"S,T",		0x46200034, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,		I1,		0,	SF|I37 },
+{"c.olt.d",		"M,S,T",	0x46200034, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D,   0,		I4_32,		0,	I37 },
+{"c.olt.s",		"S,T",		0x46000034, 0xffe007ff,	RD_1|RD_2|WR_CC|FP_S,	0,		I1,		0,	EE|I37 },
+{"c.olt.s",		"M,S,T",	0x46000034, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S,   0,		I4_32,		0,	I37 },
+{"c.olt.ps",		"S,T",		0x46c00034, 0xffe007ff,	RD_1|RD_2|WR_CC|FP_D,	0,		I5_33|IL2F,	0,	I37 },
 {"c.olt.ps",		"S,T",		0x45600034, 0xffe007ff,	RD_1|RD_2|WR_CC|FP_D,	0,		IL2E,		0,	0 },
-{"c.olt.ps",		"M,S,T",	0x46c00034, 0xffe000ff,	RD_2|RD_3|WR_CC|FP_D,	0,		I5_33,		0,	0 },
-{"c.ult.d",		"S,T",		0x46200035, 0xffe007ff,	RD_1|RD_2|WR_CC|FP_D,	0,		I1,		0,	SF },
-{"c.ult.d",		"M,S,T",	0x46200035, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D,   0,		I4_32,		0,	0 },
-{"c.ult.s",		"S,T",		0x46000035, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S,   0,		I1,		0,	EE },
-{"c.ult.s",		"M,S,T",	0x46000035, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S,   0,		I4_32,		0,	0 },
-{"c.ult.ps",		"S,T",		0x46c00035, 0xffe007ff,	RD_1|RD_2|WR_CC|FP_D,	0,		I5_33|IL2F,	0,	0 },
+{"c.olt.ps",		"M,S,T",	0x46c00034, 0xffe000ff,	RD_2|RD_3|WR_CC|FP_D,	0,		I5_33,		0,	I37 },
+{"c.ult.d",		"S,T",		0x46200035, 0xffe007ff,	RD_1|RD_2|WR_CC|FP_D,	0,		I1,		0,	SF|I37 },
+{"c.ult.d",		"M,S,T",	0x46200035, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D,   0,		I4_32,		0,	I37 },
+{"c.ult.s",		"S,T",		0x46000035, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S,   0,		I1,		0,	EE|I37 },
+{"c.ult.s",		"M,S,T",	0x46000035, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S,   0,		I4_32,		0,	I37 },
+{"c.ult.ps",		"S,T",		0x46c00035, 0xffe007ff,	RD_1|RD_2|WR_CC|FP_D,	0,		I5_33|IL2F,	0,	I37 },
 {"c.ult.ps",		"S,T",		0x45600035, 0xffe007ff,	RD_1|RD_2|WR_CC|FP_D,	0,		IL2E,		0,	0 },
-{"c.ult.ps",		"M,S,T",	0x46c00035, 0xffe000ff,	RD_2|RD_3|WR_CC|FP_D,	0,		I5_33,		0,	0 },
-{"c.ole.d",		"S,T",		0x46200036, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,		I1,		0,	SF },
-{"c.ole.d",		"M,S,T",	0x46200036, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D,   0,		I4_32,		0,	0 },
-{"c.ole.s",		"S,T",		0x46000036, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S,   0,		I1,		0,	EE },
-{"c.ole.s",		"M,S,T",	0x46000036, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S,   0,		I4_32,		0,	0 },
-{"c.ole.ps",		"S,T",		0x46c00036, 0xffe007ff,	RD_1|RD_2|WR_CC|FP_D,	0,		I5_33|IL2F,	0,	0 },
+{"c.ult.ps",		"M,S,T",	0x46c00035, 0xffe000ff,	RD_2|RD_3|WR_CC|FP_D,	0,		I5_33,		0,	I37 },
+{"c.ole.d",		"S,T",		0x46200036, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,		I1,		0,	SF|I37 },
+{"c.ole.d",		"M,S,T",	0x46200036, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D,   0,		I4_32,		0,	I37 },
+{"c.ole.s",		"S,T",		0x46000036, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S,   0,		I1,		0,	EE|I37 },
+{"c.ole.s",		"M,S,T",	0x46000036, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S,   0,		I4_32,		0,	I37 },
+{"c.ole.ps",		"S,T",		0x46c00036, 0xffe007ff,	RD_1|RD_2|WR_CC|FP_D,	0,		I5_33|IL2F,	0,	I37 },
 {"c.ole.ps",		"S,T",		0x45600036, 0xffe007ff,	RD_1|RD_2|WR_CC|FP_D,	0,		IL2E,		0,	0 },
-{"c.ole.ps",		"M,S,T",	0x46c00036, 0xffe000ff,	RD_2|RD_3|WR_CC|FP_D,	0,		I5_33,		0,	0 },
-{"c.ule.d",		"S,T",		0x46200037, 0xffe007ff,	RD_1|RD_2|WR_CC|FP_D,	0,		I1,		0,	SF },
-{"c.ule.d",		"M,S,T",	0x46200037, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D,   0,		I4_32,		0,	0 },
-{"c.ule.s",		"S,T",		0x46000037, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S,   0,		I1,		0,	EE },
-{"c.ule.s",		"M,S,T",	0x46000037, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S,   0,		I4_32,		0,	0 },
-{"c.ule.ps",		"S,T",		0x46c00037, 0xffe007ff,	RD_1|RD_2|WR_CC|FP_D,	0,		I5_33|IL2F,	0,	0 },
+{"c.ole.ps",		"M,S,T",	0x46c00036, 0xffe000ff,	RD_2|RD_3|WR_CC|FP_D,	0,		I5_33,		0,	I37 },
+{"c.ule.d",		"S,T",		0x46200037, 0xffe007ff,	RD_1|RD_2|WR_CC|FP_D,	0,		I1,		0,	SF|I37 },
+{"c.ule.d",		"M,S,T",	0x46200037, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D,   0,		I4_32,		0,	I37 },
+{"c.ule.s",		"S,T",		0x46000037, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S,   0,		I1,		0,	EE|I37 },
+{"c.ule.s",		"M,S,T",	0x46000037, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S,   0,		I4_32,		0,	I37 },
+{"c.ule.ps",		"S,T",		0x46c00037, 0xffe007ff,	RD_1|RD_2|WR_CC|FP_D,	0,		I5_33|IL2F,	0,	I37 },
 {"c.ule.ps",		"S,T",		0x45600037, 0xffe007ff,	RD_1|RD_2|WR_CC|FP_D,	0,		IL2E,		0,	0 },
-{"c.ule.ps",		"M,S,T",	0x46c00037, 0xffe000ff,	RD_2|RD_3|WR_CC|FP_D,	0,		I5_33,		0,	0 },
-{"c.sf.d",		"S,T",		0x46200038, 0xffe007ff,	RD_1|RD_2|WR_CC|FP_D,	0,		I1,		0,	SF },
-{"c.sf.d",		"M,S,T",	0x46200038, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D,   0,		I4_32,		0,	0 },
-{"c.sf.s",		"S,T",		0x46000038, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S,   0,		I1,		0,	EE },
-{"c.sf.s",		"M,S,T",	0x46000038, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S,   0,		I4_32,		0,	0 },
-{"c.sf.ps",		"S,T",		0x46c00038, 0xffe007ff,	RD_1|RD_2|WR_CC|FP_D,	0,		I5_33|IL2F,	0,	0 },
+{"c.ule.ps",		"M,S,T",	0x46c00037, 0xffe000ff,	RD_2|RD_3|WR_CC|FP_D,	0,		I5_33,		0,	I37 },
+{"c.sf.d",		"S,T",		0x46200038, 0xffe007ff,	RD_1|RD_2|WR_CC|FP_D,	0,		I1,		0,	SF|I37 },
+{"c.sf.d",		"M,S,T",	0x46200038, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D,   0,		I4_32,		0,	I37 },
+{"c.sf.s",		"S,T",		0x46000038, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S,   0,		I1,		0,	EE|I37 },
+{"c.sf.s",		"M,S,T",	0x46000038, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S,   0,		I4_32,		0,	I37 },
+{"c.sf.ps",		"S,T",		0x46c00038, 0xffe007ff,	RD_1|RD_2|WR_CC|FP_D,	0,		I5_33|IL2F,	0,	I37 },
 {"c.sf.ps",		"S,T",		0x45600038, 0xffe007ff,	RD_1|RD_2|WR_CC|FP_D,	0,		IL2E,		0,	0 },
-{"c.sf.ps",		"M,S,T",	0x46c00038, 0xffe000ff,	RD_2|RD_3|WR_CC|FP_D,	0,		I5_33,		0,	0 },
-{"c.ngle.d",		"S,T",		0x46200039, 0xffe007ff,	RD_1|RD_2|WR_CC|FP_D,	0,		I1,		0,	SF },
-{"c.ngle.d",		"M,S,T",	0x46200039, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D,   0,		I4_32,		0,	0 },
-{"c.ngle.s",		"S,T",		0x46000039, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S,   0,		I1,		0,	EE },
-{"c.ngle.s",		"M,S,T",	0x46000039, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S,   0,		I4_32,		0,	0 },
-{"c.ngle.ps",		"S,T",		0x46c00039, 0xffe007ff,	RD_1|RD_2|WR_CC|FP_D,	0,		I5_33|IL2F,	0,	0 },
+{"c.sf.ps",		"M,S,T",	0x46c00038, 0xffe000ff,	RD_2|RD_3|WR_CC|FP_D,	0,		I5_33,		0,	I37 },
+{"c.ngle.d",		"S,T",		0x46200039, 0xffe007ff,	RD_1|RD_2|WR_CC|FP_D,	0,		I1,		0,	SF|I37 },
+{"c.ngle.d",		"M,S,T",	0x46200039, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D,   0,		I4_32,		0,	I37 },
+{"c.ngle.s",		"S,T",		0x46000039, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S,   0,		I1,		0,	EE|I37 },
+{"c.ngle.s",		"M,S,T",	0x46000039, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S,   0,		I4_32,		0,	I37 },
+{"c.ngle.ps",		"S,T",		0x46c00039, 0xffe007ff,	RD_1|RD_2|WR_CC|FP_D,	0,		I5_33|IL2F,	0,	I37 },
 {"c.ngle.ps",		"S,T",		0x45600039, 0xffe007ff,	RD_1|RD_2|WR_CC|FP_D,	0,		IL2E,		0,	0 },
-{"c.ngle.ps",		"M,S,T",	0x46c00039, 0xffe000ff,	RD_2|RD_3|WR_CC|FP_D,	0,		I5_33,		0,	0 },
-{"c.seq.d",		"S,T",		0x4620003a, 0xffe007ff,	RD_1|RD_2|WR_CC|FP_D,	0,		I1,		0,	SF },
-{"c.seq.d",		"M,S,T",	0x4620003a, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D,   0,		I4_32,		0,	0 },
-{"c.seq.s",		"S,T",		0x4600003a, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S,   0,		I1,		0,	EE },
-{"c.seq.s",		"M,S,T",	0x4600003a, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S,   0,		I4_32,		0,	0 },
-{"c.seq.ps",		"S,T",		0x46c0003a, 0xffe007ff,	RD_1|RD_2|WR_CC|FP_D,	0,		I5_33|IL2F,	0,	0 },
+{"c.ngle.ps",		"M,S,T",	0x46c00039, 0xffe000ff,	RD_2|RD_3|WR_CC|FP_D,	0,		I5_33,		0,	I37 },
+{"c.seq.d",		"S,T",		0x4620003a, 0xffe007ff,	RD_1|RD_2|WR_CC|FP_D,	0,		I1,		0,	SF|I37 },
+{"c.seq.d",		"M,S,T",	0x4620003a, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D,   0,		I4_32,		0,	I37 },
+{"c.seq.s",		"S,T",		0x4600003a, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S,   0,		I1,		0,	EE|I37 },
+{"c.seq.s",		"M,S,T",	0x4600003a, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S,   0,		I4_32,		0,	I37 },
+{"c.seq.ps",		"S,T",		0x46c0003a, 0xffe007ff,	RD_1|RD_2|WR_CC|FP_D,	0,		I5_33|IL2F,	0,	I37 },
 {"c.seq.ps",		"S,T",		0x4560003a, 0xffe007ff,	RD_1|RD_2|WR_CC|FP_D,	0,		IL2E,		0,	0 },
-{"c.seq.ps",		"M,S,T",	0x46c0003a, 0xffe000ff,	RD_2|RD_3|WR_CC|FP_D,	0,		I5_33,		0,	0 },
-{"c.ngl.d",		"S,T",		0x4620003b, 0xffe007ff,	RD_1|RD_2|WR_CC|FP_D,	0,		I1,		0,	SF },
-{"c.ngl.d",		"M,S,T",	0x4620003b, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D,   0,		I4_32,		0,	0 },
-{"c.ngl.s",		"S,T",		0x4600003b, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S,   0,		I1,		0,	EE },
-{"c.ngl.s",		"M,S,T",	0x4600003b, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S,   0,		I4_32,		0,	0 },
-{"c.ngl.ps",		"S,T",		0x46c0003b, 0xffe007ff,	RD_1|RD_2|WR_CC|FP_D,	0,		I5_33|IL2F,	0,	0 },
+{"c.seq.ps",		"M,S,T",	0x46c0003a, 0xffe000ff,	RD_2|RD_3|WR_CC|FP_D,	0,		I5_33,		0,	I37 },
+{"c.ngl.d",		"S,T",		0x4620003b, 0xffe007ff,	RD_1|RD_2|WR_CC|FP_D,	0,		I1,		0,	SF|I37 },
+{"c.ngl.d",		"M,S,T",	0x4620003b, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D,   0,		I4_32,		0,	I37 },
+{"c.ngl.s",		"S,T",		0x4600003b, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S,   0,		I1,		0,	EE|I37 },
+{"c.ngl.s",		"M,S,T",	0x4600003b, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S,   0,		I4_32,		0,	I37 },
+{"c.ngl.ps",		"S,T",		0x46c0003b, 0xffe007ff,	RD_1|RD_2|WR_CC|FP_D,	0,		I5_33|IL2F,	0,	I37 },
 {"c.ngl.ps",		"S,T",		0x4560003b, 0xffe007ff,	RD_1|RD_2|WR_CC|FP_D,	0,		IL2E,		0,	0 },
-{"c.ngl.ps",		"M,S,T",	0x46c0003b, 0xffe000ff,	RD_2|RD_3|WR_CC|FP_D,	0,		I5_33,		0,	0 },
-{"c.lt.d",		"S,T",		0x4620003c, 0xffe007ff,	RD_1|RD_2|WR_CC|FP_D,	0,		I1,		0,	SF },
-{"c.lt.d",		"M,S,T",	0x4620003c, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D,   0,		I4_32,		0,	0 },
+{"c.ngl.ps",		"M,S,T",	0x46c0003b, 0xffe000ff,	RD_2|RD_3|WR_CC|FP_D,	0,		I5_33,		0,	I37 },
+{"c.lt.d",		"S,T",		0x4620003c, 0xffe007ff,	RD_1|RD_2|WR_CC|FP_D,	0,		I1,		0,	SF|I37 },
+{"c.lt.d",		"M,S,T",	0x4620003c, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D,   0,		I4_32,		0,	I37 },
 {"c.lt.s",		"S,T",		0x46000034, 0xffe007ff,	RD_1|RD_2|WR_CC|FP_S,	0,		EE,		0,	0 },
-{"c.lt.s",		"S,T",		0x4600003c, 0xffe007ff,	RD_1|RD_2|WR_CC|FP_S,	0,		I1,		0,	EE },
-{"c.lt.s",		"M,S,T",	0x4600003c, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S,   0,		I4_32,		0,	0 },
+{"c.lt.s",		"S,T",		0x4600003c, 0xffe007ff,	RD_1|RD_2|WR_CC|FP_S,	0,		I1,		0,	EE|I37 },
+{"c.lt.s",		"M,S,T",	0x4600003c, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S,   0,		I4_32,		0,	I37 },
 {"c.lt.ob",		"Y,Q",		0x78000004, 0xfc2007ff,	RD_1|RD_2|WR_CC|FP_D,	0,		SB1,		MX,	0 },
 {"c.lt.ob",		"S,Q",		0x48000004, 0xfc2007ff,	RD_1|RD_2|WR_CC|FP_D,	0,		N54,		0,	0 },
-{"c.lt.ps",		"S,T",		0x46c0003c, 0xffe007ff,	RD_1|RD_2|WR_CC|FP_D,	0,		I5_33|IL2F,	0,	0 },
+{"c.lt.ps",		"S,T",		0x46c0003c, 0xffe007ff,	RD_1|RD_2|WR_CC|FP_D,	0,		I5_33|IL2F,	0,	I37 },
 {"c.lt.ps",		"S,T",		0x4560003c, 0xffe007ff,	RD_1|RD_2|WR_CC|FP_D,	0,		IL2E,		0,	0 },
-{"c.lt.ps",		"M,S,T",	0x46c0003c, 0xffe000ff,	RD_2|RD_3|WR_CC|FP_D,	0,		I5_33,		0,	0 },
+{"c.lt.ps",		"M,S,T",	0x46c0003c, 0xffe000ff,	RD_2|RD_3|WR_CC|FP_D,	0,		I5_33,		0,	I37 },
 {"c.lt.qh",		"Y,Q",		0x78200004, 0xfc2007ff,	RD_1|RD_2|WR_CC|FP_D,	0,		0,		MX,	0 },
-{"c.nge.d",		"S,T",		0x4620003d, 0xffe007ff,	RD_1|RD_2|WR_CC|FP_D,	0,		I1,		0,	SF },
-{"c.nge.d",		"M,S,T",	0x4620003d, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D,   0,		I4_32,		0,	0 },
-{"c.nge.s",		"S,T",		0x4600003d, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S,   0,		I1,		0,	EE },
-{"c.nge.s",		"M,S,T",	0x4600003d, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S,   0,		I4_32,		0,	0 },
-{"c.nge.ps",		"S,T",		0x46c0003d, 0xffe007ff,	RD_1|RD_2|WR_CC|FP_D,	0,		I5_33|IL2F,	0,	0 },
+{"c.nge.d",		"S,T",		0x4620003d, 0xffe007ff,	RD_1|RD_2|WR_CC|FP_D,	0,		I1,		0,	SF|I37 },
+{"c.nge.d",		"M,S,T",	0x4620003d, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D,   0,		I4_32,		0,	I37 },
+{"c.nge.s",		"S,T",		0x4600003d, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S,   0,		I1,		0,	EE|I37 },
+{"c.nge.s",		"M,S,T",	0x4600003d, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S,   0,		I4_32,		0,	I37 },
+{"c.nge.ps",		"S,T",		0x46c0003d, 0xffe007ff,	RD_1|RD_2|WR_CC|FP_D,	0,		I5_33|IL2F,	0,	I37 },
 {"c.nge.ps",		"S,T",		0x4560003d, 0xffe007ff,	RD_1|RD_2|WR_CC|FP_D,	0,		IL2E,		0,	0 },
-{"c.nge.ps",		"M,S,T",	0x46c0003d, 0xffe000ff,	RD_2|RD_3|WR_CC|FP_D,	0,		I5_33,		0,	0 },
-{"c.le.d",		"S,T",		0x4620003e, 0xffe007ff,	RD_1|RD_2|WR_CC|FP_D,	0,		I1,		0,	SF },
-{"c.le.d",		"M,S,T",	0x4620003e, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D,   0,		I4_32,		0,	0 },
+{"c.nge.ps",		"M,S,T",	0x46c0003d, 0xffe000ff,	RD_2|RD_3|WR_CC|FP_D,	0,		I5_33,		0,	I37 },
+{"c.le.d",		"S,T",		0x4620003e, 0xffe007ff,	RD_1|RD_2|WR_CC|FP_D,	0,		I1,		0,	SF|I37 },
+{"c.le.d",		"M,S,T",	0x4620003e, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D,   0,		I4_32,		0,	I37 },
 {"c.le.s",		"S,T",		0x46000036, 0xffe007ff,	RD_1|RD_2|WR_CC|FP_S,	0,		EE,		0,	0 },
-{"c.le.s",		"S,T",		0x4600003e, 0xffe007ff,	RD_1|RD_2|WR_CC|FP_S,	0,		I1,		0,	EE },
-{"c.le.s",		"M,S,T",	0x4600003e, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S,   0,		I4_32,		0,	0 },
+{"c.le.s",		"S,T",		0x4600003e, 0xffe007ff,	RD_1|RD_2|WR_CC|FP_S,	0,		I1,		0,	EE|I37 },
+{"c.le.s",		"M,S,T",	0x4600003e, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S,   0,		I4_32,		0,	I37 },
 {"c.le.ob",		"Y,Q",		0x78000005, 0xfc2007ff,	RD_1|RD_2|WR_CC|FP_D,	0,		SB1,		MX,	0 },
 {"c.le.ob",		"S,Q",		0x48000005, 0xfc2007ff,	RD_1|RD_2|WR_CC|FP_D,	0,		N54,		0,	0 },
-{"c.le.ps",		"S,T",		0x46c0003e, 0xffe007ff,	RD_1|RD_2|WR_CC|FP_D,	0,		I5_33|IL2F,	0,	0 },
+{"c.le.ps",		"S,T",		0x46c0003e, 0xffe007ff,	RD_1|RD_2|WR_CC|FP_D,	0,		I5_33|IL2F,	0,	I37 },
 {"c.le.ps",		"S,T",		0x4560003e, 0xffe007ff,	RD_1|RD_2|WR_CC|FP_D,	0,		IL2E,		0,	0 },
-{"c.le.ps",		"M,S,T",	0x46c0003e, 0xffe000ff,	RD_2|RD_3|WR_CC|FP_D,	0,		I5_33,		0,	0 },
+{"c.le.ps",		"M,S,T",	0x46c0003e, 0xffe000ff,	RD_2|RD_3|WR_CC|FP_D,	0,		I5_33,		0,	I37 },
 {"c.le.qh",		"Y,Q",		0x78200005, 0xfc2007ff,	RD_1|RD_2|WR_CC|FP_D,	0,		0,		MX,	0 },
-{"c.ngt.d",		"S,T",		0x4620003f, 0xffe007ff,	RD_1|RD_2|WR_CC|FP_D,	0,		I1,		0,	SF },
-{"c.ngt.d",		"M,S,T",	0x4620003f, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D,   0,		I4_32,		0,	0 },
-{"c.ngt.s",		"S,T",		0x4600003f, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S,   0,		I1,		0,	EE },
-{"c.ngt.s",		"M,S,T",	0x4600003f, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S,   0,		I4_32,		0,	0 },
-{"c.ngt.ps",		"S,T",		0x46c0003f, 0xffe007ff,	RD_1|RD_2|WR_CC|FP_D,	0,		I5_33|IL2F,	0,	0 },
+{"c.ngt.d",		"S,T",		0x4620003f, 0xffe007ff,	RD_1|RD_2|WR_CC|FP_D,	0,		I1,		0,	SF|I37 },
+{"c.ngt.d",		"M,S,T",	0x4620003f, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D,   0,		I4_32,		0,	I37 },
+{"c.ngt.s",		"S,T",		0x4600003f, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S,   0,		I1,		0,	EE|I37 },
+{"c.ngt.s",		"M,S,T",	0x4600003f, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S,   0,		I4_32,		0,	I37 },
+{"c.ngt.ps",		"S,T",		0x46c0003f, 0xffe007ff,	RD_1|RD_2|WR_CC|FP_D,	0,		I5_33|IL2F,	0,	I37 },
 {"c.ngt.ps",		"S,T",		0x4560003f, 0xffe007ff,	RD_1|RD_2|WR_CC|FP_D,	0,		IL2E,		0,	0 },
-{"c.ngt.ps",		"M,S,T",	0x46c0003f, 0xffe000ff,	RD_2|RD_3|WR_CC|FP_D,	0,		I5_33,		0,	0 },
+{"c.ngt.ps",		"M,S,T",	0x46c0003f, 0xffe000ff,	RD_2|RD_3|WR_CC|FP_D,	0,		I5_33,		0,	I37 },
 {"cabs.eq.d",		"M,S,T",	0x46200072, 0xffe000ff,	RD_2|RD_3|WR_CC|FP_D,	0,		0,		M3D,	0 },
 {"cabs.eq.ps",		"M,S,T",	0x46c00072, 0xffe000ff,	RD_2|RD_3|WR_CC|FP_D,	0,		0,		M3D,	0 },
 {"cabs.eq.s",		"M,S,T",	0x46000072, 0xffe000ff,	RD_2|RD_3|WR_CC|FP_S,	0,		0,		M3D,	0 },
@@ -894,8 +934,9 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"flushd",		"",		0xbc020000, 0xffffffff, 0, 			0,		L1,		0,	0 },
 {"flushid",		"",		0xbc030000, 0xffffffff, 0, 			0,		L1,		0,	0 },
 {"wb",			"o(b)",		0xbc040000, 0xfc1f0000, RD_2|SM,		0,		L1,		0,	0 },
-{"cache",		"k,o(b)",	0xbc000000, 0xfc000000, RD_3,           	0,		I3_32|T3,	0,	0},
-{"cache",		"k,A(b)",	0,    (int) M_CACHE_AB, INSN_MACRO,		0,		I3_32|T3,	0,	0},
+{"cache",		"k,+j(b)",	0x7c000025, 0xfc00007f, RD_3,			0,		I37,		0,	0 },
+{"cache",		"k,o(b)",	0xbc000000, 0xfc000000, RD_3,           	0,		I3_32|T3,	0,	I37 },
+{"cache",		"k,A(b)",	0,    (int) M_CACHE_AB, INSN_MACRO,		0,		I3_32|T3,	0,	0 },
 {"ceil.l.d",		"D,S",		0x4620000a, 0xffff003f, WR_1|RD_2|FP_D,		0,		I3_33,		0,	0 },
 {"ceil.l.s",		"D,S",		0x4600000a, 0xffff003f, WR_1|RD_2|FP_S|FP_D,	0,		I3_33,		0,	0 },
 {"ceil.w.d",		"D,S",		0x4620000e, 0xffff003f, WR_1|RD_2|FP_S|FP_D,	0,		I2,		0,	SF },
@@ -911,8 +952,10 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"cins32",		"t,r,+p,+s",	0x70000033, 0xfc00003f, WR_1|RD_2,		0,		IOCT,		0,	0 },
 {"cins",		"t,r,+P,+S",	0x70000033, 0xfc00003f, WR_1|RD_2,		0,		IOCT,		0,	0 }, /* cins32 */
 {"cins",		"t,r,+p,+S",	0x70000032, 0xfc00003f, WR_1|RD_2,		0,		IOCT,		0,	0 },
-{"clo",			"U,s",		0x70000021, 0xfc0007ff, WR_1|RD_2, 	0,		I32|N55,	0,	0 },
-{"clz",			"U,s",		0x70000020, 0xfc0007ff, WR_1|RD_2, 	0,		I32|N55,	0,	0 },
+{"clo",			"d,s",		0x00000051, 0xfc1f07ff, WR_1|RD_2,		0,		I37,		0,	0 },
+{"clo",			"U,s",		0x70000021, 0xfc0007ff, WR_1|RD_2,		0,		I32|N55,	0,	I37 },
+{"clz",			"d,s",		0x00000050, 0xfc1f07ff, WR_1|RD_2,		0,		I37,		0,	0 },
+{"clz",			"U,s",		0x70000020, 0xfc0007ff, WR_1|RD_2,		0,		I32|N55,	0,	I37 },
 /* ctc0 is at the bottom of the table.  */
 {"ctc1",		"t,G",		0x44c00000, 0xffe007ff,	RD_1|WR_CC|CM,		0,		I1,		0,	0 },
 {"ctc1",		"t,S",		0x44c00000, 0xffe007ff,	RD_1|WR_CC|CM,		0,		I1,		0,	0 },
@@ -934,21 +977,23 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"cvt.w.d",		"D,S",		0x46200024, 0xffff003f,	WR_1|RD_2|FP_S|FP_D,	0,		I1,		0,	SF },
 {"cvt.w.s",		"D,S",		0x46000024, 0xffff003f,	WR_1|RD_2|FP_S,		0,		I1,		0,	EE },
 {"cvt.ps.pw",		"D,S",		0x46800026, 0xffff003f,	WR_1|RD_2|FP_S|FP_D,	0,		0,		M3D,	0 },
-{"cvt.ps.s",		"D,V,T",	0x46000026, 0xffe0003f,	WR_1|RD_2|RD_3|FP_S|FP_D, 0,		I5_33,		0,	0 },
+{"cvt.ps.s",		"D,V,T",	0x46000026, 0xffe0003f,	WR_1|RD_2|RD_3|FP_S|FP_D, 0,		I5_33,		0,	I37 },
 {"cvt.pw.ps",		"D,S",		0x46c00024, 0xffff003f,	WR_1|RD_2|FP_S|FP_D,	0,		0,		M3D,	0 },
 {"dabs",		"d,v",		0,    (int) M_DABS,	INSN_MACRO,		0,		I3,		0,	0 },
 {"dadd",		"d,v,t",	0x0000002c, 0xfc0007ff, WR_1|RD_2|RD_3,		0,		I3,		0,	0 },
-{"dadd",		"t,r,I",	0,    (int) M_DADD_I,	INSN_MACRO,		0,		I3,		0,	0 },
+{"dadd",		"t,r,I",	0,    (int) M_DADD_I,	INSN_MACRO,		0,		I3,		0,	I69 },
 {"dadd",		"D,S,T",	0x45e00000, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2E,		0,	0 },
 {"dadd",		"D,S,T",	0x4b60000c, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2F|IL3A,	0,	0 },
-{"daddi",		"t,r,j",	0x60000000, 0xfc000000, WR_1|RD_2,		0,		I3,		0,	0 },
+{"daddi",		"t,r,j",	0x60000000, 0xfc000000, WR_1|RD_2,		0,		I3,		0,	I69 },
 {"daddiu",		"t,r,j",	0x64000000, 0xfc000000, WR_1|RD_2,		0,		I3,		0,	0 },
 {"daddu",		"d,v,t",	0x0000002d, 0xfc0007ff, WR_1|RD_2|RD_3,		0,		I3,		0,	0 },
 {"daddu",		"t,r,I",	0,    (int) M_DADDU_I,	INSN_MACRO,		0,		I3,		0,	0 },
 {"daddwc",		"d,s,t", 	0x70000038, 0xfc0007ff, WR_1|RD_2|RD_3|WR_C0|RD_C0, 0,		XLR,		0,	0 },
 {"dbreak",		"",		0x7000003f, 0xffffffff,	0,			0,		N5,		0,	0 },
-{"dclo",		"U,s",	 	0x70000025, 0xfc0007ff, WR_1|RD_2, 	0,		I64|N55,	0,	0 },
-{"dclz",		"U,s",	 	0x70000024, 0xfc0007ff, WR_1|RD_2, 	0,		I64|N55,	0,	0 },
+{"dclo",		"d,s",		0x00000053, 0xfc1f07ff, WR_1|RD_2,		0,		I69,		0,	0 },
+{"dclo",		"U,s",	 	0x70000025, 0xfc0007ff, WR_1|RD_2, 	0,		I64|N55,	0,	I69 },
+{"dclz",		"d,s",		0x00000052, 0xfc1f07ff, WR_1|RD_2,		0,		I69,		0,	0 },
+{"dclz",		"U,s",	 	0x70000024, 0xfc0007ff, WR_1|RD_2, 	0,		I64|N55,	0,	I69 },
 /* dctr and dctw are used on the r5000.  */
 {"dctr",		"o(b)",	 	0xbc050000, 0xfc1f0000, RD_2,			0,		I3,		0,	0 },
 {"dctw",		"o(b)",		0xbc090000, 0xfc1f0000, RD_2,			0,		I3,		0,	0 },
@@ -959,13 +1004,17 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"dextm",		"t,r,+A,+G",	0x7c000001, 0xfc00003f, WR_1|RD_2,    		0,		I65,		0,	0 },
 {"dextu",		"t,r,+E,+H",	0x7c000002, 0xfc00003f, WR_1|RD_2,    		0,		I65,		0,	0 },
 /* For ddiv, see the comments about div.  */
-{"ddiv",		"z,s,t",	0x0000001e, 0xfc00ffff, RD_2|RD_3|WR_HILO,      0,		I3,		0,	M32 },
-{"ddiv",		"d,v,t",	0,    (int) M_DDIV_3,	INSN_MACRO,		0,		I3,		0,	M32 },
-{"ddiv",		"d,v,I",	0,    (int) M_DDIV_3I,	INSN_MACRO,		0,		I3,		0,	M32 },
+{"dmod",		"d,s,t",	0x000000de, 0xfc0007ff, WR_1|RD_2|RD_3,		0,		I69,		0,	0 },
+{"ddiv",		"d,s,t",	0x0000009e, 0xfc0007ff, WR_1|RD_2|RD_3,		0,		I69,		0,	0 },
+{"ddiv",		"z,s,t",	0x0000001e, 0xfc00ffff, RD_2|RD_3|WR_HILO,      0,		I3,		0,	M32|I69 },
+{"ddiv",		"d,v,t",	0,    (int) M_DDIV_3,	INSN_MACRO,		0,		I3,		0,	M32|I69 },
+{"ddiv",		"d,v,I",	0,    (int) M_DDIV_3I,	INSN_MACRO,		0,		I3,		0,	M32|I69 },
 /* For ddivu, see the comments about div.  */
-{"ddivu",		"z,s,t",	0x0000001f, 0xfc00ffff, RD_2|RD_3|WR_HILO,      0,		I3,		0,	M32 },
-{"ddivu",		"d,v,t",	0,    (int) M_DDIVU_3,	INSN_MACRO,		0,		I3,		0,	M32 },
-{"ddivu",		"d,v,I",	0,    (int) M_DDIVU_3I,	INSN_MACRO,		0,		I3,		0,	M32 },
+{"dmodu",		"d,s,t",	0x000000df, 0xfc0007ff, WR_1|RD_2|RD_3,		0,		I69,		0,	0 },
+{"ddivu",		"d,s,t",	0x0000009f, 0xfc0007ff, WR_1|RD_2|RD_3,		0,		I69,		0,	0 },
+{"ddivu",		"z,s,t",	0x0000001f, 0xfc00ffff, RD_2|RD_3|WR_HILO,      0,		I3,		0,	M32|I69 },
+{"ddivu",		"d,v,t",	0,    (int) M_DDIVU_3,	INSN_MACRO,		0,		I3,		0,	M32|I69 },
+{"ddivu",		"d,v,I",	0,    (int) M_DDIVU_3I,	INSN_MACRO,		0,		I3,		0,	M32|I69 },
 {"di",			"",		0x42000039, 0xffffffff,	WR_C0,			0,		EE,		0,	0 },
 {"di",			"",		0x41606000, 0xffffffff,	WR_C0,			0,		I33,		0,	0 },
 {"di",			"t",		0x41606000, 0xffe0ffff,	WR_1|WR_C0,		0,		I33,		0,	0 },
@@ -978,20 +1027,24 @@ const struct mips_opcode mips_builtin_opcodes[] =
    though the first operand appeared twice (the first operand is both
    a source and a destination).  To get the div machine instruction,
    you must use an explicit destination of $0.  */
-{"div",			"z,s,t",	0x0000001a, 0xfc00ffff, RD_2|RD_3|WR_HILO,      0,		I1,		0,	0 },
-{"div",			"z,t",		0x0000001a, 0xffe0ffff, RD_2|WR_HILO,		0,		I1,		0,	0 },
-{"div",			"d,v,t",	0,    (int) M_DIV_3,	INSN_MACRO,		0,		I1,		0,	0 },
-{"div",			"d,v,I",	0,    (int) M_DIV_3I,	INSN_MACRO,		0,		I1,		0,	0 },
+{"mod",			"d,v,t",	0x000000da, 0xfc0007ff, WR_1|RD_2|RD_3, 	0,		I37,		0,	0},
+{"modu",		"d,v,t",	0x000000db, 0xfc0007ff, WR_1|RD_2|RD_3, 	0,		I37,		0,	0},
+{"div",			"d,v,t",	0x0000009a, 0xfc0007ff, WR_1|RD_2|RD_3, 	0,		I37,		0,	0},
+{"div",			"z,s,t",	0x0000001a, 0xfc00ffff, RD_2|RD_3|WR_HILO,      0,		I1,		0,	I37 },
+{"div",			"z,t",		0x0000001a, 0xffe0ffff, RD_2|WR_HILO,		0,		I1,		0,	I37 },
+{"div",			"d,v,t",	0,    (int) M_DIV_3,	INSN_MACRO,		0,		I1,		0,	I37 },
+{"div",			"d,v,I",	0,    (int) M_DIV_3I,	INSN_MACRO,		0,		I1,		0,	I37 },
 {"div1",		"z,s,t",	0x7000001a, 0xfc00ffff, RD_2|RD_3|WR_HILO,      0,		EE,		0,	0 },
 {"div1",		"z,t",		0x7000001a, 0xffe0ffff, RD_2|WR_HILO,		0,		EE,		0,	0 },
 {"div.d",		"D,V,T",	0x46200003, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		I1,		0,	SF },
 {"div.s",		"D,V,T",	0x46000003, 0xffe0003f,	WR_1|RD_2|RD_3|FP_S,	0,		I1,		0,	0 },
 {"div.ps",		"D,V,T",	0x46c00003, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		SB1,		0,	0 },
 /* For divu, see the comments about div.  */
-{"divu",		"z,s,t",	0x0000001b, 0xfc00ffff, RD_2|RD_3|WR_HILO,      0,		I1,		0,	0 },
-{"divu",		"z,t",		0x0000001b, 0xffe0ffff, RD_2|WR_HILO,		0,		I1,		0,	0 },
-{"divu",		"d,v,t",	0,    (int) M_DIVU_3,	INSN_MACRO,		0,		I1,		0,	0 },
-{"divu",		"d,v,I",	0,    (int) M_DIVU_3I,	INSN_MACRO,		0,		I1,		0,	0 },
+{"divu",		"d,v,t",	0x0000009b, 0xfc0007ff, WR_1|RD_2|RD_3, 	0,		I37,		0,	0},
+{"divu",		"z,s,t",	0x0000001b, 0xfc00ffff, RD_2|RD_3|WR_HILO,      0,		I1,		0,	I37 },
+{"divu",		"z,t",		0x0000001b, 0xffe0ffff, RD_2|WR_HILO,		0,		I1,		0,	I37 },
+{"divu",		"d,v,t",	0,    (int) M_DIVU_3,	INSN_MACRO,		0,		I1,		0,	I37 },
+{"divu",		"d,v,I",	0,    (int) M_DIVU_3I,	INSN_MACRO,		0,		I1,		0,	I37 },
 {"divu1",		"z,s,t",	0x7000001b, 0xfc00ffff, RD_2|RD_3|WR_HILO,      0,		EE,		0,	0 },
 {"divu1",		"z,t",		0x7000001b, 0xffe0ffff, RD_2|WR_HILO,		0,		EE,		0,	0 },
 {"dla",			"t,A(b)",	0,    (int) M_DLA_AB,	INSN_MACRO,		0,		I3,		0,	0 },
@@ -1026,24 +1079,28 @@ const struct mips_opcode mips_builtin_opcodes[] =
 /* dmtc2 is at the bottom of the table.  */
 /* dmfc3 is at the bottom of the table.  */
 /* dmtc3 is at the bottom of the table.  */
+{"dmuh",		"d,s,t",	0x000000dc, 0xfc0007ff, WR_1|RD_2|RD_3,		0,		I69,		0,	0 },
+{"dmul",		"d,s,t",	0x0000009c, 0xfc0007ff, WR_1|RD_2|RD_3,		0,		I69,		0,	0 },
 {"dmul",		"d,v,t",	0x70000003, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO,	0,		IOCT,		0,	0 },
-{"dmul",		"d,v,t",	0,    (int) M_DMUL,	INSN_MACRO,		0,		I3,		0,	M32 },
-{"dmul",		"d,v,I",	0,    (int) M_DMUL_I,	INSN_MACRO,		0,		I3,		0,	M32 },
-{"dmulo",		"d,v,t",	0,    (int) M_DMULO,	INSN_MACRO,		0,		I3,		0,	M32 },
-{"dmulo",		"d,v,I",	0,    (int) M_DMULO_I,	INSN_MACRO,		0,		I3,		0,	M32 },
-{"dmulou",		"d,v,t",	0,    (int) M_DMULOU,	INSN_MACRO,		0,		I3,		0,	M32 },
-{"dmulou",		"d,v,I",	0,    (int) M_DMULOU_I,	INSN_MACRO,		0,		I3,		0,	M32 },
-{"dmult",		"s,t",		0x0000001c, 0xfc00ffff, RD_1|RD_2|WR_HILO,      0,		I3,		0,	M32 },
-{"dmultu",		"s,t",		0x0000001d, 0xfc00ffff, RD_1|RD_2|WR_HILO,      0,		I3,		0,	M32 },
+{"dmul",		"d,v,t",	0,    (int) M_DMUL,	INSN_MACRO,		0,		I3,		0,	M32|I69 },
+{"dmul",		"d,v,I",	0,    (int) M_DMUL_I,	INSN_MACRO,		0,		I3,		0,	M32|I69 },
+{"dmulo",		"d,v,t",	0,    (int) M_DMULO,	INSN_MACRO,		0,		I3,		0,	M32|I69 },
+{"dmulo",		"d,v,I",	0,    (int) M_DMULO_I,	INSN_MACRO,		0,		I3,		0,	M32|I69 },
+{"dmulou",		"d,v,t",	0,    (int) M_DMULOU,	INSN_MACRO,		0,		I3,		0,	M32|I69 },
+{"dmulou",		"d,v,I",	0,    (int) M_DMULOU_I,	INSN_MACRO,		0,		I3,		0,	M32|I69 },
+{"dmult",		"s,t",		0x0000001c, 0xfc00ffff, RD_1|RD_2|WR_HILO,      0,		I3,		0,	M32|I69 },
+{"dmulu",		"d,s,t",	0x0000009d, 0xfc0007ff, WR_1|RD_2|RD_3,      	0,		I69,		0,	0 },
+{"dmuhu",		"d,s,t",	0x000000dd, 0xfc0007ff, WR_1|RD_2|RD_3,      	0,		I69,		0,	0 },
+{"dmultu",		"s,t",		0x0000001d, 0xfc00ffff, RD_1|RD_2|WR_HILO,      0,		I3,		0,	M32|I69 },
 {"dneg",		"d,w",		0x0000002e, 0xffe007ff,	WR_1|RD_2,		0,		I3,		0,	0 }, /* dsub 0 */
 {"dnegu",		"d,w",		0x0000002f, 0xffe007ff,	WR_1|RD_2,		0,		I3,		0,	0 }, /* dsubu 0*/
 {"dpop",		"d,v",		0x7000002d, 0xfc1f07ff, WR_1|RD_2,		0,		IOCT,		0,	0 },
-{"drem",		"z,s,t",	0x0000001e, 0xfc00ffff, RD_2|RD_3|WR_HILO,      0,		I3,		0,	M32 },
-{"drem",		"d,v,t",	0,    (int) M_DREM_3,	INSN_MACRO,		0,		I3,		0,	M32 },
-{"drem",		"d,v,I",	0,    (int) M_DREM_3I,	INSN_MACRO,		0,		I3,		0,	M32 },
-{"dremu",		"z,s,t",	0x0000001f, 0xfc00ffff, RD_2|RD_3|WR_HILO,      0,		I3,		0,	M32 },
-{"dremu",		"d,v,t",	0,    (int) M_DREMU_3,	INSN_MACRO,		0,		I3,		0,	M32 },
-{"dremu",		"d,v,I",	0,    (int) M_DREMU_3I,	INSN_MACRO,		0,		I3,		0,	M32 },
+{"drem",		"z,s,t",	0x0000001e, 0xfc00ffff, RD_2|RD_3|WR_HILO,      0,		I3,		0,	M32|I69 },
+{"drem",		"d,v,t",	0,    (int) M_DREM_3,	INSN_MACRO,		0,		I3,		0,	M32|I69 },
+{"drem",		"d,v,I",	0,    (int) M_DREM_3I,	INSN_MACRO,		0,		I3,		0,	M32|I69 },
+{"dremu",		"z,s,t",	0x0000001f, 0xfc00ffff, RD_2|RD_3|WR_HILO,      0,		I3,		0,	M32|I69 },
+{"dremu",		"d,v,t",	0,    (int) M_DREMU_3,	INSN_MACRO,		0,		I3,		0,	M32|I69 },
+{"dremu",		"d,v,I",	0,    (int) M_DREMU_3I,	INSN_MACRO,		0,		I3,		0,	M32|I69 },
 {"dret",		"",		0x7000003e, 0xffffffff,	0,			0,		N5,		0,	0 },
 {"drol",		"d,v,t",	0,    (int) M_DROL,	INSN_MACRO,		0,		I3,		0,	0 },
 {"drol",		"d,v,I",	0,    (int) M_DROL_I,	INSN_MACRO,		0,		I3,		0,	0 },
@@ -1082,7 +1139,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"dsrl",		"D,S,T",	0x45a00003, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2E,		0,	0 },
 {"dsrl",		"D,S,T",	0x4b20000f, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2F|IL3A,	0,	0 },
 {"dsub",		"d,v,t",	0x0000002e, 0xfc0007ff,	WR_1|RD_2|RD_3,		0,		I3,		0,	0 },
-{"dsub",		"d,v,I",	0,    (int) M_DSUB_I,	INSN_MACRO,		0,		I3,		0,	0 },
+{"dsub",		"d,v,I",	0,    (int) M_DSUB_I,	INSN_MACRO,		0,		I3,		0,	I69 },
 {"dsub",		"D,S,T",	0x45e00001, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2E,		0,	0 },
 {"dsub",		"D,S,T",	0x4b60000d, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2F|IL3A,	0,	0 },
 {"dsubu",		"d,v,t",	0x0000002f, 0xfc0007ff,	WR_1|RD_2|RD_3,		0,		I3,		0,	0 },
@@ -1111,11 +1168,15 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"hypcall",		"+J",		0x42000028, 0xffe007ff, TRAP,			0,		0,		IVIRT,	0 },
 {"ins",			"t,r,+A,+B",	0x7c000004, 0xfc00003f, WR_1|RD_2,    		0,		I33,		0,	0 },
 {"iret",		"",		0x42000038, 0xffffffff,	NODS,			0,		0,		MC,	0 },
-{"jr",			"s",		0x00000008, 0xfc1fffff,	RD_1|UBD,		0,		I1,		0,	0 },
+{"jr",			"s",		0x00000009, 0xfc1fffff,	RD_1|UBD,		INSN2_ALIAS,	I37,		0,	0 }, /* jalr $0 */
+{"jr",			"s",		0x00000008, 0xfc1fffff,	RD_1|UBD,		0,		I1,		0,	I37 },
+/* MIPS R6 jic appears before beqzc and jialc appears before bnezc */
 /* jr.hb is officially MIPS{32,64}R2, but it works on R1 as jr with
    the same hazard barrier effect.  */
-{"jr.hb",		"s",		0x00000408, 0xfc1fffff,	RD_1|UBD,		0,		I32,		0,	0 },
-{"j",			"s",		0x00000008, 0xfc1fffff,	RD_1|UBD,		0,		I1,		0,	0 }, /* jr */
+{"jr.hb",		"s",		0x00000409, 0xfc1fffff,	RD_1|UBD,		INSN2_ALIAS,	I37,		0,	0 }, /* jalr.hb $0 */
+{"jr.hb",		"s",		0x00000408, 0xfc1fffff,	RD_1|UBD,		0,		I32,		0,	I37 },
+{"j",			"s",		0x00000009, 0xfc1fffff,	RD_1|UBD,		INSN2_ALIAS,	I37,		0,	0 }, /* jalr $0 */
+{"j",			"s",		0x00000008, 0xfc1fffff,	RD_1|UBD,		0,		I1,		0,	I37 }, /* jr */
 /* SVR4 PIC code requires special handling for j, so it must be a
    macro.  */
 {"j",			"a",		0,     (int) M_J_A,	INSN_MACRO,		0,		I1,		0,	0 },
@@ -1138,8 +1199,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
    assembler, but will never match user input (because the line above
    will match first).  */
 {"jal",			"a",		0x0c000000, 0xfc000000,	WR_31|UBD,		0,		I1,		0,	0 },
-{"jalx",		"+i",		0x74000000, 0xfc000000, WR_31|UBD,		0,		I1,		0,	0 },
-{"la",			"t,A(b)",	0,    (int) M_LA_AB,	INSN_MACRO,		0,		I1,		0,	0 },
+{"jalx",		"+i",		0x74000000, 0xfc000000, WR_31|UBD,		0,		I1,		0,	I37 },
 {"laa",			"d,(b),t",	0x7000049f, 0xfc0007ff, WR_1|RD_2|RD_3|LM|SM,	0,		IOCT2,		0,	0 },
 {"laad",		"d,(b),t",	0x700004df, 0xfc0007ff, WR_1|RD_2|RD_3|LM|SM,	0,		IOCT2,		0,	0 },
 {"lac",			"d,(b)",	0x7000039f, 0xfc1f07ff, WR_1|RD_2|LM|SM,	0,		IOCT2,		0,	0 },
@@ -1164,7 +1224,9 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"lwx",			"d,t(b)",	0x7c00000a, 0xfc0007ff, WR_1|RD_2|RD_3|LM,	0,		IOCT2,		D32,	0},
 {"lwux",		"d,t(b)",	0x7c00040a, 0xfc0007ff, WR_1|RD_2|RD_3|LM,	0,		IOCT2,		0,	0 },
 {"lca",			"t,A(b)",	0,    (int) M_LCA_AB,	INSN_MACRO,		0,		I1,		0,	0 },
+{"ldpc",		"s,-B",		0xec180000, 0xfc1c0000, WR_1,			RD_pc,		I69,		0,	0 },
 /* The macro has to be first to handle o32 correctly.  */
+{"ld",			"s,-b(+R)",	0xec180000, 0xfc1c0000, WR_1,			RD_pc,		I69,		0,	0 },
 {"ld",			"t,A(b)",	0,    (int) M_LD_AB,	INSN_MACRO,		0,		I1,		0,	0 },
 {"ld",			"t,o(b)",	0xdc000000, 0xfc000000, WR_1|RD_3|LM,		0,		I3,		0,	0 },
 {"ldaddw",		"t,b",		0x70000010, 0xfc00ffff,	MOD_1|RD_2|LM|SM,	0,		XLR,		0,	0 },
@@ -1176,15 +1238,16 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"ldc1",		"E,A(b)",	0,    (int) M_LDC1_AB,	INSN_MACRO,		INSN2_M_FP_D,	I2,		0,	SF },
 {"l.d",			"T,o(b)",	0xd4000000, 0xfc000000, WR_1|RD_3|CLD|FP_D,	0,		I2,		0,	SF }, /* ldc1 */
 {"l.d",			"T,A(b)",	0,    (int) M_L_DAB,	INSN_MACRO,		INSN2_M_FP_D,	I1,		0,	0 },
-{"ldc2",		"E,o(b)",	0xd8000000, 0xfc000000,	RD_3|WR_CC|CLD,		0,		I2,		0,	IOCT|IOCTP|IOCT2|EE },
+{"ldc2",		"E,+:(d)",	0x49c00000, 0xffe00000,	RD_3|WR_C2|CLD,		0,		I37,		0,	0 },
+{"ldc2",		"E,o(b)",	0xd8000000, 0xfc000000,	RD_3|WR_CC|CLD,		0,		I2,		0,	IOCT|IOCTP|IOCT2|EE|I37 },
 {"ldc2",		"E,A(b)",	0,    (int) M_LDC2_AB,	INSN_MACRO,		0,		I2,		0,	IOCT|IOCTP|IOCT2|EE },
 {"ldc3",		"E,o(b)",	0xdc000000, 0xfc000000,	RD_3|WR_CC|CLD,		0,		I2,		0,	IOCT|IOCTP|IOCT2|EE },
 {"ldc3",		"E,A(b)",	0,    (int) M_LDC3_AB,	INSN_MACRO,		0,		I2,		0,	IOCT|IOCTP|IOCT2|EE },
-{"ldl",			"t,o(b)",	0x68000000, 0xfc000000, WR_1|RD_3|LM,		0,		I3,		0,	0 },
-{"ldl",			"t,A(b)",	0,    (int) M_LDL_AB,	INSN_MACRO,		0,		I3,		0,	0 },
-{"ldr",			"t,o(b)",	0x6c000000, 0xfc000000, WR_1|RD_3|LM,		0,		I3,		0,	0 },
-{"ldr",			"t,A(b)",	0,    (int) M_LDR_AB,	INSN_MACRO,		0,		I3,		0,	0 },
-{"ldxc1",		"D,t(b)",	0x4c000001, 0xfc00f83f, WR_1|RD_2|RD_3|LM|FP_D, 0,		I4_33,		0,	0 },
+{"ldl",			"t,o(b)",	0x68000000, 0xfc000000, WR_1|RD_3|LM,		0,		I3,		0,	I69 },
+{"ldl",			"t,A(b)",	0,    (int) M_LDL_AB,	INSN_MACRO,		0,		I3,		0,	I69 },
+{"ldr",			"t,o(b)",	0x6c000000, 0xfc000000, WR_1|RD_3|LM,		0,		I3,		0,	I69 },
+{"ldr",			"t,A(b)",	0,    (int) M_LDR_AB,	INSN_MACRO,		0,		I3,		0,	I69 },
+{"ldxc1",		"D,t(b)",	0x4c000001, 0xfc00f83f, WR_1|RD_2|RD_3|LM|FP_D, 0,		I4_33,		0,	I37 },
 {"lh",			"t,o(b)",	0x84000000, 0xfc000000,	WR_1|RD_3|LM,		0,		I1,		0,	0 },
 {"lh",			"t,A(b)",	0,    (int) M_LH_AB,	INSN_MACRO,		0,		I1,		0,	0 },
 {"lhu",			"t,o(b)",	0x94000000, 0xfc000000,	WR_1|RD_3|LM,		0,		I1,		0,	0 },
@@ -1194,42 +1257,49 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"li.d",		"T,L",		0,    (int) M_LI_DD,	INSN_MACRO,		INSN2_M_FP_D,	I1,		0,	SF },
 {"li.s",		"t,f",		0,    (int) M_LI_S,	INSN_MACRO,		INSN2_M_FP_S,	I1,		0,	0 },
 {"li.s",		"T,l",		0,    (int) M_LI_SS,	INSN_MACRO,		INSN2_M_FP_S,	I1,		0,	0 },
-{"ll",			"t,o(b)",	0xc0000000, 0xfc000000, WR_1|RD_3|LM,		0,		I2,		0,	EE },
+{"ll",			"t,+j(b)",	0x7c000036, 0xfc00007f, WR_1|RD_3|LM,		0,		I37,		0,	0 },
+{"ll",			"t,o(b)",	0xc0000000, 0xfc000000, WR_1|RD_3|LM,		0,		I2,		0,	EE|I37 },
 {"ll",			"t,A(b)",	0,    (int) M_LL_AB,	INSN_MACRO,		0,		I2,		0,	EE },
-{"lld",			"t,o(b)",	0xd0000000, 0xfc000000, WR_1|RD_3|LM,		0,		I3,		0,	EE },
+{"lld",			"t,+j(b)",	0x7c000037, 0xfc00007f, WR_1|RD_3|LM,		0,		I69,		0,	0 },
+{"lld",			"t,o(b)",	0xd0000000, 0xfc000000, WR_1|RD_3|LM,		0,		I3,		0,	EE|I69 },
 {"lld",			"t,A(b)",	0,    (int) M_LLD_AB,	INSN_MACRO,		0,		I3,		0,	EE },
 {"lq",			"t,o(b)",	0x78000000, 0xfc000000, WR_1|RD_3|LM,		0,		MMI,		0,	0 },
 {"lq",			"t,A(b)",	0,    (int) M_LQ_AB,	INSN_MACRO,		0,		MMI,		0,	0 },
 {"lqc2",		"+7,o(b)",	0xd8000000, 0xfc000000,	RD_3|WR_C2|LM,		0,		EE,		0,	0 },
 {"lqc2",		"+7,A(b)",	0,    (int) M_LQC2_AB,	INSN_MACRO,		0,		EE,		0,	0 },
 {"lui",			"t,u",		0x3c000000, 0xffe00000,	WR_1,			0,		I1,		0,	0 },
-{"luxc1",		"D,t(b)",	0x4c000005, 0xfc00f83f, WR_1|RD_2|RD_3|LM|FP_D, 0,		I5_33|N55,	0,	0},
+{"luxc1",		"D,t(b)",	0x4c000005, 0xfc00f83f, WR_1|RD_2|RD_3|LM|FP_D, 0,		I5_33|N55,	0,	I37},
+{"lwpc",		"s,-A",		0xec080000, 0xfc180000, WR_1|LM,		RD_pc,		I37,		0,	0 },
 {"lw",			"t,o(b)",	0x8c000000, 0xfc000000,	WR_1|RD_3|LM,		0,		I1,		0,	0 },
+{"lw",			"s,-a(+R)",	0xec080000, 0xfc180000, WR_1|LM,		RD_pc,		I37,		0,	0 },
 {"lw",			"t,A(b)",	0,    (int) M_LW_AB,	INSN_MACRO,		0,		I1,		0,	0 },
-{"lwc0",		"E,o(b)",	0xc0000000, 0xfc000000,	RD_3|WR_CC|CLD,		0,		I1,		0,	IOCT|IOCTP|IOCT2 },
-{"lwc0",		"E,A(b)",	0,    (int) M_LWC0_AB,	INSN_MACRO,		0,		I1,		0,	IOCT|IOCTP|IOCT2 },
+{"lwc0",		"E,o(b)",	0xc0000000, 0xfc000000,	RD_3|WR_CC|CLD,		0,		I1,		0,	IOCT|IOCTP|IOCT2|I37 },
+{"lwc0",		"E,A(b)",	0,    (int) M_LWC0_AB,	INSN_MACRO,		0,		I1,		0,	IOCT|IOCTP|IOCT2|I37 },
 {"lwc1",		"T,o(b)",	0xc4000000, 0xfc000000,	WR_1|RD_3|CLD|FP_S,	0,		I1,		0,	0 },
 {"lwc1",		"E,o(b)",	0xc4000000, 0xfc000000,	WR_1|RD_3|CLD|FP_S,	0,		I1,		0,	0 },
 {"lwc1",		"T,A(b)",	0,    (int) M_LWC1_AB,	INSN_MACRO,		INSN2_M_FP_S,	I1,		0,	0 },
 {"lwc1",		"E,A(b)",	0,    (int) M_LWC1_AB,	INSN_MACRO,		INSN2_M_FP_S,	I1,		0,	0 },
 {"l.s",			"T,o(b)",	0xc4000000, 0xfc000000,	WR_1|RD_3|CLD|FP_S,	0,		I1,		0,	0 }, /* lwc1 */
 {"l.s",			"T,A(b)",	0,    (int) M_LWC1_AB,	INSN_MACRO,		INSN2_M_FP_S,	I1,		0,	0 },
-{"lwc2",		"E,o(b)",	0xc8000000, 0xfc000000,	RD_3|WR_CC|CLD,		0,		I1,		0,	IOCT|IOCTP|IOCT2|EE },
+{"lwc2",		"E,+:(d)",	0x49400000, 0xffe00000,	RD_3|WR_C2|CLD,		0,		I37,		0,	0 },
+{"lwc2",		"E,o(b)",	0xc8000000, 0xfc000000,	RD_3|WR_CC|CLD,		0,		I1,		0,	IOCT|IOCTP|IOCT2|EE|I37 },
 {"lwc2",		"E,A(b)",	0,    (int) M_LWC2_AB,	INSN_MACRO,		0,		I1,		0,	IOCT|IOCTP|IOCT2|EE },
-{"lwc3",		"E,o(b)",	0xcc000000, 0xfc000000,	RD_3|WR_CC|CLD,		0,		I1,		0,	IOCT|IOCTP|IOCT2|EE },
-{"lwc3",		"E,A(b)",	0,    (int) M_LWC3_AB,	INSN_MACRO,		0,		I1,		0,	IOCT|IOCTP|IOCT2|EE },
-{"lwl",			"t,o(b)",	0x88000000, 0xfc000000,	WR_1|RD_3|LM,		0,		I1,		0,	0 },
-{"lwl",			"t,A(b)",	0,    (int) M_LWL_AB,	INSN_MACRO,		0,		I1,		0,	0 },
-{"lcache",		"t,o(b)",	0x88000000, 0xfc000000,	WR_1|RD_3|LM,		0,		I2,		0,	0 }, /* same */
-{"lcache",		"t,A(b)",	0,    (int) M_LWL_AB,	INSN_MACRO,		0,		I2,		0,	0 }, /* as lwl */
-{"lwr",			"t,o(b)",	0x98000000, 0xfc000000,	WR_1|RD_3|LM,		0,		I1,		0,	0 },
-{"lwr",			"t,A(b)",	0,    (int) M_LWR_AB,	INSN_MACRO,		0,		I1,		0,	0 },
-{"flush",		"t,o(b)",	0x98000000, 0xfc000000,	WR_1|RD_3|LM,		0,		I2,		0,	0 }, /* same */
-{"flush",		"t,A(b)",	0,    (int) M_LWR_AB,	INSN_MACRO,		0,		I2,		0,	0 }, /* as lwr */
+{"lwc3",		"E,o(b)",	0xcc000000, 0xfc000000,	RD_3|WR_CC|CLD,		0,		I1,		0,	IOCT|IOCTP|IOCT2|EE|I37 },
+{"lwc3",		"E,A(b)",	0,    (int) M_LWC3_AB,	INSN_MACRO,		0,		I1,		0,	IOCT|IOCTP|IOCT2|EE|I37 },
+{"lwl",			"t,o(b)",	0x88000000, 0xfc000000,	WR_1|RD_3|LM,		0,		I1,		0,	I37 },
+{"lwl",			"t,A(b)",	0,    (int) M_LWL_AB,	INSN_MACRO,		0,		I1,		0,	I37 },
+{"lcache",		"t,o(b)",	0x88000000, 0xfc000000,	WR_1|RD_3|LM,		0,		I2,		0,	I37 }, /* same */
+{"lcache",		"t,A(b)",	0,    (int) M_LWL_AB,	INSN_MACRO,		0,		I2,		0,	I37 }, /* as lwl */
+{"lwr",			"t,o(b)",	0x98000000, 0xfc000000,	WR_1|RD_3|LM,		0,		I1,		0,	I37 },
+{"lwr",			"t,A(b)",	0,    (int) M_LWR_AB,	INSN_MACRO,		0,		I1,		0,	I37 },
+{"flush",		"t,o(b)",	0x98000000, 0xfc000000,	WR_1|RD_3|LM,		0,		I2,		0,	I37 }, /* same */
+{"flush",		"t,A(b)",	0,    (int) M_LWR_AB,	INSN_MACRO,		0,		I2,		0,	I37 }, /* as lwr */
 {"fork",		"d,s,t",	0x7c000008, 0xfc0007ff, WR_1|RD_2|RD_3|TRAP,	0,		0,		MT32,	0 },
+{"lwupc",		"s,-A",		0xec100000, 0xfc180000, WR_1,			RD_pc,		I69,		0,	0 },
 {"lwu",			"t,o(b)",	0x9c000000, 0xfc000000,	WR_1|RD_3|LM,		0,		I3,		0,	0 },
+{"lwu"	,		"s,-a(+R)",	0xec100000, 0xfc180000, WR_1,			RD_pc,		I69,		0,	0 },
 {"lwu",			"t,A(b)",	0,    (int) M_LWU_AB,	INSN_MACRO,		0,		I3,		0,	0 },
-{"lwxc1",		"D,t(b)",	0x4c000000, 0xfc00f83f, WR_1|RD_2|RD_3|LM|FP_S,     0,		I4_33,		0,	0 },
+{"lwxc1",		"D,t(b)",	0x4c000000, 0xfc00f83f, WR_1|RD_2|RD_3|LM|FP_S,     0,		I4_33,		0,	I37 },
 {"lwxs",		"d,t(b)",	0x70000088, 0xfc0007ff,	WR_1|RD_2|RD_3|LM,	     0,		0,		SMT,	0 },
 {"macc",		"d,s,t",	0x00000028, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO,	     0,		N412,		0,	0 },
 {"macc",		"d,s,t",	0x00000158, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO,	     0,		N5,		0,	0 },
@@ -1245,18 +1315,18 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"maccus",		"d,s,t",	0x00000468, 0xfc0007ff,	WR_1|RD_2|RD_3|WR_HILO,	     0,		N412,		0,	0 },
 {"mad",			"s,t",		0x70000000, 0xfc00ffff, RD_1|RD_2|MOD_HILO,	     0,		P3,		0,	0 },
 {"madu",		"s,t",		0x70000001, 0xfc00ffff, RD_1|RD_2|MOD_HILO,	     0,		P3,		0,	0 },
-{"madd.d",		"D,R,S,T",	0x4c000021, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D,    0,		I4_33,		0,	0 },
+{"madd.d",		"D,R,S,T",	0x4c000021, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D,    0,		I4_33,		0,	I37 },
 {"madd.d",		"D,S,T",	0x46200018, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	     0,		IL2E,		0,	0 },
 {"madd.d",		"D,S,T",	0x72200018, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	     0,		IL2F,		0,	0 },
-{"madd.s",		"D,R,S,T",	0x4c000020, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_S,    0,		I4_33,		0,	0 },
+{"madd.s",		"D,R,S,T",	0x4c000020, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_S,    0,		I4_33,		0,	I37 },
 {"madd.s",		"D,S,T",	0x46000018, 0xffe0003f,	WR_1|RD_2|RD_3|FP_S,	     0,		IL2E,		0,	0 },
 {"madd.s",		"D,S,T",	0x72000018, 0xffe0003f,	WR_1|RD_2|RD_3|FP_S,	     0,		IL2F,		0,	0 },
 {"madd.s",		"D,S,T",	0x4600001c, 0xffe0003f, WR_1|RD_2|RD_3|FP_S,	     0,		EE,		0,	0 },
-{"madd.ps",		"D,R,S,T",	0x4c000026, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D,    0,		I5_33,		0,	0 },
+{"madd.ps",		"D,R,S,T",	0x4c000026, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D,    0,		I5_33,		0,	I37 },
 {"madd.ps",		"D,S,T",	0x45600018, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	     0,		IL2E,		0,	0 },
 {"madd.ps",		"D,S,T",	0x72c00018, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	     0,		IL2F,		0,	0 },
 {"madd",		"s,t",		0x0000001c, 0xfc00ffff, RD_1|RD_2|WR_HILO,           0,		L1,		0,	0 },
-{"madd",		"s,t",		0x70000000, 0xfc00ffff, RD_1|RD_2|MOD_HILO,          0,		I32|N55,	0,	0 },
+{"madd",		"s,t",		0x70000000, 0xfc00ffff, RD_1|RD_2|MOD_HILO,          0,		I32|N55,	0,	I37 },
 {"madd",		"s,t",		0x70000000, 0xfc00ffff, RD_1|RD_2|WR_HILO|IS_M,      0,		G1,		0,	0 },
 {"madd",		"7,s,t",	0x70000000, 0xfc00e7ff, RD_2|RD_3|MOD_a,             0,         0,		D32,	0 },
 {"madd",		"d,s,t",	0x70000000, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO|IS_M, 0,		G1,		0,	0 },
@@ -1265,7 +1335,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"madda.s",		"S,T",		0x4600001e, 0xffe007ff, RD_1|RD_2|FP_S,		     0,		EE,		0,	0 },
 {"maddp",		"s,t",		0x70000441, 0xfc00ffff,	RD_1|RD_2|MOD_HILO,	     0,		0,		SMT,	0 },
 {"maddu",		"s,t",		0x0000001d, 0xfc00ffff, RD_1|RD_2|WR_HILO,           0,		L1,		0,	0 },
-{"maddu",		"s,t",		0x70000001, 0xfc00ffff, RD_1|RD_2|MOD_HILO,          0,		I32|N55,	0,	0 },
+{"maddu",		"s,t",		0x70000001, 0xfc00ffff, RD_1|RD_2|MOD_HILO,          0,		I32|N55,	0,	I37 },
 {"maddu",		"s,t",		0x70000001, 0xfc00ffff, RD_1|RD_2|WR_HILO|IS_M,      0,		G1,		0,	0 },
 {"maddu",		"7,s,t",	0x70000001, 0xfc00e7ff, RD_2|RD_3|MOD_a,             0,         0,		D32,	0 },
 {"maddu",		"d,s,t",	0x70000001, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO|IS_M, 0,		G1,		0,	0 },
@@ -1276,6 +1346,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"max.ob",		"D,S,Q",	0x48000007, 0xfc20003f,	WR_1|RD_2|RD_3|FP_D,	0,		N54,		0,	0 },
 {"max.qh",		"X,Y,Q",	0x78200007, 0xfc20003f,	WR_1|RD_2|RD_3|FP_D,	0,		0,		MX,	0 },
 {"max.s",		"D,S,T",	0x46000028, 0xffe0003f, WR_1|RD_2|RD_3|FP_S,	0,		EE,		0,	0 },
+{"max.s",		"D,S,T",	0x4600001e, 0xffe0003f,	WR_1|RD_2|RD_3|FP_S,	0,		I37,		0,	0 },
 {"mfbpc",		"t",		0x4000c000, 0xffe0ffff,	WR_1|RD_C0|LC,		0,		EE,		0,	0 },
 {"mfdab",		"t",		0x4000c004, 0xffe0ffff,	WR_1|RD_C0|LC,		0,		EE,		0,	0 },
 {"mfdabm",		"t",		0x4000c005, 0xffe0ffff,	WR_1|RD_C0|LC,		0,		EE,		0,	0 },
@@ -1318,10 +1389,10 @@ const struct mips_opcode mips_builtin_opcodes[] =
 /* mfhc2 is at the bottom of the table.  */
 /* mfc3 is at the bottom of the table.  */
 {"mfdr",		"t,G",		0x7000003d, 0xffe007ff,	WR_1|RD_C0|LC,		0,		N5,		0,	0 },
-{"mfhi",		"d",		0x00000010, 0xffff07ff,	WR_1|RD_HI,		0,		I1,		0,	0 },
+{"mfhi",		"d",		0x00000010, 0xffff07ff,	WR_1|RD_HI,		0,		I1,		0,	I37 },
 {"mfhi",		"d,9",		0x00000010, 0xff9f07ff, WR_1|RD_HI,		0,		0,		D32,	0 },
 {"mfhi1",		"d",		0x70000010, 0xffff07ff,	WR_1|RD_HI,		0,		EE,		0,	0 },
-{"mflo",		"d",		0x00000012, 0xffff07ff,	WR_1|RD_LO,		0,		I1,		0,	0 },
+{"mflo",		"d",		0x00000012, 0xffff07ff,	WR_1|RD_LO,		0,		I1,		0,	I37 },
 {"mflo",		"d,9",		0x00000012, 0xff9f07ff, WR_1|RD_LO,		0,		0,		D32,	0 },
 {"mflo1",		"d",		0x70000012, 0xffff07ff,	WR_1|RD_LO,		0,		EE,		0,	0 },
 {"mflhxu",		"d",		0x00000052, 0xffff07ff,	WR_1|MOD_HILO,		0,		0,		SMT,	0 },
@@ -1331,37 +1402,38 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"min.ob",		"D,S,Q",	0x48000006, 0xfc20003f,	WR_1|RD_2|RD_3|FP_D,	0,		N54,		0,	0 },
 {"min.qh",		"X,Y,Q",	0x78200006, 0xfc20003f,	WR_1|RD_2|RD_3|FP_D,	0,		0,		MX,	0 },
 {"min.s",		"D,S,T",	0x46000029, 0xffe0003f, WR_1|RD_2|RD_3|FP_S,	0,		EE,		0,	0 },
+{"min.s",		"D,S,T",	0x4600001c, 0xffe0003f,	WR_1|RD_2|RD_3|FP_S,	0,		I37,		0,	0 },
 {"mov.d",		"D,S",		0x46200006, 0xffff003f,	WR_1|RD_2|FP_D,		0,		I1,		0,	SF },
 {"mov.s",		"D,S",		0x46000006, 0xffff003f,	WR_1|RD_2|FP_S,		0,		I1,		0,	0 },
-{"mov.ps",		"D,S",		0x46c00006, 0xffff003f,	WR_1|RD_2|FP_D,		0,		I5_33|IL2F,	0,	0 },
+{"mov.ps",		"D,S",		0x46c00006, 0xffff003f,	WR_1|RD_2|FP_D,		0,		I5_33|IL2F,	0,	I37 },
 {"mov.ps",		"D,S",		0x45600006, 0xffff003f,	WR_1|RD_2|FP_D,		0,		IL2E,		0,	0 },
-{"movf",		"d,s,N",	0x00000001, 0xfc0307ff, WR_1|RD_2|RD_CC|FP_S|FP_D, 0,		I4_32,		0,	0  },
-{"movf.d",		"D,S,N",	0x46200011, 0xffe3003f, WR_1|RD_2|RD_CC|FP_D,   0,		I4_32,		0,	0 },
+{"movf",		"d,s,N",	0x00000001, 0xfc0307ff, WR_1|RD_2|RD_CC|FP_S|FP_D, 0,		I4_32,		0,	I37  },
+{"movf.d",		"D,S,N",	0x46200011, 0xffe3003f, WR_1|RD_2|RD_CC|FP_D,   0,		I4_32,		0,	I37 },
 {"movf.l",		"D,S,N",	0x46a00011, 0xffe3003f, WR_1|RD_2|RD_CC|FP_D,	0,		SB1,		MX,	0 },
 {"movf.l",		"X,Y,N",	0x46a00011, 0xffe3003f, WR_1|RD_2|RD_CC|FP_D,	0,		SB1,		MX,	0 },
-{"movf.s",		"D,S,N",	0x46000011, 0xffe3003f, WR_1|RD_2|RD_CC|FP_S,   0,		I4_32,		0,	0 },
-{"movf.ps",		"D,S,N",	0x46c00011, 0xffe3003f, WR_1|RD_2|RD_CC|FP_D,	0,		I5_33,		0,	0 },
-{"movn",		"d,v,t",	0x0000000b, 0xfc0007ff, WR_1|RD_2|RD_3, 	0,		I4_32|IL2E|IL2F|EE, 0,	0 },
+{"movf.s",		"D,S,N",	0x46000011, 0xffe3003f, WR_1|RD_2|RD_CC|FP_S,   0,		I4_32,		0,	I37 },
+{"movf.ps",		"D,S,N",	0x46c00011, 0xffe3003f, WR_1|RD_2|RD_CC|FP_D,	0,		I5_33,		0,	I37 },
+{"movn",		"d,v,t",	0x0000000b, 0xfc0007ff, WR_1|RD_2|RD_3, 	0,		I4_32|IL2E|IL2F|EE, 0,	I37 },
 {"movnz",		"d,v,t",	0x0000000b, 0xfc0007ff, WR_1|RD_2|RD_3, 	0,		IL2E|IL2F|IL3A,	0,	0 },
 {"ffc",			"d,v",		0x0000000b, 0xfc1f07ff,	WR_1|RD_2,		0,		L1,		0,	0 },
-{"movn.d",		"D,S,t",	0x46200013, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,		I4_32,		0,	0 },
+{"movn.d",		"D,S,t",	0x46200013, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,		I4_32,		0,	I37 },
 {"movn.l",		"D,S,t",	0x46a00013, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,		SB1,		MX,	0 },
 {"movn.l",		"X,Y,t",	0x46a00013, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,		SB1,		MX,	0 },
-{"movn.s",		"D,S,t",	0x46000013, 0xffe0003f, WR_1|RD_2|RD_3|FP_S,    0,		I4_32,		0,	0 },
-{"movn.ps",		"D,S,t",	0x46c00013, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,		I5_33,		0,	0 },
-{"movt",		"d,s,N",	0x00010001, 0xfc0307ff, WR_1|RD_2|RD_CC|FP_S|FP_D, 0,		I4_32,		0,	0 },
-{"movt.d",		"D,S,N",	0x46210011, 0xffe3003f, WR_1|RD_2|RD_CC|FP_D,   0,		I4_32,		0,	0 },
+{"movn.s",		"D,S,t",	0x46000013, 0xffe0003f, WR_1|RD_2|RD_3|FP_S,    0,		I4_32,		0,	I37 },
+{"movn.ps",		"D,S,t",	0x46c00013, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,		I5_33,		0,	I37 },
+{"movt",		"d,s,N",	0x00010001, 0xfc0307ff, WR_1|RD_2|RD_CC|FP_S|FP_D, 0,		I4_32,		0,	I37 },
+{"movt.d",		"D,S,N",	0x46210011, 0xffe3003f, WR_1|RD_2|RD_CC|FP_D,   0,		I4_32,		0,	I37 },
 {"movt.l",		"D,S,N",	0x46a10011, 0xffe3003f, WR_1|RD_2|RD_CC|FP_D,   0,		SB1,		MX,	0 },
 {"movt.l",		"X,Y,N",	0x46a10011, 0xffe3003f, WR_1|RD_2|RD_CC|FP_D,   0,		SB1,		MX,	0 },
-{"movt.s",		"D,S,N",	0x46010011, 0xffe3003f, WR_1|RD_2|RD_CC|FP_S,   0,		I4_32,		0,	0 },
-{"movt.ps",		"D,S,N",	0x46c10011, 0xffe3003f, WR_1|RD_2|RD_CC|FP_D,	0,		I5_33,		0,	0 },
-{"movz",		"d,v,t",	0x0000000a, 0xfc0007ff, WR_1|RD_2|RD_3, 	0,		I4_32|IL2E|IL2F|EE, 0,	0 },
+{"movt.s",		"D,S,N",	0x46010011, 0xffe3003f, WR_1|RD_2|RD_CC|FP_S,   0,		I4_32,		0,	I37 },
+{"movt.ps",		"D,S,N",	0x46c10011, 0xffe3003f, WR_1|RD_2|RD_CC|FP_D,	0,		I5_33,		0,	I37 },
+{"movz",		"d,v,t",	0x0000000a, 0xfc0007ff, WR_1|RD_2|RD_3, 	0,		I4_32|IL2E|IL2F|EE, 0,	I37 },
 {"ffs",			"d,v",		0x0000000a, 0xfc1f07ff,	WR_1|RD_2,		0,		L1,		0,	0 },
-{"movz.d",		"D,S,t",	0x46200012, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,		I4_32,		0,	0 },
+{"movz.d",		"D,S,t",	0x46200012, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,		I4_32,		0,	I37 },
 {"movz.l",		"D,S,t",	0x46a00012, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,		SB1,		MX,	0 },
 {"movz.l",		"X,Y,t",	0x46a00012, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,		SB1,		MX,	0 },
-{"movz.s",		"D,S,t",	0x46000012, 0xffe0003f, WR_1|RD_2|RD_3|FP_S,    0,		I4_32,		0,	0 },
-{"movz.ps",		"D,S,t",	0x46c00012, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,		I5_33,		0,	0 },
+{"movz.s",		"D,S,t",	0x46000012, 0xffe0003f, WR_1|RD_2|RD_3|FP_S,    0,		I4_32,		0,	I37 },
+{"movz.ps",		"D,S,t",	0x46c00012, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,		I5_33,		0,	I37 },
 {"msac",		"d,s,t",	0x000001d8, 0xfc0007ff,	WR_1|RD_2|RD_3|WR_HILO,	0,		N5,		0,	0 },
 {"msacu",		"d,s,t",	0x000001d9, 0xfc0007ff,	WR_1|RD_2|RD_3|WR_HILO,	0,		N5,		0,	0 },
 {"msachi",		"d,s,t",	0x000003d8, 0xfc0007ff,	WR_1|RD_2|RD_3|WR_HILO,	0,		N5,		0,	0 },
@@ -1373,22 +1445,22 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"msgld",		"t",		0,    (int) M_MSGLD_T,	INSN_MACRO,		0,		XLR,		0,	0 },
 {"msgwait",		"", 		0,    (int) M_MSGWAIT,	INSN_MACRO,		0,		XLR,		0,	0 },
 {"msgwait",		"t",		0,    (int) M_MSGWAIT_T,INSN_MACRO,		0,		XLR,		0,	0 },
-{"msub.d",		"D,R,S,T",	0x4c000029, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0,		I4_33,		0,	0 },
+{"msub.d",		"D,R,S,T",	0x4c000029, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0,		I4_33,		0,	I37 },
 {"msub.d",		"D,S,T",	0x46200019, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2E,		0,	0 },
 {"msub.d",		"D,S,T",	0x72200019, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2F,		0,	0 },
-{"msub.s",		"D,R,S,T",	0x4c000028, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_S, 0,		I4_33,		0,	0 },
+{"msub.s",		"D,R,S,T",	0x4c000028, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_S, 0,		I4_33,		0,	I37 },
 {"msub.s",		"D,S,T",	0x46000019, 0xffe0003f,	WR_1|RD_2|RD_3|FP_S,	0,		IL2E,		0,	0 },
 {"msub.s",		"D,S,T",	0x72000019, 0xffe0003f,	WR_1|RD_2|RD_3|FP_S,	0,		IL2F,		0,	0 },
 {"msub.s",		"D,S,T",	0x4600001d, 0xffe0003f,	WR_1|RD_2|RD_3|FP_S,	0,		EE,		0,	0 },
-{"msub.ps",		"D,R,S,T",	0x4c00002e, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0,		I5_33,		0,	0 },
+{"msub.ps",		"D,R,S,T",	0x4c00002e, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0,		I5_33,		0,	I37 },
 {"msub.ps",		"D,S,T",	0x45600019, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2E,		0,	0 },
 {"msub.ps",		"D,S,T",	0x72c00019, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2F,		0,	0 },
 {"msub",		"s,t",		0x0000001e, 0xfc00ffff, RD_1|RD_2|WR_HILO,	0,		L1,		0,	0 },
-{"msub",		"s,t",		0x70000004, 0xfc00ffff, RD_1|RD_2|MOD_HILO,     0,		I32|N55,	0,	0 },
+{"msub",		"s,t",		0x70000004, 0xfc00ffff, RD_1|RD_2|MOD_HILO,     0,		I32|N55,	0,	I37 },
 {"msub",		"7,s,t",	0x70000004, 0xfc00e7ff, RD_2|RD_3|MOD_a,        0,              0,		D32,	0 },
 {"msuba.s",		"S,T",		0x4600001f, 0xffe007ff,	RD_1|RD_2|FP_S,		0,		EE,		0,	0 },
 {"msubu",		"s,t",		0x0000001f, 0xfc00ffff, RD_1|RD_2|WR_HILO,	0,		L1,		0,	0 },
-{"msubu",		"s,t",		0x70000005, 0xfc00ffff, RD_1|RD_2|MOD_HILO,     0,		I32|N55,	0,	0 },
+{"msubu",		"s,t",		0x70000005, 0xfc00ffff, RD_1|RD_2|MOD_HILO,     0,		I32|N55,	0,	I37 },
 {"msubu",		"7,s,t",	0x70000005, 0xfc00e7ff, RD_2|RD_3|MOD_a,        0,              0,		D32,	0 },
 {"mtbpc",		"t",		0x4080c000, 0xffe0ffff,	RD_1|WR_C0|CM,		0,		EE,		0,	0 },
 {"mtdab",		"t",		0x4080c004, 0xffe0ffff,	RD_1|WR_C0|CM,		0,		EE,		0,	0 },
@@ -1415,10 +1487,10 @@ const struct mips_opcode mips_builtin_opcodes[] =
 /* mthc2 is at the bottom of the table.  */
 /* mtc3 is at the bottom of the table.  */
 {"mtdr",		"t,G",		0x7080003d, 0xffe007ff,	RD_1|WR_C0|CM,		0,		N5,		0,	0 },
-{"mthi",		"s",		0x00000011, 0xfc1fffff,	RD_1|WR_HI,		0,		I1,		0,	0 },
+{"mthi",		"s",		0x00000011, 0xfc1fffff,	RD_1|WR_HI,		0,		I1,		0,	I37 },
 {"mthi",		"s,7",		0x00000011, 0xfc1fe7ff, RD_1|WR_HI,		0,		0,		D32,	0 },
 {"mthi1",		"s",		0x70000011, 0xfc1fffff,	RD_1|WR_HI,		0,		EE,		0,	0 },
-{"mtlo",		"s",		0x00000013, 0xfc1fffff,	RD_1|WR_LO,		0,		I1,		0,	0 },
+{"mtlo",		"s",		0x00000013, 0xfc1fffff,	RD_1|WR_LO,		0,		I1,		0,	I37 },
 {"mtlo",		"s,7",		0x00000013, 0xfc1fe7ff, RD_1|WR_LO,		0,		0,		D32,	0 },
 {"mtlo1",		"s",		0x70000013, 0xfc1fffff,	RD_1|WR_LO,		0,		EE,		0,	0 },
 {"mtlhx",		"s",		0x00000053, 0xfc1fffff,	RD_1|MOD_HILO,		0,		0,		SMT,	0 },
@@ -1453,13 +1525,16 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"mul.s",		"D,V,T",	0x46000002, 0xffe0003f,	WR_1|RD_2|RD_3|FP_S,	0,		I1,		0,	0 },
 {"mul.ob",		"X,Y,Q",	0x78000030, 0xfc20003f,	WR_1|RD_2|RD_3|FP_D,	0,		SB1,		MX,	0 },
 {"mul.ob",		"D,S,Q",	0x48000030, 0xfc20003f,	WR_1|RD_2|RD_3|FP_D,	0,		N54,		0,	0 },
-{"mul.ps",		"D,V,T",	0x46c00002, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		I5_33|IL2F,	0,	0 },
+{"mul.ps",		"D,V,T",	0x46c00002, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		I5_33|IL2F,	0,	I37 },
 {"mul.ps",		"D,V,T",	0x45600002, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2E,		0,	0 },
 {"mul.qh",		"X,Y,Q",	0x78200030, 0xfc20003f,	WR_1|RD_2|RD_3|FP_D,	0,		0,		MX,	0 },
-{"mul",			"d,v,t",	0x70000002, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0,		I32|P3|N55,	0,	0},
+{"muh",			"d,v,t",	0x000000d8, 0xfc0007ff, WR_1|RD_2|RD_3, 	0,		I37,		0,	0},
+{"muhu",		"d,v,t",	0x000000d9, 0xfc0007ff, WR_1|RD_2|RD_3, 	0,		I37,		0,	0},
+{"mul",			"d,v,t",	0x00000098, 0xfc0007ff, WR_1|RD_2|RD_3, 	0,		I37,		0,	0},
+{"mul",			"d,v,t",	0x70000002, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0,		I32|P3|N55,	0,	I37},
 {"mul",			"d,s,t",	0x00000058, 0xfc0007ff,	WR_1|RD_2|RD_3|WR_HILO,	0,		N54,		0,	0 },
-{"mul",			"d,v,t",	0,    (int) M_MUL,	INSN_MACRO,		0,		I1,		0,	0 },
-{"mul",			"d,v,I",	0,    (int) M_MUL_I,	INSN_MACRO,		0,		I1,		0,	0 },
+{"mul",			"d,v,t",	0,    (int) M_MUL,	INSN_MACRO,		0,		I1,		0,	I37 },
+{"mul",			"d,v,I",	0,    (int) M_MUL_I,	INSN_MACRO,		0,		I1,		0,	I37 },
 {"mula.ob",		"Y,Q",		0x78000033, 0xfc2007ff,	RD_1|RD_2|FP_D,		WR_MACC,	SB1,		MX,	0 },
 {"mula.ob",		"S,Q",		0x48000033, 0xfc2007ff,	RD_1|RD_2|FP_D,		WR_MACC,	N54,		0,	0 },
 {"mula.qh",		"Y,Q",		0x78200033, 0xfc2007ff,	RD_1|RD_2|FP_D,		WR_MACC,	0,		MX,	0 },
@@ -1469,10 +1544,10 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"mull.ob",		"Y,Q",		0x78000433, 0xfc2007ff,	RD_1|RD_2|FP_D, 	WR_MACC,	SB1,		MX,	0 },
 {"mull.ob",		"S,Q",		0x48000433, 0xfc2007ff,	RD_1|RD_2|FP_D,		WR_MACC,	N54,		0,	0 },
 {"mull.qh",		"Y,Q",		0x78200433, 0xfc2007ff,	RD_1|RD_2|FP_D,		WR_MACC,	0,		MX,	0 },
-{"mulo",		"d,v,t",	0,    (int) M_MULO,	INSN_MACRO,		0,		I1,		0,	0 },
-{"mulo",		"d,v,I",	0,    (int) M_MULO_I,	INSN_MACRO,		0,		I1,		0,	0 },
-{"mulou",		"d,v,t",	0,    (int) M_MULOU,	INSN_MACRO,		0,		I1,		0,	0 },
-{"mulou",		"d,v,I",	0,    (int) M_MULOU_I,	INSN_MACRO,		0,		I1,		0,	0 },
+{"mulo",		"d,v,t",	0,    (int) M_MULO,	INSN_MACRO,		0,		I1,		0,	I37 },
+{"mulo",		"d,v,I",	0,    (int) M_MULO_I,	INSN_MACRO,		0,		I1,		0,	I37 },
+{"mulou",		"d,v,t",	0,    (int) M_MULOU,	INSN_MACRO,		0,		I1,		0,	I37 },
+{"mulou",		"d,v,I",	0,    (int) M_MULOU_I,	INSN_MACRO,		0,		I1,		0,	I37 },
 {"mulr.ps",		"D,S,T",	0x46c0001a, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		0,		M3D,	0 },
 {"muls",		"d,s,t",	0x000000d8, 0xfc0007ff,	WR_1|RD_2|RD_3|WR_HILO,	0,		N5,		0,	0 },
 {"mulsu",		"d,s,t",	0x000000d9, 0xfc0007ff,	WR_1|RD_2|RD_3|WR_HILO,	0,		N5,		0,	0 },
@@ -1484,40 +1559,41 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"mulsl.ob",		"Y,Q",		0x78000432, 0xfc2007ff,	RD_1|RD_2|FP_D,		WR_MACC,	SB1,		MX,	0 },
 {"mulsl.ob",		"S,Q",		0x48000432, 0xfc2007ff,	RD_1|RD_2|FP_D,		WR_MACC,	N54,		0,	0 },
 {"mulsl.qh",		"Y,Q",		0x78200432, 0xfc2007ff,	RD_1|RD_2|FP_D,		WR_MACC,	0,		MX,	0 },
-{"mult",		"s,t",		0x00000018, 0xfc00ffff, RD_1|RD_2|WR_HILO|IS_M, 0,		I1,		0,	0 },
+{"mult",		"s,t",		0x00000018, 0xfc00ffff, RD_1|RD_2|WR_HILO|IS_M, 0,		I1,		0,	I37 },
 {"mult",		"7,s,t",	0x00000018, 0xfc00e7ff, RD_2|RD_3|WR_a,         0,              0,		D32,	0 },
 {"mult",		"d,s,t",	0x00000018, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO|IS_M, 0,		G1,		0,	0 },
 {"mult1",		"s,t",		0x70000018, 0xfc00ffff, RD_1|RD_2|WR_HILO|IS_M, 0,		EE,		0,	0 },
 {"mult1",		"d,s,t",	0x70000018, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO|IS_M, 0,		EE,		0,	0 },
 {"multp",		"s,t",		0x00000459, 0xfc00ffff,	RD_1|RD_2|MOD_HILO,	0,		0,		SMT,	0 },
-{"multu",		"s,t",		0x00000019, 0xfc00ffff, RD_1|RD_2|WR_HILO|IS_M, 0,		I1,		0,	0 },
+{"multu",		"s,t",		0x00000019, 0xfc00ffff, RD_1|RD_2|WR_HILO|IS_M, 0,		I1,		0,	I37 },
 {"multu",		"7,s,t",	0x00000019, 0xfc00e7ff, RD_2|RD_3|WR_a,         0,              0,		D32,	0 },
 {"multu",		"d,s,t",	0x00000019, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO|IS_M, 0,		G1,		0,	0 },
 {"multu1",		"s,t",		0x70000019, 0xfc00ffff, RD_1|RD_2|WR_HILO|IS_M, 0,		EE,		0,	0 },
 {"multu1",		"d,s,t",	0x70000019, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO|IS_M, 0,		EE,		0,	0 },
+{"mulu",		"d,v,t",	0x00000099, 0xfc0007ff, WR_1|RD_2|RD_3, 	0,		I37,		0,	0},
 {"mulu",		"d,s,t",	0x00000059, 0xfc0007ff,	WR_1|RD_2|RD_3|WR_HILO,	0,		N5,		0,	0 },
 {"neg",			"d,w",		0x00000022, 0xffe007ff,	WR_1|RD_2,		0,		I1,		0,	0 }, /* sub 0 */
 {"negu",		"d,w",		0x00000023, 0xffe007ff,	WR_1|RD_2,		0,		I1,		0,	0 }, /* subu 0 */
 {"neg.d",		"D,V",		0x46200007, 0xffff003f,	WR_1|RD_2|FP_D,		0,		I1,		0,	SF },
 {"neg.s",		"D,V",		0x46000007, 0xffff003f,	WR_1|RD_2|FP_S,		0,		I1,		0,	0 },
-{"neg.ps",		"D,V",		0x46c00007, 0xffff003f,	WR_1|RD_2|FP_D,		0,		I5_33|IL2F,	0,	0 },
+{"neg.ps",		"D,V",		0x46c00007, 0xffff003f,	WR_1|RD_2|FP_D,		0,		I5_33|IL2F,	0,	I37 },
 {"neg.ps",		"D,V",		0x45600007, 0xffff003f,	WR_1|RD_2|FP_D,		0,		IL2E,		0,	0 },
-{"nmadd.d",		"D,R,S,T",	0x4c000031, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0,		I4_33,		0,	0 },
+{"nmadd.d",		"D,R,S,T",	0x4c000031, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0,		I4_33,		0,	I37 },
 {"nmadd.d",		"D,S,T",	0x4620001a, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2E,		0,	0 },
 {"nmadd.d",		"D,S,T",	0x7220001a, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2F,		0,	0 },
-{"nmadd.s",		"D,R,S,T",	0x4c000030, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_S, 0,		I4_33,		0,	0 },
+{"nmadd.s",		"D,R,S,T",	0x4c000030, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_S, 0,		I4_33,		0,	I37 },
 {"nmadd.s",		"D,S,T",	0x4600001a, 0xffe0003f,	WR_1|RD_2|RD_3|FP_S,	0,		IL2E,		0,	0 },
 {"nmadd.s",		"D,S,T",	0x7200001a, 0xffe0003f,	WR_1|RD_2|RD_3|FP_S,	0,		IL2F,		0,	0 },
-{"nmadd.ps",		"D,R,S,T",	0x4c000036, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0,		I5_33,		0,	0 },
+{"nmadd.ps",		"D,R,S,T",	0x4c000036, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0,		I5_33,		0,	I37 },
 {"nmadd.ps",		"D,S,T",	0x4560001a, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2E,		0,	0 },
 {"nmadd.ps",		"D,S,T",	0x72c0001a, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2F,		0,	0 },
-{"nmsub.d",		"D,R,S,T",	0x4c000039, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0,		I4_33,		0,	0 },
+{"nmsub.d",		"D,R,S,T",	0x4c000039, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0,		I4_33,		0,	I37 },
 {"nmsub.d",		"D,S,T",	0x4620001b, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2E,		0,	0 },
 {"nmsub.d",		"D,S,T",	0x7220001b, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2F,		0,	0 },
-{"nmsub.s",		"D,R,S,T",	0x4c000038, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_S, 0,		I4_33,		0,	0 },
+{"nmsub.s",		"D,R,S,T",	0x4c000038, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_S, 0,		I4_33,		0,	I37 },
 {"nmsub.s",		"D,S,T",	0x4600001b, 0xffe0003f,	WR_1|RD_2|RD_3|FP_S,	0,		IL2E,		0,	0 },
 {"nmsub.s",		"D,S,T",	0x7200001b, 0xffe0003f,	WR_1|RD_2|RD_3|FP_S,	0,		IL2F,		0,	0 },
-{"nmsub.ps",		"D,R,S,T",	0x4c00003e, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0,		I5_33,		0,	0 },
+{"nmsub.ps",		"D,R,S,T",	0x4c00003e, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0,		I5_33,		0,	I37 },
 {"nmsub.ps",		"D,S,T",	0x4560001b, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2E,		0,	0 },
 {"nmsub.ps",		"D,S,T",	0x72c0001b, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2F,		0,	0 },
 /* nop is at the start of the table.  */
@@ -1582,8 +1658,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"pickt.qh",		"X,Y,Q",	0x78200003, 0xfc20003f,	WR_1|RD_2|RD_3|FP_D,	0,		0,		MX,	0 },
 {"pinteh",		"d,s,t",	0x700002a9, 0xfc0007ff, WR_1|RD_2|RD_3,		0,		MMI,		0,	0 },
 {"pinth",		"d,s,t",	0x70000289, 0xfc0007ff, WR_1|RD_2|RD_3,		0,		MMI,		0,	0 },
-{"pll.ps",		"D,V,T",	0x46c0002c, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		I5_33,		0,	0 },
-{"plu.ps",		"D,V,T",	0x46c0002d, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		I5_33,		0,	0 },
+{"pll.ps",		"D,V,T",	0x46c0002c, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		I5_33,		0,	I37 },
+{"plu.ps",		"D,V,T",	0x46c0002d, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		I5_33,		0,	I37 },
 {"plzcw",		"d,s",		0x70000004, 0xfc1f07ff, WR_1|RD_2,		0,		MMI,		0,	0 },
 {"pmaddh",		"d,s,t",	0x70000409, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO,	0,		MMI,		0,	0 },
 {"pmadduw",		"d,s,t",	0x70000029, 0xfc0007ff, WR_1|RD_2|RD_3|MOD_HILO, 0,		MMI,		0,	0 },
@@ -1625,8 +1701,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"psubuw",		"d,s,t",	0x70000468, 0xfc0007ff, WR_1|RD_2|RD_3,		0,		MMI,		0,	0 },
 {"pxor",		"d,s,t",	0x700004c9, 0xfc0007ff, WR_1|RD_2|RD_3,		0,		MMI,		0,	0 },
   /* pref and prefx are at the start of the table.  */
-{"pul.ps",		"D,V,T",	0x46c0002e, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		I5_33,		0,	0 },
-{"puu.ps",		"D,V,T",	0x46c0002f, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		I5_33,		0,	0 },
+{"pul.ps",		"D,V,T",	0x46c0002e, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		I5_33,		0,	I37 },
+{"puu.ps",		"D,V,T",	0x46c0002f, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		I5_33,		0,	I37 },
 {"pperm",		"s,t",		0x70000481, 0xfc00ffff,	RD_1|RD_2|MOD_HILO,	0,		0,		SMT,	0 },
 {"qfsrv",		"d,s,t",	0x700006e8, 0xfc0007ff, WR_1|RD_2|RD_3,		0,		MMI,		0,	0 },
 {"qmac.00",		"s,t",		0x70000412, 0xfc00ffff, RD_1|RD_2|MOD_HILO,	0,		IOCT2,		0,	0 },
@@ -1655,12 +1731,12 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"recip2.d",		"D,S,T",	0x4620001c, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		0,		M3D,	0 },
 {"recip2.ps",		"D,S,T",	0x46c0001c, 0xffe0003f,	WR_1|RD_2|RD_3|FP_S,	0,		0,		M3D,	0 },
 {"recip2.s",		"D,S,T",	0x4600001c, 0xffe0003f,	WR_1|RD_2|RD_3|FP_S,	0,		0,		M3D,	0 },
-{"rem",			"z,s,t",	0x0000001a, 0xfc00ffff, RD_2|RD_3|WR_HILO,      0,		I1,		0,	0 },
-{"rem",			"d,v,t",	0,    (int) M_REM_3,	INSN_MACRO,		0,		I1,		0,	0 },
-{"rem",			"d,v,I",	0,    (int) M_REM_3I,	INSN_MACRO,		0,		I1,		0,	0 },
-{"remu",		"z,s,t",	0x0000001b, 0xfc00ffff, RD_2|RD_3|WR_HILO,      0,		I1,		0,	0 },
-{"remu",		"d,v,t",	0,    (int) M_REMU_3,	INSN_MACRO,		0,		I1,		0,	0 },
-{"remu",		"d,v,I",	0,    (int) M_REMU_3I,	INSN_MACRO,		0,		I1,		0,	0 },
+{"rem",			"z,s,t",	0x0000001a, 0xfc00ffff, RD_2|RD_3|WR_HILO,      INSN2_ALIAS,	I1,		0,	I37 },
+{"rem",			"d,v,t",	0,    (int) M_REM_3,	INSN_MACRO,		0,		I1,		0,	I37 },
+{"rem",			"d,v,I",	0,    (int) M_REM_3I,	INSN_MACRO,		0,		I1,		0,	I37 },
+{"remu",		"z,s,t",	0x0000001b, 0xfc00ffff, RD_2|RD_3|WR_HILO,      INSN2_ALIAS,	I1,		0,	I37 },
+{"remu",		"d,v,t",	0,    (int) M_REMU_3,	INSN_MACRO,		0,		I1,		0,	I37 },
+{"remu",		"d,v,I",	0,    (int) M_REMU_3I,	INSN_MACRO,		0,		I1,		0,	I37 },
 {"rdhwr",		"t,K",		0x7c00003b, 0xffe007ff, WR_1,			0,		I33,		0,	0 },
 {"rdpgpr",		"d,w",		0x41400000, 0xffe007ff, WR_1,			0,		I33,		0,	0 },
 /* rfe is moved below as it now conflicts with tlbgp */
@@ -1705,9 +1781,11 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"saad",		"t,(b)",	0x70000019, 0xfc00ffff,	RD_1|RD_2|SM,		0,		IOCTP,		0,	0 },
 {"sb",			"t,o(b)",	0xa0000000, 0xfc000000,	RD_1|RD_3|SM,		0,		I1,		0,	0 },
 {"sb",			"t,A(b)",	0,    (int) M_SB_AB,	INSN_MACRO,		0,		I1,		0,	0 },
-{"sc",			"t,o(b)",	0xe0000000, 0xfc000000, MOD_1|RD_3|SM,		0,		I2,		0,	EE },
+{"sc",			"t,+j(b)",	0x7c000026, 0xfc00007f, MOD_1|RD_3|SM,		0,		I37,		0,	0 },
+{"sc",			"t,o(b)",	0xe0000000, 0xfc000000, MOD_1|RD_3|SM,		0,		I2,		0,	EE|I37 },
 {"sc",			"t,A(b)",	0,    (int) M_SC_AB,	INSN_MACRO,		0,		I2,		0,	EE },
-{"scd",			"t,o(b)",	0xf0000000, 0xfc000000, MOD_1|RD_3|SM,		0,		I3,		0,	EE },
+{"scd",			"t,+j(b)",	0x7c000027, 0xfc00007f, MOD_1|RD_3|SM,		0,		I69,		0,	0 },
+{"scd",			"t,o(b)",	0xf0000000, 0xfc000000, MOD_1|RD_3|SM,		0,		I3,		0,	EE|I69 },
 {"scd",			"t,A(b)",	0,    (int) M_SCD_AB,	INSN_MACRO,		0,		I3,		0,	EE },
 /* The macro has to be first to handle o32 correctly.  */
 {"sd",			"t,A(b)",	0,    (int) M_SD_AB,	INSN_MACRO,		0,		I1,		0,	0 },
@@ -1715,23 +1793,26 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"sdbbp",		"",		0x0000000e, 0xffffffff,	TRAP,           	0,		G2,		0,	0 },
 {"sdbbp",		"c",		0x0000000e, 0xfc00ffff,	TRAP,			0,		G2,		0,	0 },
 {"sdbbp",		"c,q",		0x0000000e, 0xfc00003f,	TRAP,			0,		G2,		0,	0 },
-{"sdbbp",		"",		0x7000003f, 0xffffffff, TRAP,           	0,		I32,		0,	0 },
-{"sdbbp",		"B",		0x7000003f, 0xfc00003f, TRAP,           	0,		I32,		0,	0 },
+{"sdbbp",		"",		0x0000000e, 0xffffffff, TRAP,           	0,		I37,		0,	0 },
+{"sdbbp",		"",		0x7000003f, 0xffffffff, TRAP,           	0,		I32,		0,	I37 },
+{"sdbbp",		"B",		0x0000000e, 0xfc00003f, TRAP,           	0,		I37,		0,	0 },
+{"sdbbp",		"B",		0x7000003f, 0xfc00003f, TRAP,           	0,		I32,		0,	I37 },
 {"sdc1",		"T,o(b)",	0xf4000000, 0xfc000000, RD_1|RD_3|SM|FP_D,	0,		I2,		0,	SF },
 {"sdc1",		"E,o(b)",	0xf4000000, 0xfc000000, RD_1|RD_3|SM|FP_D,	0,		I2,		0,	SF },
 {"sdc1",		"T,A(b)",	0,    (int) M_SDC1_AB,	INSN_MACRO,		INSN2_M_FP_D,	I2,		0,	SF },
 {"sdc1",		"E,A(b)",	0,    (int) M_SDC1_AB,	INSN_MACRO,		INSN2_M_FP_D,	I2,		0,	SF },
-{"sdc2",		"E,o(b)",	0xf8000000, 0xfc000000,	RD_3|RD_C2|SM,		0,		I2,		0,	IOCT|IOCTP|IOCT2|EE },
+{"sdc2",		"E,+:(d)",	0x49e00000, 0xffe00000,	RD_3|RD_C2|SM,		0,		I37,		0,	0 },
+{"sdc2",		"E,o(b)",	0xf8000000, 0xfc000000,	RD_3|RD_C2|SM,		0,		I2,		0,	IOCT|IOCTP|IOCT2|EE|I37 },
 {"sdc2",		"E,A(b)",	0,    (int) M_SDC2_AB,	INSN_MACRO,		0,		I2,		0,	IOCT|IOCTP|IOCT2|EE },
 {"sdc3",		"E,o(b)",	0xfc000000, 0xfc000000,	RD_3|RD_C3|SM,		0,		I2,		0,	IOCT|IOCTP|IOCT2|EE },
 {"sdc3",		"E,A(b)",	0,    (int) M_SDC3_AB,	INSN_MACRO,		0,		I2,		0,	IOCT|IOCTP|IOCT2|EE },
 {"s.d",			"T,o(b)",	0xf4000000, 0xfc000000, RD_1|RD_3|SM|FP_D,	0,		I2,		0,	SF },
 {"s.d",			"T,A(b)",	0,    (int) M_S_DAB,	INSN_MACRO,		INSN2_M_FP_D,	I1,		0,	0 },
-{"sdl",			"t,o(b)",	0xb0000000, 0xfc000000,	RD_1|RD_3|SM,		0,		I3,		0,	0 },
-{"sdl",			"t,A(b)",	0,    (int) M_SDL_AB,	INSN_MACRO,		0,		I3,		0,	0 },
-{"sdr",			"t,o(b)",	0xb4000000, 0xfc000000,	RD_1|RD_3|SM,		0,		I3,		0,	0 },
-{"sdr",			"t,A(b)",	0,    (int) M_SDR_AB,	INSN_MACRO,		0,		I3,		0,	0 },
-{"sdxc1",		"S,t(b)",	0x4c000009, 0xfc0007ff, RD_1|RD_2|RD_3|SM|FP_D,	0,		I4_33,		0,	0 },
+{"sdl",			"t,o(b)",	0xb0000000, 0xfc000000,	RD_1|RD_3|SM,		0,		I3,		0,	I69 },
+{"sdl",			"t,A(b)",	0,    (int) M_SDL_AB,	INSN_MACRO,		0,		I3,		0,	I69 },
+{"sdr",			"t,o(b)",	0xb4000000, 0xfc000000,	RD_1|RD_3|SM,		0,		I3,		0,	I69 },
+{"sdr",			"t,A(b)",	0,    (int) M_SDR_AB,	INSN_MACRO,		0,		I3,		0,	I69 },
+{"sdxc1",		"S,t(b)",	0x4c000009, 0xfc0007ff, RD_1|RD_2|RD_3|SM|FP_D,	0,		I4_33,		0,	I37 },
 {"seb",			"d,w",		0x7c000420, 0xffe007ff,	WR_1|RD_2,		0,		I33,		0,	0 },
 {"seh",			"d,w",		0x7c000620, 0xffe007ff,	WR_1|RD_2,		0,		I33,		0,	0 },
 {"selsl",		"d,v,t",	0x00000005, 0xfc0007ff,	WR_1|RD_2|RD_3,		0,		L1,		0,	0 },
@@ -1820,14 +1901,14 @@ const struct mips_opcode mips_builtin_opcodes[] =
 /* ssnop is at the start of the table.  */
 {"standby",		"",		0x42000021, 0xffffffff,	0,			0,		V1,		0,	0 },
 {"sub",			"d,v,t",	0x00000022, 0xfc0007ff,	WR_1|RD_2|RD_3,		0,		I1,		0,	0 },
-{"sub",			"d,v,I",	0,    (int) M_SUB_I,	INSN_MACRO,		0,		I1,		0,	0 },
+{"sub",			"d,v,I",	0,    (int) M_SUB_I,	INSN_MACRO,		0,		I1,		0,	I37 },
 {"sub",			"D,S,T",	0x45c00001, 0xffe0003f,	WR_1|RD_2|RD_3|FP_S,	0,		IL2E,		0,	0 },
 {"sub",			"D,S,T",	0x4b40000d, 0xffe0003f,	WR_1|RD_2|RD_3|FP_S,	0,		IL2F|IL3A,	0,	0 },
 {"sub.d",		"D,V,T",	0x46200001, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		I1,		0,	SF },
 {"sub.s",		"D,V,T",	0x46000001, 0xffe0003f,	WR_1|RD_2|RD_3|FP_S,	0,		I1,		0,	0 },
 {"sub.ob",		"X,Y,Q",	0x7800000a, 0xfc20003f,	WR_1|RD_2|RD_3|FP_D,	0,		SB1,		MX,	0 },
 {"sub.ob",		"D,S,Q",	0x4800000a, 0xfc20003f,	WR_1|RD_2|RD_3|FP_D,	0,		N54,		0,	0 },
-{"sub.ps",		"D,V,T",	0x46c00001, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		I5_33|IL2F,	0,	0 },
+{"sub.ps",		"D,V,T",	0x46c00001, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		I5_33|IL2F,	0,	I37 },
 {"sub.ps",		"D,V,T",	0x45600001, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2E,		0,	0 },
 {"sub.qh",		"X,Y,Q",	0x7820000a, 0xfc20003f,	WR_1|RD_2|RD_3|FP_D,	0,		0,		MX,	0 },
 {"suba.ob",		"Y,Q",		0x78000036, 0xfc2007ff,	RD_1|RD_2|FP_D,		WR_MACC,	SB1,		MX,	0 },
@@ -1840,33 +1921,34 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"subu",		"D,S,T",	0x45800001, 0xffe0003f,	WR_1|RD_2|RD_3|FP_S,	0,		IL2E,		0,	0 },
 {"subu",		"D,S,T",	0x4b00000d, 0xffe0003f,	WR_1|RD_2|RD_3|FP_S,	0,		IL2F|IL3A,	0,	0 },
 {"suspend",		"",		0x42000022, 0xffffffff,	0,			0,		V1,		0,	0 },
-{"suxc1",		"S,t(b)",	0x4c00000d, 0xfc0007ff, RD_1|RD_2|RD_3|SM|FP_D,	0,		I5_33|N55,	0,	0},
+{"suxc1",		"S,t(b)",	0x4c00000d, 0xfc0007ff, RD_1|RD_2|RD_3|SM|FP_D,	0,		I5_33|N55,	0,	I37},
 {"sw",			"t,o(b)",	0xac000000, 0xfc000000,	RD_1|RD_3|SM,		0,		I1,		0,	0 },
 {"sw",			"t,A(b)",	0,    (int) M_SW_AB,	INSN_MACRO,		0,		I1,		0,	0 },
 {"swapw",		"t,b",		0x70000014, 0xfc00ffff, MOD_1|RD_2|LM|SM,	0,		XLR,		0,	0 },
 {"swapwu",		"t,b",		0x70000015, 0xfc00ffff, MOD_1|RD_2|LM|SM,	0,		XLR,		0,	0 },
 {"swapd",		"t,b",		0x70000016, 0xfc00ffff, MOD_1|RD_2|LM|SM,	0,		XLR,		0,	0 },
-{"swc0",		"E,o(b)",	0xe0000000, 0xfc000000,	RD_3|RD_C0|SM,		0,		I1,		0,	IOCT|IOCTP|IOCT2 },
-{"swc0",		"E,A(b)",	0,    (int) M_SWC0_AB,	INSN_MACRO,		0,		I1,		0,	IOCT|IOCTP|IOCT2 },
+{"swc0",		"E,o(b)",	0xe0000000, 0xfc000000,	RD_3|RD_C0|SM,		0,		I1,		0,	IOCT|IOCTP|IOCT2|I37 },
+{"swc0",		"E,A(b)",	0,    (int) M_SWC0_AB,	INSN_MACRO,		0,		I1,		0,	IOCT|IOCTP|IOCT2|I37 },
 {"swc1",		"T,o(b)",	0xe4000000, 0xfc000000,	RD_1|RD_3|SM|FP_S,	0,		I1,		0,	0 },
 {"swc1",		"E,o(b)",	0xe4000000, 0xfc000000,	RD_1|RD_3|SM|FP_S,	0,		I1,		0,	0 },
 {"swc1",		"T,A(b)",	0,    (int) M_SWC1_AB,	INSN_MACRO,		INSN2_M_FP_S,	I1,		0,	0 },
 {"swc1",		"E,A(b)",	0,    (int) M_SWC1_AB,	INSN_MACRO,		INSN2_M_FP_S,	I1,		0,	0 },
 {"s.s",			"T,o(b)",	0xe4000000, 0xfc000000,	RD_1|RD_3|SM|FP_S,	0,		I1,		0,	0 }, /* swc1 */
 {"s.s",			"T,A(b)",	0,    (int) M_SWC1_AB,	INSN_MACRO,		INSN2_M_FP_S,	I1,		0,	0 },
-{"swc2",		"E,o(b)",	0xe8000000, 0xfc000000,	RD_3|RD_C2|SM,		0,		I1,		0,	IOCT|IOCTP|IOCT2|EE },
+{"swc2",		"E,+:(d)",	0x49600000, 0xffe00000,	RD_3|RD_C2|SM,		0,		I37,		0,	0 },
+{"swc2",		"E,o(b)",	0xe8000000, 0xfc000000,	RD_3|RD_C2|SM,		0,		I1,		0,	IOCT|IOCTP|IOCT2|EE|I37 },
 {"swc2",		"E,A(b)",	0,    (int) M_SWC2_AB,	INSN_MACRO,		0,		I1,		0,	IOCT|IOCTP|IOCT2|EE },
-{"swc3",		"E,o(b)",	0xec000000, 0xfc000000,	RD_3|RD_C3|SM,		0,		I1,		0,	IOCT|IOCTP|IOCT2|EE },
-{"swc3",		"E,A(b)",	0,    (int) M_SWC3_AB,	INSN_MACRO,		0,		I1,		0,	IOCT|IOCTP|IOCT2|EE },
-{"swl",			"t,o(b)",	0xa8000000, 0xfc000000,	RD_1|RD_3|SM,		0,		I1,		0,	0 },
-{"swl",			"t,A(b)",	0,    (int) M_SWL_AB,	INSN_MACRO,		0,		I1,		0,	0 },
-{"scache",		"t,o(b)",	0xa8000000, 0xfc000000,	RD_1|RD_3,		0,		I2,		0,	0 }, /* same */
-{"scache",		"t,A(b)",	0,    (int) M_SWL_AB,	INSN_MACRO,		0,		I2,		0,	0 }, /* as swl */
-{"swr",			"t,o(b)",	0xb8000000, 0xfc000000,	RD_1|RD_3|SM,		0,		I1,		0,	0 },
-{"swr",			"t,A(b)",	0,    (int) M_SWR_AB,	INSN_MACRO,		0,		I1,		0,	0 },
-{"invalidate",		"t,o(b)",	0xb8000000, 0xfc000000,	RD_1|RD_3,		0,		I2,		0,	0 }, /* same */
-{"invalidate",		"t,A(b)",	0,    (int) M_SWR_AB,	INSN_MACRO,		0,		I2,		0,	0 }, /* as swr */
-{"swxc1",		"S,t(b)",	0x4c000008, 0xfc0007ff, RD_1|RD_2|RD_3|SM|FP_S,	0,		I4_33,		0,	0 },
+{"swc3",		"E,o(b)",	0xec000000, 0xfc000000,	RD_3|RD_C3|SM,		0,		I1,		0,	IOCT|IOCTP|IOCT2|EE|I37 },
+{"swc3",		"E,A(b)",	0,    (int) M_SWC3_AB,	INSN_MACRO,		0,		I1,		0,	IOCT|IOCTP|IOCT2|EE|I37 },
+{"swl",			"t,o(b)",	0xa8000000, 0xfc000000,	RD_1|RD_3|SM,		0,		I1,		0,	I37 },
+{"swl",			"t,A(b)",	0,    (int) M_SWL_AB,	INSN_MACRO,		0,		I1,		0,	I37 },
+{"scache",		"t,o(b)",	0xa8000000, 0xfc000000,	RD_1|RD_3,		0,		I2,		0,	I37 }, /* same */
+{"scache",		"t,A(b)",	0,    (int) M_SWL_AB,	INSN_MACRO,		0,		I2,		0,	I37 }, /* as swl */
+{"swr",			"t,o(b)",	0xb8000000, 0xfc000000,	RD_1|RD_3|SM,		0,		I1,		0,	I37 },
+{"swr",			"t,A(b)",	0,    (int) M_SWR_AB,	INSN_MACRO,		0,		I1,		0,	I37 },
+{"invalidate",		"t,o(b)",	0xb8000000, 0xfc000000,	RD_1|RD_3,		0,		I2,		0,	I37 }, /* same */
+{"invalidate",		"t,A(b)",	0,    (int) M_SWR_AB,	INSN_MACRO,		0,		I2,		0,	I37 }, /* as swr */
+{"swxc1",		"S,t(b)",	0x4c000008, 0xfc0007ff, RD_1|RD_2|RD_3|SM|FP_S,	0,		I4_33,		0,	I37 },
 {"synciobdma",		"",		0x0000008f, 0xffffffff,	NODS,			0,		IOCT,		0,	0 },
 {"syncs",		"",		0x0000018f, 0xffffffff,	NODS,			0,		IOCT,		0,	0 },
 {"syncw",		"",		0x0000010f, 0xffffffff,	NODS,			0,		IOCT,		0,	0 },
@@ -1883,23 +1965,23 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"synci",		"o(b)",		0x041f0000, 0xfc1f0000,	RD_2|SM,		0,		I33,		0,	0 },
 {"syscall",		"",		0x0000000c, 0xffffffff,	TRAP,			0,		I1,		0,	0 },
 {"syscall",		"B",		0x0000000c, 0xfc00003f,	TRAP,			0,		I1,		0,	0 },
-{"teqi",		"s,j",		0x040c0000, 0xfc1f0000, RD_1|TRAP,		0,		I2,		0,	0 },
+{"teqi",		"s,j",		0x040c0000, 0xfc1f0000, RD_1|TRAP,		0,		I2,		0,	I37 },
 {"teq",			"s,t",		0x00000034, 0xfc00ffff, RD_1|RD_2|TRAP,		0,		I2,		0,	0 },
 {"teq",			"s,t,q",	0x00000034, 0xfc00003f, RD_1|RD_2|TRAP,		0,		I2,		0,	0 },
-{"teq",			"s,j",		0x040c0000, 0xfc1f0000, RD_1|TRAP,		0,		I2,		0,	0 }, /* teqi */
+{"teq",			"s,j",		0x040c0000, 0xfc1f0000, RD_1|TRAP,		0,		I2,		0,	I37 }, /* teqi */
 {"teq",			"s,I",		0,    (int) M_TEQ_I,	INSN_MACRO,		0,		I2,		0,	0 },
-{"tgei",		"s,j",		0x04080000, 0xfc1f0000, RD_1|TRAP,		0,		I2,		0,	0 },
+{"tgei",		"s,j",		0x04080000, 0xfc1f0000, RD_1|TRAP,		0,		I2,		0,	I37 },
 {"tge",			"s,t",		0x00000030, 0xfc00ffff,	RD_1|RD_2|TRAP,		0,		I2,		0,	0 },
 {"tge",			"s,t,q",	0x00000030, 0xfc00003f,	RD_1|RD_2|TRAP,		0,		I2,		0,	0 },
-{"tge",			"s,j",		0x04080000, 0xfc1f0000, RD_1|TRAP,		0,		I2,		0,	0 }, /* tgei */
+{"tge",			"s,j",		0x04080000, 0xfc1f0000, RD_1|TRAP,		0,		I2,		0,	I37 }, /* tgei */
 {"tge",			"s,I",		0,    (int) M_TGE_I,    INSN_MACRO,		0,		I2,		0,	0 },
-{"tgeiu",		"s,j",		0x04090000, 0xfc1f0000, RD_1|TRAP,		0,		I2,		0,	0 },
+{"tgeiu",		"s,j",		0x04090000, 0xfc1f0000, RD_1|TRAP,		0,		I2,		0,	I37 },
 {"tgeu",		"s,t",		0x00000031, 0xfc00ffff, RD_1|RD_2|TRAP,		0,		I2,		0,	0 },
 {"tgeu",		"s,t,q",	0x00000031, 0xfc00003f, RD_1|RD_2|TRAP,		0,		I2,		0,	0 },
-{"tgeu",		"s,j",		0x04090000, 0xfc1f0000, RD_1|TRAP,		0,		I2,		0,	0 }, /* tgeiu */
+{"tgeu",		"s,j",		0x04090000, 0xfc1f0000, RD_1|TRAP,		0,		I2,		0,	I37 }, /* tgeiu */
 {"tgeu",		"s,I",		0,    (int) M_TGEU_I,	INSN_MACRO,		0,		I2,		0,	0 },
-{"tlbinv",		"",		0x42000003, 0xffffffff, INSN_TLB,       	0,		0,		TLBINV,	0 },
-{"tlbinvf",		"",		0x42000004, 0xffffffff, INSN_TLB,       	0,		0,		TLBINV,	0 },
+{"tlbinv",		"",		0x42000003, 0xffffffff, INSN_TLB,       	0,		I37,		TLBINV,	0 },
+{"tlbinvf",		"",		0x42000004, 0xffffffff, INSN_TLB,       	0,		I37,		TLBINV,	0 },
 {"tlbp",		"",		0x42000008, 0xffffffff, INSN_TLB,       	0,		I1,		0,	0 },
 {"tlbr",		"",		0x42000001, 0xffffffff, INSN_TLB,       	0,		I1,		0,	0 },
 {"tlbwi",		"",		0x42000002, 0xffffffff, INSN_TLB,       	0,		I1,		0,	0 },
@@ -1910,20 +1992,20 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"tlbginvf",		"",		0x4200000c, 0xffffffff, INSN_TLB,       	0,		0,		IVIRT,	0 },
 {"tlbgwr",		"",		0x4200000e, 0xffffffff, INSN_TLB,       	0,		0,		IVIRT,	0 },
 {"tlbgp",		"",		0x42000010, 0xffffffff, INSN_TLB,       	0,		0,		IVIRT,	0 },
-{"tlti",		"s,j",		0x040a0000, 0xfc1f0000,	RD_1|TRAP,		0,		I2,		0,	0 },
+{"tlti",		"s,j",		0x040a0000, 0xfc1f0000,	RD_1|TRAP,		0,		I2,		0,	I37 },
 {"tlt",			"s,t",		0x00000032, 0xfc00ffff, RD_1|RD_2|TRAP,		0,		I2,		0,	0 },
 {"tlt",			"s,t,q",	0x00000032, 0xfc00003f, RD_1|RD_2|TRAP,		0,		I2,		0,	0 },
-{"tlt",			"s,j",		0x040a0000, 0xfc1f0000,	RD_1|TRAP,		0,		I2,		0,	0 }, /* tlti */
+{"tlt",			"s,j",		0x040a0000, 0xfc1f0000,	RD_1|TRAP,		0,		I2,		0,	I37 }, /* tlti */
 {"tlt",			"s,I",		0,    (int) M_TLT_I,	INSN_MACRO,		0,		I2,		0,	0 },
-{"tltiu",		"s,j",		0x040b0000, 0xfc1f0000, RD_1|TRAP,		0,		I2,		0,	0 },
+{"tltiu",		"s,j",		0x040b0000, 0xfc1f0000, RD_1|TRAP,		0,		I2,		0,	I37 },
 {"tltu",		"s,t",		0x00000033, 0xfc00ffff, RD_1|RD_2|TRAP,		0,		I2,		0,	0 },
 {"tltu",		"s,t,q",	0x00000033, 0xfc00003f, RD_1|RD_2|TRAP,		0,		I2,		0,	0 },
-{"tltu",		"s,j",		0x040b0000, 0xfc1f0000, RD_1|TRAP,		0,		I2,		0,	0 }, /* tltiu */
+{"tltu",		"s,j",		0x040b0000, 0xfc1f0000, RD_1|TRAP,		0,		I2,		0,	I37 }, /* tltiu */
 {"tltu",		"s,I",		0,    (int) M_TLTU_I,	INSN_MACRO,		0,		I2,		0,	0 },
-{"tnei",		"s,j",		0x040e0000, 0xfc1f0000, RD_1|TRAP,		0,		I2,		0,	0 },
+{"tnei",		"s,j",		0x040e0000, 0xfc1f0000, RD_1|TRAP,		0,		I2,		0,	I37 },
 {"tne",			"s,t",		0x00000036, 0xfc00ffff, RD_1|RD_2|TRAP,		0,		I2,		0,	0 },
 {"tne",			"s,t,q",	0x00000036, 0xfc00003f, RD_1|RD_2|TRAP,		0,		I2,		0,	0 },
-{"tne",			"s,j",		0x040e0000, 0xfc1f0000, RD_1|TRAP,		0,		I2,		0,	0 }, /* tnei */
+{"tne",			"s,j",		0x040e0000, 0xfc1f0000, RD_1|TRAP,		0,		I2,		0,	I37 }, /* tnei */
 {"tne",			"s,I",		0,    (int) M_TNE_I,	INSN_MACRO,		0,		I2,		0,	0 },
 {"trunc.l.d",		"D,S",		0x46200009, 0xffff003f, WR_1|RD_2|FP_D,		0,		I3_33,		0,	0 },
 {"trunc.l.s",		"D,S",		0x46000009, 0xffff003f,	WR_1|RD_2|FP_S|FP_D,	0,		I3_33,		0,	0 },
@@ -1934,13 +2016,13 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"trunc.w.s",		"D,S",		0x4600000d, 0xffff003f,	WR_1|RD_2|FP_S,		0,		I2,		0,	EE },
 {"trunc.w.s",		"D,S,x",	0x4600000d, 0xffff003f,	WR_1|RD_2|FP_S,		0,		I2,		0,	EE },
 {"trunc.w.s",		"D,S,t",	0,    (int) M_TRUNCWS,	INSN_MACRO,		INSN2_M_FP_S,	I1,		0,	EE },
-{"uld",			"t,A(b)",	0,    (int) M_ULD_AB,	INSN_MACRO,		0,		I3,		0,	0 },
-{"ulh",			"t,A(b)",	0,    (int) M_ULH_AB,	INSN_MACRO,		0,		I1,		0,	0 },
-{"ulhu",		"t,A(b)",	0,    (int) M_ULHU_AB,	INSN_MACRO,		0,		I1,		0,	0 },
-{"ulw",			"t,A(b)",	0,    (int) M_ULW_AB,	INSN_MACRO,		0,		I1,		0,	0 },
-{"usd",			"t,A(b)",	0,    (int) M_USD_AB,	INSN_MACRO,		0,		I3,		0,	0 },
-{"ush",			"t,A(b)",	0,    (int) M_USH_AB,	INSN_MACRO,		0,		I1,		0,	0 },
-{"usw",			"t,A(b)",	0,    (int) M_USW_AB,	INSN_MACRO,		0,		I1,		0,	0 },
+{"uld",			"t,A(b)",	0,    (int) M_ULD_AB,	INSN_MACRO,		0,		I3,		0,	I69 },
+{"ulh",			"t,A(b)",	0,    (int) M_ULH_AB,	INSN_MACRO,		0,		I1,		0,	I37 },
+{"ulhu",		"t,A(b)",	0,    (int) M_ULHU_AB,	INSN_MACRO,		0,		I1,		0,	I37 },
+{"ulw",			"t,A(b)",	0,    (int) M_ULW_AB,	INSN_MACRO,		0,		I1,		0,	I37 },
+{"usd",			"t,A(b)",	0,    (int) M_USD_AB,	INSN_MACRO,		0,		I3,		0,	I69 },
+{"ush",			"t,A(b)",	0,    (int) M_USH_AB,	INSN_MACRO,		0,		I1,		0,	I37 },
+{"usw",			"t,A(b)",	0,    (int) M_USW_AB,	INSN_MACRO,		0,		I1,		0,	I37 },
 {"v3mulu",		"d,v,t",	0x70000011, 0xfc0007ff, WR_1|RD_2|RD_3,		0,		IOCT,		0,	0 },
 {"vmm0",		"d,v,t",	0x70000010, 0xfc0007ff, WR_1|RD_2|RD_3,		0,		IOCT,		0,	0 },
 {"vmulu",		"d,v,t",	0x7000000f, 0xfc0007ff, WR_1|RD_2|RD_3,		0,		IOCT,		0,	0 },
@@ -1976,14 +2058,16 @@ const struct mips_opcode mips_builtin_opcodes[] =
 
 /* Coprocessor 2 move/branch operations overlap with VR5400 .ob format
    instructions so they are here for the latters to take precedence.  */
-{"bc2f",		"p",		0x49000000, 0xffff0000,	RD_CC|CBD,		0,		I1,		0,	IOCT|IOCTP|IOCT2 },
-{"bc2f",		"N,p",		0x49000000, 0xffe30000,	RD_CC|CBD,		0,		I32,		0,	IOCT|IOCTP|IOCT2 },
-{"bc2fl",		"p",		0x49020000, 0xffff0000,	RD_CC|CBL,		0,		I2|T3,		0,	IOCT|IOCTP|IOCT2 },
-{"bc2fl",		"N,p",		0x49020000, 0xffe30000,	RD_CC|CBL,		0,		I32,		0,	IOCT|IOCTP|IOCT2 },
-{"bc2t",		"p",		0x49010000, 0xffff0000,	RD_CC|CBD,		0,		I1,		0,	IOCT|IOCTP|IOCT2 },
-{"bc2t",		"N,p",		0x49010000, 0xffe30000,	RD_CC|CBD,		0,		I32,		0,	IOCT|IOCTP|IOCT2 },
-{"bc2tl",		"p",		0x49030000, 0xffff0000,	RD_CC|CBL,		0,		I2|T3,		0,	IOCT|IOCTP|IOCT2 },
-{"bc2tl",		"N,p",		0x49030000, 0xffe30000,	RD_CC|CBL,		0,		I32,		0,	IOCT|IOCTP|IOCT2 },
+{"bc2eqz",		"E,p",		0x49200000, 0xffe00000, RD_C2|CBD,		0,		I37,		0,	0 },
+{"bc2f",		"p",		0x49000000, 0xffff0000,	RD_CC|CBD,		0,		I1,		0,	IOCT|IOCTP|IOCT2|I37 },
+{"bc2f",		"N,p",		0x49000000, 0xffe30000,	RD_CC|CBD,		0,		I32,		0,	IOCT|IOCTP|IOCT2|I37 },
+{"bc2fl",		"p",		0x49020000, 0xffff0000,	RD_CC|CBL,		0,		I2|T3,		0,	IOCT|IOCTP|IOCT2|I37 },
+{"bc2fl",		"N,p",		0x49020000, 0xffe30000,	RD_CC|CBL,		0,		I32,		0,	IOCT|IOCTP|IOCT2|I37 },
+{"bc2nez",		"E,p",		0x49a00000, 0xffe00000, RD_C2|CBD,		0,		I37,		0,	0 },
+{"bc2t",		"p",		0x49010000, 0xffff0000,	RD_CC|CBD,		0,		I1,		0,	IOCT|IOCTP|IOCT2|I37 },
+{"bc2t",		"N,p",		0x49010000, 0xffe30000,	RD_CC|CBD,		0,		I32,		0,	IOCT|IOCTP|IOCT2|I37 },
+{"bc2tl",		"p",		0x49030000, 0xffff0000,	RD_CC|CBL,		0,		I2|T3,		0,	IOCT|IOCTP|IOCT2|I37 },
+{"bc2tl",		"N,p",		0x49030000, 0xffe30000,	RD_CC|CBL,		0,		I32,		0,	IOCT|IOCTP|IOCT2|I37 },
 {"cfc2",		"t,G",		0x48400000, 0xffe007ff,	WR_1|RD_C2|LC,		0,		I1,		0,	IOCT|IOCTP|IOCT2|EE },
 {"cfc2",		"t,+9",		0x48400000, 0xffe007ff,	WR_1|RD_C2|LC,		0,		EE,		0,	0 },
 {"cfc2.i",		"t,+9",		0x48400001, 0xffe007ff, WR_1|RD_C2|LC,		0,		EE,		0,	0 },
@@ -2016,18 +2100,18 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"qmtc2.ni",		"t,+6",		0x48a00000, 0xffe007ff,	RD_1|WR_C2,		0,		EE,		0,	0 },
 /* Coprocessor 3 move/branch operations overlap with MIPS IV COP1X 
    instructions, so they are here for the latters to take precedence.  */
-{"bc3f",		"p",		0x4d000000, 0xffff0000,	RD_CC|CBD,		0,		I1,		0,	IOCT|IOCTP|IOCT2|EE },
-{"bc3fl",		"p",		0x4d020000, 0xffff0000,	RD_CC|CBL,		0,		I2|T3,		0,	IOCT|IOCTP|IOCT2|EE },
-{"bc3t",		"p",		0x4d010000, 0xffff0000,	RD_CC|CBD,		0,		I1,		0,	IOCT|IOCTP|IOCT2|EE },
-{"bc3tl",		"p",		0x4d030000, 0xffff0000,	RD_CC|CBL,		0,		I2|T3,		0,	IOCT|IOCTP|IOCT2|EE },
-{"cfc3",		"t,G",		0x4c400000, 0xffe007ff,	WR_1|RD_C3|LC,		0,		I1,		0,	IOCT|IOCTP|IOCT2|EE },
-{"ctc3",		"t,G",		0x4cc00000, 0xffe007ff,	RD_1|WR_CC|CM,		0,		I1,		0,	IOCT|IOCTP|IOCT2|EE },
-{"dmfc3",		"t,G",		0x4c200000, 0xffe007ff,	WR_1|RD_C3|LC,		0,		I3,		0,	IOCT|IOCTP|IOCT2|EE },
-{"dmtc3",		"t,G",		0x4ca00000, 0xffe007ff,	RD_1|WR_C3|WR_CC|CM,	0,		I3,		0,	IOCT|IOCTP|IOCT2|EE },
-{"mfc3",		"t,G",		0x4c000000, 0xffe007ff,	WR_1|RD_C3|LC,		0,		I1,		0,	IOCT|IOCTP|IOCT2|EE },
-{"mfc3",		"t,G,H",	0x4c000000, 0xffe007f8,	WR_1|RD_C3|LC,		0,		I32,		0,	IOCT|IOCTP|IOCT2|EE },
-{"mtc3",		"t,G",		0x4c800000, 0xffe007ff,	RD_1|WR_C3|WR_CC|CM,	0,		I1,		0,	IOCT|IOCTP|IOCT2|EE },
-{"mtc3",		"t,G,H",	0x4c800000, 0xffe007f8,	RD_1|WR_C3|WR_CC|CM,	0,		I32,		0,	IOCT|IOCTP|IOCT2|EE },
+{"bc3f",		"p",		0x4d000000, 0xffff0000,	RD_CC|CBD,		0,		I1,		0,	IOCT|IOCTP|IOCT2|EE|I37 },
+{"bc3fl",		"p",		0x4d020000, 0xffff0000,	RD_CC|CBL,		0,		I2|T3,		0,	IOCT|IOCTP|IOCT2|EE|I37 },
+{"bc3t",		"p",		0x4d010000, 0xffff0000,	RD_CC|CBD,		0,		I1,		0,	IOCT|IOCTP|IOCT2|EE|I37 },
+{"bc3tl",		"p",		0x4d030000, 0xffff0000,	RD_CC|CBL,		0,		I2|T3,		0,	IOCT|IOCTP|IOCT2|EE|I37 },
+{"cfc3",		"t,G",		0x4c400000, 0xffe007ff,	WR_1|RD_C3|LC,		0,		I1,		0,	IOCT|IOCTP|IOCT2|EE|I37 },
+{"ctc3",		"t,G",		0x4cc00000, 0xffe007ff,	RD_1|WR_CC|CM,		0,		I1,		0,	IOCT|IOCTP|IOCT2|EE|I37 },
+{"dmfc3",		"t,G",		0x4c200000, 0xffe007ff,	WR_1|RD_C3|LC,		0,		I3,		0,	IOCT|IOCTP|IOCT2|EE|I37 },
+{"dmtc3",		"t,G",		0x4ca00000, 0xffe007ff,	RD_1|WR_C3|WR_CC|CM,	0,		I3,		0,	IOCT|IOCTP|IOCT2|EE|I37 },
+{"mfc3",		"t,G",		0x4c000000, 0xffe007ff,	WR_1|RD_C3|LC,		0,		I1,		0,	IOCT|IOCTP|IOCT2|EE|I37 },
+{"mfc3",		"t,G,H",	0x4c000000, 0xffe007f8,	WR_1|RD_C3|LC,		0,		I32,		0,	IOCT|IOCTP|IOCT2|EE|I37 },
+{"mtc3",		"t,G",		0x4c800000, 0xffe007ff,	RD_1|WR_C3|WR_CC|CM,	0,		I1,		0,	IOCT|IOCTP|IOCT2|EE|I37 },
+{"mtc3",		"t,G,H",	0x4c800000, 0xffe007f8,	RD_1|WR_C3|WR_CC|CM,	0,		I32,		0,	IOCT|IOCTP|IOCT2|EE|I37 },
 
   /* Conflicts with the 4650's "mul" instruction.  Nobody's using the
      4010 any more, so move this insn out of the way.  If the object
@@ -2314,10 +2398,10 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"dpsqx_s.w.ph",	"7,s,t",	0x7c000670, 0xfc00e7ff, RD_2|RD_3|MOD_a,	0,              0,		D33,	0 },
 {"dpsqx_sa.w.ph",	"7,s,t",	0x7c0006f0, 0xfc00e7ff, RD_2|RD_3|MOD_a,	0,              0,		D33,	0 },
 /* Move bc0* after mftr and mttr to avoid opcode collision.  */
-{"bc0f",		"p",		0x41000000, 0xffff0000,	RD_CC|CBD,		0,		I1,		0,	IOCT|IOCTP|IOCT2 },
-{"bc0fl",		"p",		0x41020000, 0xffff0000,	RD_CC|CBL,		0,		I2|T3,		0,	IOCT|IOCTP|IOCT2 },
-{"bc0t",		"p",		0x41010000, 0xffff0000,	RD_CC|CBD,		0,		I1,		0,	IOCT|IOCTP|IOCT2 },
-{"bc0tl",		"p",		0x41030000, 0xffff0000,	RD_CC|CBL,		0,		I2|T3,		0,	IOCT|IOCTP|IOCT2 },
+{"bc0f",		"p",		0x41000000, 0xffff0000,	RD_CC|CBD,		0,		I1,		0,	IOCT|IOCTP|IOCT2|I37 },
+{"bc0fl",		"p",		0x41020000, 0xffff0000,	RD_CC|CBL,		0,		I2|T3,		0,	IOCT|IOCTP|IOCT2|I37 },
+{"bc0t",		"p",		0x41010000, 0xffff0000,	RD_CC|CBD,		0,		I1,		0,	IOCT|IOCTP|IOCT2|I37 },
+{"bc0tl",		"p",		0x41030000, 0xffff0000,	RD_CC|CBL,		0,		I2|T3,		0,	IOCT|IOCTP|IOCT2|I37 },
 /* ST Microelectronics Loongson-2E and -2F.  */
 {"mult.g",		"d,s,t",	0x7c000018, 0xfc0007ff,	WR_1|RD_2|RD_3,		0,		IL2E,		0,	0 },
 {"mult.g",		"d,s,t",	0x70000010, 0xfc0007ff,	WR_1|RD_2|RD_3,		0,		IL2F,		0,	0 },
@@ -2502,10 +2586,10 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"lle",			"t,A(b)",	0,    (int) M_LLE_AB,	INSN_MACRO,		0,		0,		EVA,	0 },
 {"lwe",			"t,+j(b)",	0x7c00002f, 0xfc00007f, WR_1|RD_3|LM,		0,		0,		EVA,	0 },
 {"lwe",			"t,A(b)",	0,    (int) M_LWE_AB,	INSN_MACRO,		0,		0,		EVA,	0 },
-{"lwle",		"t,+j(b)",	0x7c000019, 0xfc00007f, WR_1|RD_3|LM,		0,		0,		EVA,	0 },
-{"lwle",		"t,A(b)",	0,    (int) M_LWLE_AB,	INSN_MACRO,		0,		0,		EVA,	0 },
-{"lwre",		"t,+j(b)",	0x7c00001a, 0xfc00007f, WR_1|RD_3|LM,		0,		0,		EVA,	0 },
-{"lwre",		"t,A(b)",	0,    (int) M_LWRE_AB,	INSN_MACRO,		0,		0,		EVA,	0 },
+{"lwle",		"t,+j(b)",	0x7c000019, 0xfc00007f, WR_1|RD_3|LM,		0,		0,		EVA,	I37 },
+{"lwle",		"t,A(b)",	0,    (int) M_LWLE_AB,	INSN_MACRO,		0,		0,		EVA,	I37 },
+{"lwre",		"t,+j(b)",	0x7c00001a, 0xfc00007f, WR_1|RD_3|LM,		0,		0,		EVA,	I37 },
+{"lwre",		"t,A(b)",	0,    (int) M_LWRE_AB,	INSN_MACRO,		0,		0,		EVA,	I37 },
 {"sbe",			"t,+j(b)",	0x7c00001c, 0xfc00007f, RD_1|RD_3|SM,		0,		0,		EVA,	0 },
 {"sbe",			"t,A(b)",	0,    (int) M_SBE_AB,	INSN_MACRO,		0,		0,		EVA,	0 },
 {"sce",			"t,+j(b)",	0x7c00001e, 0xfc00007f, MOD_1|RD_3|SM,		0,		0,		EVA,	0 },
@@ -2514,10 +2598,10 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"she",			"t,A(b)",	0,    (int) M_SHE_AB,	INSN_MACRO,		0,		0,		EVA,	0 },
 {"swe",			"t,+j(b)",	0x7c00001f, 0xfc00007f, RD_1|RD_3|SM,		0,		0,		EVA,	0 },
 {"swe",			"t,A(b)",	0,    (int) M_SWE_AB,	INSN_MACRO,		0,		0,		EVA,	0 },
-{"swle",		"t,+j(b)",	0x7c000021, 0xfc00007f, RD_1|RD_3|SM,		0,		0,		EVA,	0 },
-{"swle",		"t,A(b)",	0,    (int) M_SWLE_AB,	INSN_MACRO,		0,		0,		EVA,	0 },
-{"swre",		"t,+j(b)",	0x7c000022, 0xfc00007f, RD_1|RD_3|SM,		0,		0,		EVA,	0 },
-{"swre",		"t,A(b)",	0,    (int) M_SWRE_AB,	INSN_MACRO,		0,		0,		EVA,	0 },
+{"swle",		"t,+j(b)",	0x7c000021, 0xfc00007f, RD_1|RD_3|SM,		0,		0,		EVA,	I37 },
+{"swle",		"t,A(b)",	0,    (int) M_SWLE_AB,	INSN_MACRO,		0,		0,		EVA,	I37 },
+{"swre",		"t,+j(b)",	0x7c000022, 0xfc00007f, RD_1|RD_3|SM,		0,		0,		EVA,	I37 },
+{"swre",		"t,A(b)",	0,    (int) M_SWRE_AB,	INSN_MACRO,		0,		0,		EVA,	I37 },
 {"cachee",		"k,+j(b)",	0x7c00001b, 0xfc00007f, RD_3,			0,		0,		EVA,	0 },
 {"cachee",		"k,A(b)",	0,    (int) M_CACHEE_AB,INSN_MACRO,		0,		0,		EVA,	0 },
 {"prefe",		"k,+j(b)",	0x7c000023, 0xfc00007f, RD_3|LM,		0,		0,		EVA,	0 },
@@ -3053,8 +3137,6 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"ctcmsa",		"+l,d",		0x783e0019, 0xffff003f,	RD_2|CM,		0,		0,		MSA,	0 },
 {"cfcmsa",		"+k,+n",	0x787e0019, 0xffff003f,	WR_1|CM,		0,		0,		MSA,	0 },
 {"move.v",		"+d,+e",	0x78be0019, 0xffff003f,	WR_1|RD_2,		0,		0,		MSA,	0 },
-{"lsa",			"d,v,t,+~",	0x00000005, 0xfc00073f,	WR_1|RD_2|RD_3,		0,		0,		MSA,	0 },
-{"dlsa",		"d,v,t,+~",	0x00000015, 0xfc00073f,	WR_1|RD_2|RD_3,		0,		0,		MSA64,	0 },
 
 /* User Defined Instruction.  */
 {"udi0",		"s,t,d,+1",	0x70000010, 0xfc00003f,	UDI,			0,		I33,		0,	0 },
@@ -3121,6 +3203,124 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"udi15",		"s,t,+2",	0x7000001f, 0xfc00003f,	UDI,			0,		I33,		0,	0 },
 {"udi15",		"s,+3",		0x7000001f, 0xfc00003f,	UDI,			0,		I33,		0,	0 },
 {"udi15",		"+4",		0x7000001f, 0xfc00003f,	UDI,			0,		I33,		0,	0 },
+{"lsa",			"d,v,t,+~",	0x00000005, 0xfc00073f,	WR_1|RD_2|RD_3,		0,		I37,		MSA,	0 },
+{"dlsa",		"d,v,t,+~",	0x00000015, 0xfc00073f,	WR_1|RD_2|RD_3,		0,		I69,		MSA64,	0 },
+/* MIPS r6.  */
+
+{"aui",			"t,s,u",	0x3c000000, 0xfc000000,	WR_1|RD_2,		0,		I37,		0,	0 },
+{"auipc",		"s,u",		0xec1e0000, 0xfc1f0000, WR_1,			RD_pc,		I37,		0,	0 },
+{"daui",		"t,s,u",	0x74000000, 0xfc000000,	WR_1|RD_2,		0,		I37,		0,	0 },
+{"dahi",		"s,-d,u",	0x04060000, 0xfc1f0000,	MOD_1,			0,		I69,		0,	0 },
+{"dati",		"s,-d,u",	0x041e0000, 0xfc1f0000,	MOD_1,			0,		I69,		0,	0 },
+
+{"align",		"d,s,t,+I",	0x7c000220, 0xfc00073f,	WR_1|RD_2|RD_3,		0,		I37,		0,	0 },
+{"dalign",		"d,s,t,+O",	0x7c000224, 0xfc00063f,	WR_1|RD_2|RD_3,		0,		I69,		0,	0 },
+{"bitswap",		"d,t",		0x7c000020, 0xffe007ff,	WR_1|RD_2,		0,		I37,		0,	0 },
+{"dbitswap",		"d,t",		0x7c000024, 0xffe007ff,	WR_1|RD_2,		0,		I69,		0,	0 },
+
+{"bovc",		"s,-w,p",	0x20000000, 0xfc000000,	RD_1|RD_2|NODS,		FS,		I37,		0,	0 },
+{"bovc",		"t,-x,p",	0x20000000, 0xfc000000,	RD_1|RD_2|NODS,		FS|INSN2_ALIAS,	I37,		0,	0 },
+{"beqzalc",		"-t,p",		0x20000000, 0xffe00000,	RD_1|WR_31|NODS,	FS,		I37,		0,	0 },
+{"beqc",		"-s,-u,p",	0x20000000, 0xfc000000,	RD_1|RD_2|NODS,		FS,		I37,		0,	0 },
+{"beqc",		"t,-y,p",	0x20000000, 0xfc000000,	RD_1|RD_2|NODS,		FS|INSN2_ALIAS,	I37,		0,	0 },
+{"bnvc",		"s,-w,p",	0x60000000, 0xfc000000,	RD_1|RD_2|NODS,		FS,		I37,		0,	0 },
+{"bnvc",		"t,-x,p",	0x60000000, 0xfc000000,	RD_1|RD_2|NODS,		FS|INSN2_ALIAS,	I37,		0,	0 },
+{"bnezalc",		"-t,p",		0x60000000, 0xffe00000,	RD_1|WR_31|NODS,	FS,		I37,		0,	0 },
+{"bnec",		"-s,-u,p",	0x60000000, 0xfc000000,	RD_1|RD_2|NODS,		FS,		I37,		0,	0 },
+{"bnec",		"t,-y,p",	0x60000000, 0xfc000000,	RD_1|RD_2|NODS,		FS|INSN2_ALIAS,	I37,		0,	0 },
+
+{"blezc",		"-t,p",		0x58000000, 0xffe00000,	RD_1|NODS,		FS,		I37,		0,	0 },
+{"bgezc",		"+;,p",		0x58000000, 0xfc000000,	RD_1|NODS,		FS,		I37,		0,	0 },
+{"bgec",		"-s,-v,p",	0x58000000, 0xfc000000,	RD_1|RD_2|NODS,		FS,		I37,		0,	0 },
+{"bgtzc",		"-t,p",		0x5c000000, 0xffe00000,	RD_1|NODS,		FS,		I37,		0,	0 },
+{"bltzc",		"+;,p",		0x5c000000, 0xfc000000,	RD_1|NODS,		FS,		I37,		0,	0 },
+{"bltc",		"-s,-v,p",	0x5c000000, 0xfc000000,	RD_1|RD_2|NODS,		FS,		I37,		0,	0 },
+{"blezalc",		"-t,p",		0x18000000, 0xffe00000,	RD_1|WR_31|NODS,	FS,		I37,		0,	0 },
+{"bgezalc",		"+;,p",		0x18000000, 0xfc000000,	RD_1|WR_31|NODS,	FS,		I37,		0,	0 },
+{"bgeuc",		"-s,-v,p",	0x18000000, 0xfc000000,	RD_1|RD_2|NODS,		FS,		I37,		0,	0 },
+{"bgtzalc",		"-t,p",		0x1c000000, 0xffe00000,	RD_1|WR_31|NODS,	FS,		I37,		0,	0 },
+{"bltzalc",		"+;,p",		0x1c000000, 0xfc000000,	RD_1|WR_31|NODS,	FS,		I37,		0,	0 },
+{"bltuc",		"-s,-v,p",	0x1c000000, 0xfc000000,	RD_1|RD_2|NODS,		FS,		I37,		0,	0 },
+
+{"beqzc",		"-s,+\"",	0xd8000000, 0xfc000000,	RD_1|NODS,		FS,		I37,		0,	0 },
+{"jrc",			"t",		0xd8000000, 0xffe0ffff,	RD_1|NODS,		INSN2_ALIAS,	I37,		0,	0 },
+{"jic",			"t,j",		0xd8000000, 0xffe00000,	RD_1|NODS,		0,		I37,		0,	0 },
+
+{"bnezc",		"-s,+\"",	0xf8000000, 0xfc000000,	RD_1|NODS,		FS,		I37,		0,	0 },
+{"jialc",		"t,j",		0xf8000000, 0xffe00000,	RD_1|NODS,		0,		I37,		0,	0 },
+
+{"cmp.af.s",		"D,S,T",	0x46800000, 0xffe0003f,	WR_1|RD_2|RD_3|FP_S,	0,		I37,		0,	0 },
+{"cmp.af.d",		"D,S,T",	0x46a00000, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		I37,		0,	0 },
+{"cmp.eq.s",		"D,S,T",	0x46800002, 0xffe0003f,	WR_1|RD_2|RD_3|FP_S,	0,		I37,		0,	0 },
+{"cmp.eq.d",		"D,S,T",	0x46a00002, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		I37,		0,	0 },
+{"cmp.le.s",		"D,S,T",	0x46800006, 0xffe0003f,	WR_1|RD_2|RD_3|FP_S,	0,		I37,		0,	0 },
+{"cmp.le.d",		"D,S,T",	0x46a00006, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		I37,		0,	0 },
+{"cmp.lt.s",		"D,S,T",	0x46800004, 0xffe0003f,	WR_1|RD_2|RD_3|FP_S,	0,		I37,		0,	0 },
+{"cmp.lt.d",		"D,S,T",	0x46a00004, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		I37,		0,	0 },
+{"cmp.ne.s",		"D,S,T",	0x46800013, 0xffe0003f,	WR_1|RD_2|RD_3|FP_S,	0,		I37,		0,	0 },
+{"cmp.ne.d",		"D,S,T",	0x46a00013, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		I37,		0,	0 },
+{"cmp.or.s",		"D,S,T",	0x46800011, 0xffe0003f,	WR_1|RD_2|RD_3|FP_S,	0,		I37,		0,	0 },
+{"cmp.or.d",		"D,S,T",	0x46a00011, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		I37,		0,	0 },
+{"cmp.ueq.s",		"D,S,T",	0x46800003, 0xffe0003f,	WR_1|RD_2|RD_3|FP_S,	0,		I37,		0,	0 },
+{"cmp.ueq.d",		"D,S,T",	0x46a00003, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		I37,		0,	0 },
+{"cmp.ule.s",		"D,S,T",	0x46800007, 0xffe0003f,	WR_1|RD_2|RD_3|FP_S,	0,		I37,		0,	0 },
+{"cmp.ule.d",		"D,S,T",	0x46a00007, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		I37,		0,	0 },
+{"cmp.ult.s",		"D,S,T",	0x46800005, 0xffe0003f,	WR_1|RD_2|RD_3|FP_S,	0,		I37,		0,	0 },
+{"cmp.ult.d",		"D,S,T",	0x46a00005, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		I37,		0,	0 },
+{"cmp.un.s",		"D,S,T",	0x46800001, 0xffe0003f,	WR_1|RD_2|RD_3|FP_S,	0,		I37,		0,	0 },
+{"cmp.un.d",		"D,S,T",	0x46a00001, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		I37,		0,	0 },
+{"cmp.une.s",		"D,S,T",	0x46800012, 0xffe0003f,	WR_1|RD_2|RD_3|FP_S,	0,		I37,		0,	0 },
+{"cmp.une.d",		"D,S,T",	0x46a00012, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		I37,		0,	0 },
+{"cmp.saf.s",		"D,S,T",	0x46800008, 0xffe0003f,	WR_1|RD_2|RD_3|FP_S,	0,		I37,		0,	0 },
+{"cmp.saf.d",		"D,S,T",	0x46a00008, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		I37,		0,	0 },
+{"cmp.seq.s",		"D,S,T",	0x4680000a, 0xffe0003f,	WR_1|RD_2|RD_3|FP_S,	0,		I37,		0,	0 },
+{"cmp.seq.d",		"D,S,T",	0x46a0000a, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		I37,		0,	0 },
+{"cmp.sle.s",		"D,S,T",	0x4680000e, 0xffe0003f,	WR_1|RD_2|RD_3|FP_S,	0,		I37,		0,	0 },
+{"cmp.sle.d",		"D,S,T",	0x46a0000e, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		I37,		0,	0 },
+{"cmp.slt.s",		"D,S,T",	0x4680000c, 0xffe0003f,	WR_1|RD_2|RD_3|FP_S,	0,		I37,		0,	0 },
+{"cmp.slt.d",		"D,S,T",	0x46a0000c, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		I37,		0,	0 },
+{"cmp.sne.s",		"D,S,T",	0x4680001b, 0xffe0003f,	WR_1|RD_2|RD_3|FP_S,	0,		I37,		0,	0 },
+{"cmp.sne.d",		"D,S,T",	0x46a0001b, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		I37,		0,	0 },
+{"cmp.sor.s",		"D,S,T",	0x46800019, 0xffe0003f,	WR_1|RD_2|RD_3|FP_S,	0,		I37,		0,	0 },
+{"cmp.sor.d",		"D,S,T",	0x46a00019, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		I37,		0,	0 },
+{"cmp.sueq.s",		"D,S,T",	0x4680000b, 0xffe0003f,	WR_1|RD_2|RD_3|FP_S,	0,		I37,		0,	0 },
+{"cmp.sueq.d",		"D,S,T",	0x46a0000b, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		I37,		0,	0 },
+{"cmp.sule.s",		"D,S,T",	0x4680000f, 0xffe0003f,	WR_1|RD_2|RD_3|FP_S,	0,		I37,		0,	0 },
+{"cmp.sule.d",		"D,S,T",	0x46a0000f, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		I37,		0,	0 },
+{"cmp.sult.s",		"D,S,T",	0x4680000d, 0xffe0003f,	WR_1|RD_2|RD_3|FP_S,	0,		I37,		0,	0 },
+{"cmp.sult.d",		"D,S,T",	0x46a0000d, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		I37,		0,	0 },
+{"cmp.sun.s",		"D,S,T",	0x46800009, 0xffe0003f,	WR_1|RD_2|RD_3|FP_S,	0,		I37,		0,	0 },
+{"cmp.sun.d",		"D,S,T",	0x46a00009, 0xffe0003f,	WR_1|RD_2|RD_3|FP_S,	0,		I37,		0,	0 },
+{"cmp.sune.s",		"D,S,T",	0x4680001a, 0xffe0003f,	WR_1|RD_2|RD_3|FP_S,	0,		I37,		0,	0 },
+{"cmp.sune.d",		"D,S,T",	0x46a0001a, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		I37,		0,	0 },
+
+{"maddf.s",		"D,S,T",	0x46000018, 0xffe0003f,	MOD_1|RD_2|RD_3|FP_S,	0,		I37,		0,	0 },
+{"msubf.s",		"D,S,T",	0x46000019, 0xffe0003f,	MOD_1|RD_2|RD_3|FP_S,	0,		I37,		0,	0 },
+{"maddf.d",		"D,S,T",	0x46200018, 0xffe0003f,	MOD_1|RD_2|RD_3|FP_D,	0,		I37,		0,	0 },
+{"msubf.d",		"D,S,T",	0x46200019, 0xffe0003f,	MOD_1|RD_2|RD_3|FP_D,	0,		I37,		0,	0 },
+
+{"rint.s",		"D,S",		0x4600001a, 0xffff003f,	WR_1|RD_2|FP_S,		0,		I37,		0,	0 },
+{"rint.d",		"D,S",		0x4620001a, 0xffff003f,	WR_1|RD_2|FP_D,		0,		I37,		0,	0 },
+{"class.s",		"D,S",		0x4600001b, 0xffff003f,	WR_1|RD_2|FP_S,		0,		I37,		0,	0 },
+{"class.d",		"D,S",		0x4620001b, 0xffff003f,	WR_1|RD_2|FP_D,		0,		I37,		0,	0 },
+{"min.d",		"D,S,T",	0x4620001c, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		I37,		0,	0 },
+{"max.d",		"D,S,T",	0x4620001e, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		I37,		0,	0 },
+{"mina.s",		"D,S,T",	0x4600001d, 0xffe0003f,	WR_1|RD_2|RD_3|FP_S,	0,		I37,		0,	0 },
+{"mina.d",		"D,S,T",	0x4620001d, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		I37,		0,	0 },
+{"maxa.s",		"D,S,T",	0x4600001f, 0xffe0003f,	WR_1|RD_2|RD_3|FP_S,	0,		I37,		0,	0 },
+{"maxa.d",		"D,S,T",	0x4620001f, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		I37,		0,	0 },
+
+{"sel.s",		"D,S,T",	0x46000010, 0xffe0003f, MOD_1|RD_2|RD_3|FP_S,   0,		I37,		0,	0 },
+{"sel.d",		"D,S,T",	0x46200010, 0xffe0003f, MOD_1|RD_2|RD_3|FP_D,   0,		I37,		0,	0 },
+{"selnez",		"d,s,t",	0x00000037, 0xfc0007ff, WR_1|RD_2|RD_3, 	0,		I37,		0,	0 },
+{"selnez.s",		"D,S,T",	0x46000017, 0xffe0003f, WR_1|RD_2|RD_3|FP_S,	0,		I37,		0,	0 },
+{"selnez.d",		"D,S,T",	0x46200017, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,	0,		I37,		0,	0 },
+{"seleqz",		"d,s,t",	0x00000035, 0xfc0007ff, WR_1|RD_2|RD_3, 	0,		I37,		0,	0 },
+{"seleqz.s",		"D,S,T",	0x46000014, 0xffe0003f, WR_1|RD_2|RD_3|FP_S,	0,		I37,		0,	0 },
+{"seleqz.d",		"D,S,T",	0x46200014, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,	0,		I37,		0,	0 },
+
+{"aluipc",		"s,u",		0xec1f0000, 0xfc1f0000, WR_1,			RD_pc,		I37,		0,	0 },
+
 /* No hazard protection on coprocessor instructions--they shouldn't
    change the state of the processor and if they do it's up to the
    user to put in nops as necessary.  These are at the end so that the