Adds support for following CPUs to the ARM and Aarch64 assemblers: Cortex-A77, Cortex-A76AE, Cortex-A34, Cortex-A65, and Cortex-A65AE.

Related specifications can be found at
https://developer.arm.com/ip-products/processors.

gas	* NEWS: Mention the Arm and AArch64 new processors.
	* config/tc-aarch64.c: New entries for Cortex-A34, Cortex-A65,
	Cortex-A77, cortex-A65AE, and Cortex-A76AE.
	* doc/c-aarch64.texi: Document new CPUs.
	* testsuite/gas/aarch64/cpu-cortex-a34.d: New test.
	* testsuite/gas/aarch64/cpu-cortex-a65.d: New test.
	* testsuite/gas/aarch64/cpu-cortex-a65ae.d: New test.
	* testsuite/gas/aarch64/cpu-cortex-a76ae.d: New test.
	* testsuite/gas/aarch64/cpu-cortex-a77.d: New test.
	* testsuite/gas/aarch64/nop-asm.s: New test.

bfd	* cpu-aarch64.c: New entries for Cortex-A34, Cortex-A65,
	 Cortex-A77, cortex-A65AE, and Cortex-A76AE.

14 files changed, 122 insertions, 4 deletions

diff --git a/bfd/ChangeLog b/bfd/ChangeLog
index e566656e613..97d37265163 100644
--- a/bfd/ChangeLog
+++ b/bfd/ChangeLog
@@ -1,3 +1,8 @@
+2019-08-20  Dennis Zhang  <dennis.zhang@arm.com>
+
+	* cpu-aarch64.c: New entries for Cortex-A34, Cortex-A65,
+	 Cortex-A77, cortex-A65AE, and Cortex-A76AE.
+
 2019-08-20  Tamar Christina  <tamar.christina@arm.com>
 
 	* elf32-arm.c (elf32_thumb2_plt_entry, elf32_arm_plt_thumb_stub,
diff --git a/bfd/cpu-aarch64.c b/bfd/cpu-aarch64.c
index e895f151c82..eed1c3d9dcd 100644
--- a/bfd/cpu-aarch64.c
+++ b/bfd/cpu-aarch64.c
@@ -68,10 +68,11 @@ static struct
 }
 processors[] =
 {
-  /* These two are example CPUs supported in GCC, once we have real
-     CPUs they will be removed.  */
-  { bfd_mach_aarch64, "example-1" },
-  { bfd_mach_aarch64, "example-2" }
+  { bfd_mach_aarch64,	  "cortex-a34"	    },
+  { bfd_mach_aarch64,	  "cortex-a65"	    },
+  { bfd_mach_aarch64,	  "cortex-a65ae"    },
+  { bfd_mach_aarch64,	  "cortex-a76ae"    },
+  { bfd_mach_aarch64,	  "cortex-a77"	    }
 };
 
 static bfd_boolean
diff --git a/gas/ChangeLog b/gas/ChangeLog
index 966bc172710..5ae7155f771 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,16 @@
+2019-08-20  Dennis Zhang  <dennis.zhang@arm.com>
+
+	* NEWS: Mention the Arm and AArch64 new processors.
+	* config/tc-aarch64.c: New entries for Cortex-A34, Cortex-A65,
+	Cortex-A77, cortex-A65AE, and Cortex-A76AE.
+	* doc/c-aarch64.texi: Document new CPUs.
+	* testsuite/gas/aarch64/cpu-cortex-a34.d: New test.
+	* testsuite/gas/aarch64/cpu-cortex-a65.d: New test.
+	* testsuite/gas/aarch64/cpu-cortex-a65ae.d: New test.
+	* testsuite/gas/aarch64/cpu-cortex-a76ae.d: New test.
+	* testsuite/gas/aarch64/cpu-cortex-a77.d: New test.
+	* testsuite/gas/aarch64/nop-asm.s: New test.
+
 2019-08-19  Faraz Shahbazker  <fshahbazker@wavecomp.com>
 
 	* config/tc-mips.c (fix_bad_misaligned_address): New function.
diff --git a/gas/NEWS b/gas/NEWS
index ff88fe90014..45ca34f63cd 100644
--- a/gas/NEWS
+++ b/gas/NEWS
@@ -8,6 +8,12 @@
   to set the default behavior. Set the default if the configure option is not used
   to "no".
 
+* Add support for the Arm Cortex-A76AE, Cortex-A77 and Cortex-M35P
+  processors.
+
+* Add support for the AArch64 Cortex-A34, Cortex-A65, Cortex-A65AE,
+  Cortex-A76AE, and Cortex-A77 processors.
+
 Changes in 2.32:
 
 * Add -mvexwig=[0|1] option to x86 assembler to control encoding of
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 4c19cd4a24a..136297a2130 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -8799,6 +8799,8 @@ struct aarch64_cpu_option_table
    recognized by GCC.  */
 static const struct aarch64_cpu_option_table aarch64_cpus[] = {
   {"all", AARCH64_ANY, NULL},
+  {"cortex-a34", AARCH64_FEATURE (AARCH64_ARCH_V8,
+				  AARCH64_FEATURE_CRC), "Cortex-A34"},
   {"cortex-a35", AARCH64_FEATURE (AARCH64_ARCH_V8,
 				  AARCH64_FEATURE_CRC), "Cortex-A35"},
   {"cortex-a53", AARCH64_FEATURE (AARCH64_ARCH_V8,
@@ -8818,6 +8820,26 @@ static const struct aarch64_cpu_option_table aarch64_cpus[] = {
   {"cortex-a76", AARCH64_FEATURE (AARCH64_ARCH_V8_2,
 				  AARCH64_FEATURE_RCPC | AARCH64_FEATURE_F16 | AARCH64_FEATURE_DOTPROD),
 				  "Cortex-A76"},
+  {"cortex-a76ae", AARCH64_FEATURE (AARCH64_ARCH_V8_2,
+				    AARCH64_FEATURE_F16 | AARCH64_FEATURE_RCPC
+				    | AARCH64_FEATURE_DOTPROD
+				    | AARCH64_FEATURE_SSBS),
+				    "Cortex-A76AE"},
+  {"cortex-a77", AARCH64_FEATURE (AARCH64_ARCH_V8_2,
+				  AARCH64_FEATURE_F16 | AARCH64_FEATURE_RCPC
+				  | AARCH64_FEATURE_DOTPROD
+				  | AARCH64_FEATURE_SSBS),
+				  "Cortex-A77"},
+  {"cortex-a65", AARCH64_FEATURE (AARCH64_ARCH_V8_2,
+				  AARCH64_FEATURE_F16 | AARCH64_FEATURE_RCPC
+				  | AARCH64_FEATURE_DOTPROD
+				  | AARCH64_FEATURE_SSBS),
+				  "Cortex-A65"},
+  {"cortex-a65ae", AARCH64_FEATURE (AARCH64_ARCH_V8_2,
+				    AARCH64_FEATURE_F16 | AARCH64_FEATURE_RCPC
+				    | AARCH64_FEATURE_DOTPROD
+				    | AARCH64_FEATURE_SSBS),
+				    "Cortex-A65AE"},
   {"ares", AARCH64_FEATURE (AARCH64_ARCH_V8_2,
 				  AARCH64_FEATURE_RCPC | AARCH64_FEATURE_F16
 				  | AARCH64_FEATURE_DOTPROD
diff --git a/gas/doc/c-aarch64.texi b/gas/doc/c-aarch64.texi
index 05e49ad6a8c..5c66fa6026a 100644
--- a/gas/doc/c-aarch64.texi
+++ b/gas/doc/c-aarch64.texi
@@ -55,14 +55,19 @@ file in ELF32 and ELF64 format respectively.  The default is @code{lp64}.
 This option specifies the target processor.  The assembler will issue an error
 message if an attempt is made to assemble an instruction which will not execute
 on the target processor.  The following processor names are recognized:
+@code{cortex-a34},
 @code{cortex-a35},
 @code{cortex-a53},
 @code{cortex-a55},
 @code{cortex-a57},
+@code{cortex-a65},
+@code{cortex-a65ae},
 @code{cortex-a72},
 @code{cortex-a73},
 @code{cortex-a75},
 @code{cortex-a76},
+@code{cortex-a76ae},
+@code{cortex-a77},
 @code{ares},
 @code{exynos-m1},
 @code{falkor},
diff --git a/gas/testsuite/gas/aarch64/cpu-cortex-a34.d b/gas/testsuite/gas/aarch64/cpu-cortex-a34.d
new file mode 100644
index 00000000000..31285dba38e
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/cpu-cortex-a34.d
@@ -0,0 +1,6 @@
+# name: Assemble and dump for cortex-a34 CPU
+# source: nop-asm.s
+# as: -mcpu=cortex-a34
+# objdump: -d -mcortex-a34
+
+#...
diff --git a/gas/testsuite/gas/aarch64/cpu-cortex-a65.d b/gas/testsuite/gas/aarch64/cpu-cortex-a65.d
new file mode 100644
index 00000000000..24e594263e2
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/cpu-cortex-a65.d
@@ -0,0 +1,6 @@
+# name: Assemble and dump for cortex-a65 CPU
+# source: nop-asm.s
+# as: -mcpu=cortex-a65
+# objdump: -d -mcortex-a65
+
+#...
diff --git a/gas/testsuite/gas/aarch64/cpu-cortex-a65ae.d b/gas/testsuite/gas/aarch64/cpu-cortex-a65ae.d
new file mode 100644
index 00000000000..cc8e9769d5c
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/cpu-cortex-a65ae.d
@@ -0,0 +1,6 @@
+# name: Assemble and dump for cortex-a65ae CPU
+# source: nop-asm.s
+# as: -mcpu=cortex-a65ae
+# objdump: -d -mcortex-a65ae
+
+#...
diff --git a/gas/testsuite/gas/aarch64/cpu-cortex-a76ae.d b/gas/testsuite/gas/aarch64/cpu-cortex-a76ae.d
new file mode 100644
index 00000000000..7f7cf2952c6
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/cpu-cortex-a76ae.d
@@ -0,0 +1,6 @@
+# name: Assemble and dump for cortex-a76ae CPU
+# source: nop-asm.s
+# as: -mcpu=cortex-a76ae
+# objdump: -d -mcortex-a76ae
+
+#...
diff --git a/gas/testsuite/gas/aarch64/cpu-cortex-a77.d b/gas/testsuite/gas/aarch64/cpu-cortex-a77.d
new file mode 100644
index 00000000000..caff73fe076
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/cpu-cortex-a77.d
@@ -0,0 +1,6 @@
+# name: Assemble and dump for cortex-a77 CPU
+# source: nop-asm.s
+# as: -mcpu=cortex-a77
+# objdump: -d -mcortex-a77
+
+#...
diff --git a/gas/testsuite/gas/aarch64/nop-asm.s b/gas/testsuite/gas/aarch64/nop-asm.s
new file mode 100644
index 00000000000..c27745a58f6
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/nop-asm.s
@@ -0,0 +1 @@
+nop
diff --git a/gas/testsuite/gas/arm/pr24907.d b/gas/testsuite/gas/arm/pr24907.d
new file mode 100644
index 00000000000..8268d4bdc15
--- /dev/null
+++ b/gas/testsuite/gas/arm/pr24907.d
@@ -0,0 +1,19 @@
+# name: Disassembling variable width insns with relocs (PR 24907)
+# as:
+# objdump: -d
+# This test is only valid on ELF based ports.
+#notarget: *-*-pe *-*-wince *-*-vxworks
+
+.*: +file format .*arm.*
+
+Disassembly of section \.text:
+
+0+000 <foo>:
+   0:	46c0      	nop			; .*
+   2:	f7ff fffe 	bl	0 <log_func>
+   6:	e002      	b\.n	e <func\+0x2>
+   8:	f7ff fffe 	bl	c <func>
+
+0+000c <func>:
+   c:	46c0      	nop			; .*
+   e:	46c0      	nop			; .*
diff --git a/gas/testsuite/gas/arm/pr24907.s b/gas/testsuite/gas/arm/pr24907.s
new file mode 100644
index 00000000000..ee8114e5747
--- /dev/null
+++ b/gas/testsuite/gas/arm/pr24907.s
@@ -0,0 +1,16 @@
+	.syntax unified
+	.text
+	.thumb
+
+.global foo
+foo:
+	nop
+	bl  log_func
+	b.n .L1
+	bl  func
+
+.global func
+func:
+	nop
+.L1:
+	nop