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| author | Matthew Malcomson <matthew.malcomson@arm.com> | 2019-05-09 10:29:20 +0100 |
|---|---|---|
| committer | Matthew Malcomson <matthew.malcomson@arm.com> | 2019-05-09 10:29:20 +0100 |
| commit | 3c705960ca0e12bb5d3a12d14ca6703006102d98 (patch) | |
| tree | d8634f08d243b93740c60c02ae469c0d0c6dcb32 | |
| parent | 0a57e14ffa4c2900f64780375282dc5dc493e250 (diff) | |
| download | binutils-gdb-3c705960ca0e12bb5d3a12d14ca6703006102d98.tar.gz | |
[binutils][aarch64] New sve_size_bh iclass.
Add new iclass sve_size_bh to handle instructions that have two variants
encoded with the SVE_sz field.
This iclass behaves the same as the sve_size_sd iclass, but it has a
nicer name for those instructions that choose between variants using the
"B" and "H" size qualifiers.
include/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* opcode/aarch64.h (enum aarch64_insn_class): Add sve_size_bh iclass.
opcodes/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
sve_size_bh iclass encode.
* aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
sve_size_bh iclass decode.
| -rw-r--r-- | include/ChangeLog | 4 | ||||
| -rw-r--r-- | include/opcode/aarch64.h | 1 | ||||
| -rw-r--r-- | opcodes/ChangeLog | 7 | ||||
| -rw-r--r-- | opcodes/aarch64-asm.c | 1 | ||||
| -rw-r--r-- | opcodes/aarch64-dis.c | 1 |
5 files changed, 14 insertions, 0 deletions
diff --git a/include/ChangeLog b/include/ChangeLog index 3d17921d7ee..28e00bfcec8 100644 --- a/include/ChangeLog +++ b/include/ChangeLog @@ -1,5 +1,9 @@ 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> + * opcode/aarch64.h (enum aarch64_insn_class): Add sve_size_bh iclass. + +2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> + * opcode/aarch64.h (enum aarch64_insn_class): Add sve_size_sd2 iclass. 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index 87499930398..0df8bddfd1c 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -594,6 +594,7 @@ enum aarch64_insn_class sve_size_hsd, sve_size_hsd2, sve_size_sd, + sve_size_bh, sve_size_sd2, testbranch, cryptosm3, diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index f139282c9b3..d0f28ced24d 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,6 +1,13 @@ 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle + sve_size_bh iclass encode. + * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle + sve_size_bh iclass decode. + +2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> + + * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle sve_size_sd2 iclass encode. * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle sve_size_sd2 iclass decode. diff --git a/opcodes/aarch64-asm.c b/opcodes/aarch64-asm.c index 6627b543aed..674eba5e9d3 100644 --- a/opcodes/aarch64-asm.c +++ b/opcodes/aarch64-asm.c @@ -1655,6 +1655,7 @@ aarch64_encode_variant_using_iclass (struct aarch64_inst *inst) insert_field (FLD_size, &inst->value, aarch64_get_variant (inst) + 1, 0); break; + case sve_size_bh: case sve_size_sd: insert_field (FLD_SVE_sz, &inst->value, aarch64_get_variant (inst), 0); break; diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c index 35576b3d2de..bfc47b4c1b8 100644 --- a/opcodes/aarch64-dis.c +++ b/opcodes/aarch64-dis.c @@ -2806,6 +2806,7 @@ aarch64_decode_variant_using_iclass (aarch64_inst *inst) variant = i - 1; break; + case sve_size_bh: case sve_size_sd: variant = extract_field (FLD_SVE_sz, inst->value, 0); break; |