| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | utest: modify compiler_if_else to not rely on compiler behaviour. | Ruiling Song | 2017-05-04 | 1 | -10/+5 |
| | | | | | | | | | | | | | the test case modify src as well as dst. and it introduce cross workitem memory dependency in dst[id] = src[id+1]; The compiler may order 'then' and 'else' block not as written. If compiler order the else block first. src[3+1] will be modified in else part. And the utest will get wrong result. If user want to get the old behaviour, It should use two if-then and order them as required. Signed-off-by: Ruiling Song <ruiling.song@intel.com> Reviewed-by: Yang Rong <rong.r.yang@intel.com> | ||||
| * | Added support for some Gen extensions. The idea is mostly to play with Gen | bsegovia | 2012-09-17 | 1 | -19/+0 |
| | | | | | | | | | | | | | | | | | specific hardware and propose simple way to use them. We have three extensions here: - Gen register regions. This allows us to perform strided loads in the register file. To implement that on top of OCL, the idea is to encapsulate them in a function with a side effect. Not really clean but it works. - Gen gather from register file. Same idea but here we simply gather data from a bunch of registers - Vote any/all. This is basically the same idea as ptx i.e. uniform predicates for branches. - block read/write. Just to play with uniform load/store messages I added a bunch of tests for all that and fix thing here and there to make them work | ||||
| * | Cleaned up the code from previous unused dependencies Upate the README | Benjamin Segovia | 2012-08-10 | 1 | -2/+2 |
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| * | Added more tests for structured and unstructured branches Debugged the ↵ | Benjamin Segovia | 2012-08-10 | 1 | -0/+83 |
| unstructured branch code | |||||
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