diff options
| author | Yang Rong <rong.r.yang@intel.com> | 2015-01-29 16:16:16 +0800 |
|---|---|---|
| committer | Zhigang Gong <zhigang.gong@intel.com> | 2015-01-30 11:34:01 +0800 |
| commit | c00ba9b55b01025429e1dbbb7a6f208a7891f8dd (patch) | |
| tree | 01f16f3483e2f1ccaed8cc951239efeaabce175f /src/cl_device_data.h | |
| parent | 9e424347c32bebe244fb502e0ccff9686a4235cd (diff) | |
| download | beignet-c00ba9b55b01025429e1dbbb7a6f208a7891f8dd.tar.gz | |
SKL: Add skl pci ids and device.
SKL add the new GT4 type device.
Signed-off-by: Yang Rong <rong.r.yang@intel.com>
Reviewed-by: He Junyan <Junyan.he@inbox.com>
Diffstat (limited to 'src/cl_device_data.h')
| -rw-r--r-- | src/cl_device_data.h | 45 |
1 files changed, 45 insertions, 0 deletions
diff --git a/src/cl_device_data.h b/src/cl_device_data.h index 0d25ca40..d6f82096 100644 --- a/src/cl_device_data.h +++ b/src/cl_device_data.h @@ -230,5 +230,50 @@ #define IS_BROADWELL(devid) (IS_BRW_GT1(devid) || IS_BRW_GT2(devid) || IS_BRW_GT3(devid)) #define IS_GEN8(devid) IS_BROADWELL(devid) +/* SKL */ +#define PCI_CHIP_SKYLAKE_ULT_GT1 0x1906 /* Intel(R) Skylake ULT - GT1 */ +#define PCI_CHIP_SKYLAKE_ULT_GT2 0x1916 /* Intel(R) Skylake ULT - GT2 */ +#define PCI_CHIP_SKYLAKE_ULT_GT3 0x1926 /* Intel(R) Skylake ULT - GT3 */ +#define PCI_CHIP_SKYLAKE_ULT_GT2F 0x1921 /* Intel(R) Skylake ULT - GT2F */ +#define PCI_CHIP_SKYLAKE_ULX_GT1 0x190E /* Intel(R) Skylake ULX - GT1 */ +#define PCI_CHIP_SKYLAKE_ULX_GT2 0x191E /* Intel(R) Skylake ULX - GT2 */ +#define PCI_CHIP_SKYLAKE_DT_GT1 0x1902 /* Intel(R) Skylake Desktop - GT1 */ +#define PCI_CHIP_SKYLAKE_DT_GT2 0x1912 /* Intel(R) Skylake Desktop - GT2 */ +#define PCI_CHIP_SKYLAKE_HALO_GT1 0x190B /* Intel(R) Skylake HALO - GT1 */ +#define PCI_CHIP_SKYLAKE_HALO_GT2 0x191B /* Intel(R) Skylake HALO - GT2 */ +#define PCI_CHIP_SKYLAKE_HALO_GT3 0x192B /* Intel(R) Skylake HALO - GT3 */ +#define PCI_CHIP_SKYLAKE_HALO_GT4 0x193B /* Intel(R) Skylake HALO - GT4 */ +#define PCI_CHIP_SKYLAKE_SRV_GT1 0x190A /* Intel(R) Skylake Server - GT1 */ +#define PCI_CHIP_SKYLAKE_SRV_GT2 0x191A /* Intel(R) Skylake Server - GT2 */ +#define PCI_CHIP_SKYLAKE_SRV_GT3 0x192A /* Intel(R) Skylake Server - GT3 */ +#define PCI_CHIP_SKYLAKE_SRV_GT4 0x193A /* Intel(R) Skylake Server - GT4 */ + +#define IS_SKL_GT1(devid) \ + (devid == PCI_CHIP_SKYLAKE_ULT_GT1 || \ + devid == PCI_CHIP_SKYLAKE_ULX_GT1 || \ + devid == PCI_CHIP_SKYLAKE_DT_GT1 || \ + devid == PCI_CHIP_SKYLAKE_HALO_GT1 || \ + devid == PCI_CHIP_SKYLAKE_SRV_GT1) + +#define IS_SKL_GT2(devid) \ + (devid == PCI_CHIP_SKYLAKE_ULT_GT2 || \ + devid == PCI_CHIP_SKYLAKE_ULT_GT2F || \ + devid == PCI_CHIP_SKYLAKE_ULX_GT2 || \ + devid == PCI_CHIP_SKYLAKE_DT_GT2 || \ + devid == PCI_CHIP_SKYLAKE_HALO_GT2 || \ + devid == PCI_CHIP_SKYLAKE_SRV_GT2) + +#define IS_SKL_GT3(devid) \ + (devid == PCI_CHIP_SKYLAKE_ULT_GT3 || \ + devid == PCI_CHIP_SKYLAKE_HALO_GT3 || \ + devid == PCI_CHIP_SKYLAKE_SRV_GT3) + +#define IS_SKL_GT4(devid) \ + (devid == PCI_CHIP_SKYLAKE_HALO_GT4 || \ + devid == PCI_CHIP_SKYLAKE_SRV_GT4) + +#define IS_SKYLAKE(devid) (IS_SKL_GT1(devid) || IS_SKL_GT2(devid) || IS_SKL_GT3(devid) || IS_SKL_GT4(devid)) +#define IS_GEN9(devid) IS_SKYLAKE(devid) + #endif /* __CL_DEVICE_DATA_H__ */ |