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| author | Yang, Rong <rong.r.yang@intel.com> | 2014-12-26 14:57:58 +0800 |
|---|---|---|
| committer | Zhigang Gong <zhigang.gong@intel.com> | 2014-12-29 09:50:42 +0800 |
| commit | c8ce68191ad3489ecd9351fc6f84335610716c86 (patch) | |
| tree | d52ecb8881470a7ce9779f6ee55730d2d94fba3a /src/cl_command_queue_gen7.c | |
| parent | e2439a02ab8734cff7554521523ca93668754a57 (diff) | |
| download | beignet-c8ce68191ad3489ecd9351fc6f84335610716c86.tar.gz | |
Separate flush and invalidate in function intel_gpgpu_pipe_control.
HSW has a limitation when PIPECONTROL with RO Cache Invalidation:
Prior to programming a PIPECONTROL command with any of the RO cache invalidation bit set,
program a PIPECONTROL flush command with CS stall bit and HDC Flush bit set.
So must use two PIPECONTROL commands to flush and invalidate L3 cache in HSW.
This patch fix some random fails which has very heavy DC read/write in HSW.
Signed-off-by: Yang, Rong <rong.r.yang@intel.com>
Reviewed-by: Zhigang Gong <zhigang.gong@linux.intel.com>
Diffstat (limited to 'src/cl_command_queue_gen7.c')
| -rw-r--r-- | src/cl_command_queue_gen7.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/cl_command_queue_gen7.c b/src/cl_command_queue_gen7.c index ba015ca7..734267a2 100644 --- a/src/cl_command_queue_gen7.c +++ b/src/cl_command_queue_gen7.c @@ -31,7 +31,7 @@ #include <string.h> #define MAX_GROUP_SIZE_IN_HALFSLICE 512 -static INLINE size_t cl_kernel_compute_batch_sz(cl_kernel k) { return 256+128; } +static INLINE size_t cl_kernel_compute_batch_sz(cl_kernel k) { return 256+256; } /* "Varing" payload is the part of the curbe that changes accross threads in the * same work group. Right now, it consists in local IDs and block IPs |