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| author | Ruiling Song <ruiling.song@intel.com> | 2014-04-11 14:48:16 +0800 |
|---|---|---|
| committer | Zhigang Gong <zhigang.gong@intel.com> | 2014-04-16 10:04:10 +0800 |
| commit | 4bfa29a138b46b72a20226d8b2eae081ccff3293 (patch) | |
| tree | e29f8330f3d68d1d50d66903044fe2c222891bdf /backend/src | |
| parent | 2ce0abf639dda9fc10965ef95ea93e2ad1e87c7c (diff) | |
| download | beignet-4bfa29a138b46b72a20226d8b2eae081ccff3293.tar.gz | |
enable mad for mul+sub.
Signed-off-by: Ruiling Song <ruiling.song@intel.com>
Reviewed-by: Zhigang Gong <zhigang.gong@linux.intel.com>
Diffstat (limited to 'backend/src')
| -rw-r--r-- | backend/src/backend/gen_insn_selection.cpp | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/backend/src/backend/gen_insn_selection.cpp b/backend/src/backend/gen_insn_selection.cpp index 820fbad9..f7f438e6 100644 --- a/backend/src/backend/gen_insn_selection.cpp +++ b/backend/src/backend/gen_insn_selection.cpp @@ -2073,6 +2073,7 @@ namespace gbe /*! Register the pattern for all opcodes of the family */ MulAddInstructionPattern(void) : SelectionPattern(2, 1) { this->opcodes.push_back(ir::OP_ADD); + this->opcodes.push_back(ir::OP_SUB); } /*! Implements base class */ @@ -2102,7 +2103,8 @@ namespace gbe GBE_ASSERT(cast<ir::BinaryInstruction>(child0->insn).getType() == TYPE_FLOAT); const GenRegister src0 = sel.selReg(child0->insn.getSrc(0), TYPE_FLOAT); const GenRegister src1 = sel.selReg(child0->insn.getSrc(1), TYPE_FLOAT); - const GenRegister src2 = sel.selReg(insn.getSrc(1), TYPE_FLOAT); + GenRegister src2 = sel.selReg(insn.getSrc(1), TYPE_FLOAT); + if(insn.getOpcode() == ir::OP_SUB) src2 = GenRegister::negate(src2); sel.MAD(dst, src2, src0, src1); // order different on HW! if (child0->child[0]) child0->child[0]->isRoot = 1; if (child0->child[1]) child0->child[1]->isRoot = 1; @@ -2111,9 +2113,10 @@ namespace gbe } if (child1 && child1->insn.getOpcode() == OP_MUL) { GBE_ASSERT(cast<ir::BinaryInstruction>(child1->insn).getType() == TYPE_FLOAT); - const GenRegister src0 = sel.selReg(child1->insn.getSrc(0), TYPE_FLOAT); + GenRegister src0 = sel.selReg(child1->insn.getSrc(0), TYPE_FLOAT); const GenRegister src1 = sel.selReg(child1->insn.getSrc(1), TYPE_FLOAT); const GenRegister src2 = sel.selReg(insn.getSrc(0), TYPE_FLOAT); + if(insn.getOpcode() == ir::OP_SUB) src0 = GenRegister::negate(src0); sel.MAD(dst, src2, src0, src1); // order different on HW! if (child1->child[0]) child1->child[0]->isRoot = 1; if (child1->child[1]) child1->child[1]->isRoot = 1; |