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author | Lorry Tar Creator <lorry-tar-importer@lorry> | 2017-06-27 06:07:23 +0000 |
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committer | Lorry Tar Creator <lorry-tar-importer@lorry> | 2017-06-27 06:07:23 +0000 |
commit | 1bf1084f2b10c3b47fd1a588d85d21ed0eb41d0c (patch) | |
tree | 46dcd36c86e7fbc6e5df36deb463b33e9967a6f7 /Source/JavaScriptCore/assembler/MIPSAssembler.h | |
parent | 32761a6cee1d0dee366b885b7b9c777e67885688 (diff) | |
download | WebKitGtk-tarball-1bf1084f2b10c3b47fd1a588d85d21ed0eb41d0c.tar.gz |
webkitgtk-2.16.5HEADwebkitgtk-2.16.5master
Diffstat (limited to 'Source/JavaScriptCore/assembler/MIPSAssembler.h')
-rw-r--r-- | Source/JavaScriptCore/assembler/MIPSAssembler.h | 43 |
1 files changed, 15 insertions, 28 deletions
diff --git a/Source/JavaScriptCore/assembler/MIPSAssembler.h b/Source/JavaScriptCore/assembler/MIPSAssembler.h index b75b4d0af..b1c42326c 100644 --- a/Source/JavaScriptCore/assembler/MIPSAssembler.h +++ b/Source/JavaScriptCore/assembler/MIPSAssembler.h @@ -26,8 +26,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -#ifndef MIPSAssembler_h -#define MIPSAssembler_h +#pragma once #if ENABLE(ASSEMBLER) && CPU(MIPS) @@ -151,11 +150,11 @@ public: typedef MIPSRegisters::FPRegisterID FPRegisterID; typedef SegmentedVector<AssemblerLabel, 64> Jumps; - static RegisterID firstRegister() { return MIPSRegisters::r0; } - static RegisterID lastRegister() { return MIPSRegisters::r31; } + static constexpr RegisterID firstRegister() { return MIPSRegisters::r0; } + static constexpr RegisterID lastRegister() { return MIPSRegisters::r31; } - static FPRegisterID firstFPRegister() { return MIPSRegisters::f0; } - static FPRegisterID lastFPRegister() { return MIPSRegisters::f31; } + static constexpr FPRegisterID firstFPRegister() { return MIPSRegisters::f0; } + static constexpr FPRegisterID lastFPRegister() { return MIPSRegisters::f31; } MIPSAssembler() : m_indexOfLastWatchpoint(INT_MIN) @@ -240,6 +239,11 @@ public: emitInst(0x3c000000 | (rt << OP_SH_RT) | (imm & 0xffff)); } + void clz(RegisterID rd, RegisterID rs) + { + emitInst(0x70000020 | (rd << OP_SH_RD) | (rs << OP_SH_RS) | (rd << OP_SH_RT)); + } + void addiu(RegisterID rt, RegisterID rs, int imm) { emitInst(0x24000000 | (rt << OP_SH_RT) | (rs << OP_SH_RS) | (imm & 0xffff)); @@ -542,6 +546,11 @@ public: emitInst(0x46200004 | (fd << OP_SH_FD) | (fs << OP_SH_FS)); } + void absd(FPRegisterID fd, FPRegisterID fs) + { + emitInst(0x46200005 | (fd << OP_SH_FD) | (fs << OP_SH_FS)); + } + void movd(FPRegisterID fd, FPRegisterID fs) { emitInst(0x46200006 | (fd << OP_SH_FD) | (fs << OP_SH_FS)); @@ -870,28 +879,8 @@ public: static void cacheFlush(void* code, size_t size) { -#if GCC_VERSION_AT_LEAST(4, 3, 0) -#if WTF_MIPS_ISA_REV(2) && !GCC_VERSION_AT_LEAST(4, 4, 3) - int lineSize; - asm("rdhwr %0, $1" : "=r" (lineSize)); - // - // Modify "start" and "end" to avoid GCC 4.3.0-4.4.2 bug in - // mips_expand_synci_loop that may execute synci one more time. - // "start" points to the fisrt byte of the cache line. - // "end" points to the last byte of the line before the last cache line. - // Because size is always a multiple of 4, this is safe to set - // "end" to the last byte. - // - intptr_t start = reinterpret_cast<intptr_t>(code) & (-lineSize); - intptr_t end = ((reinterpret_cast<intptr_t>(code) + size - 1) & (-lineSize)) - 1; - __builtin___clear_cache(reinterpret_cast<char*>(start), reinterpret_cast<char*>(end)); -#else intptr_t end = reinterpret_cast<intptr_t>(code) + size; __builtin___clear_cache(reinterpret_cast<char*>(code), reinterpret_cast<char*>(end)); -#endif -#else - _flush_cache(reinterpret_cast<char*>(code), size, BCACHE); -#endif } static ptrdiff_t maxJumpReplacementSize() @@ -1106,5 +1095,3 @@ private: } // namespace JSC #endif // ENABLE(ASSEMBLER) && CPU(MIPS) - -#endif // MIPSAssembler_h |