1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291
1292
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342
1343
1344
1345
1346
1347
1348
1349
1350
1351
1352
1353
1354
1355
1356
1357
1358
1359
1360
1361
1362
1363
1364
1365
1366
1367
1368
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378
1379
1380
1381
1382
1383
1384
1385
1386
1387
1388
1389
1390
1391
1392
1393
1394
1395
1396
1397
1398
1399
1400
1401
1402
1403
1404
1405
1406
1407
1408
1409
1410
1411
1412
1413
1414
1415
1416
1417
1418
1419
1420
1421
1422
1423
1424
1425
1426
1427
1428
1429
1430
1431
1432
1433
1434
1435
1436
1437
1438
1439
1440
1441
1442
1443
1444
1445
1446
1447
1448
1449
1450
1451
1452
1453
1454
1455
1456
1457
1458
1459
1460
1461
1462
1463
1464
1465
1466
1467
1468
1469
1470
1471
1472
1473
1474
1475
1476
1477
1478
1479
1480
1481
1482
1483
1484
1485
1486
1487
1488
1489
1490
1491
1492
1493
1494
1495
1496
1497
1498
1499
1500
1501
1502
1503
1504
1505
1506
1507
1508
1509
1510
1511
1512
1513
1514
1515
1516
1517
1518
1519
1520
1521
1522
1523
1524
1525
1526
1527
1528
1529
1530
1531
1532
1533
1534
1535
1536
1537
1538
1539
1540
1541
1542
1543
1544
1545
1546
1547
1548
1549
1550
1551
1552
1553
1554
1555
1556
1557
1558
1559
1560
1561
1562
1563
1564
1565
1566
1567
1568
1569
1570
1571
1572
1573
1574
1575
1576
1577
1578
1579
1580
1581
1582
1583
1584
1585
1586
1587
1588
1589
1590
1591
1592
1593
1594
1595
1596
1597
1598
1599
1600
1601
1602
1603
1604
1605
1606
1607
1608
1609
1610
1611
1612
1613
1614
1615
1616
1617
1618
1619
1620
1621
1622
1623
1624
1625
1626
1627
1628
1629
1630
1631
1632
1633
1634
1635
1636
1637
1638
1639
1640
1641
1642
1643
1644
1645
1646
1647
1648
1649
1650
1651
1652
1653
1654
1655
1656
1657
1658
1659
1660
1661
1662
1663
1664
1665
1666
1667
1668
1669
1670
1671
1672
1673
1674
1675
1676
1677
1678
1679
1680
1681
1682
1683
1684
1685
1686
1687
1688
1689
1690
1691
1692
1693
1694
1695
1696
1697
1698
1699
1700
1701
1702
1703
1704
1705
1706
1707
1708
1709
1710
1711
1712
1713
1714
1715
1716
1717
1718
1719
1720
1721
1722
1723
1724
1725
1726
1727
1728
1729
1730
1731
1732
1733
1734
1735
1736
1737
1738
1739
1740
1741
1742
1743
1744
1745
1746
1747
1748
1749
1750
1751
1752
1753
1754
1755
1756
1757
1758
1759
1760
1761
1762
1763
1764
1765
1766
1767
1768
1769
1770
1771
1772
1773
1774
1775
1776
1777
1778
1779
1780
1781
1782
1783
1784
1785
1786
1787
1788
1789
1790
1791
1792
1793
1794
1795
1796
1797
1798
1799
1800
1801
1802
1803
1804
1805
1806
1807
1808
1809
1810
1811
1812
1813
1814
1815
1816
1817
1818
1819
1820
1821
1822
1823
1824
1825
1826
1827
1828
1829
1830
1831
1832
1833
1834
1835
1836
1837
1838
1839
1840
1841
1842
1843
1844
1845
1846
1847
1848
1849
1850
1851
1852
1853
1854
1855
1856
1857
1858
1859
1860
1861
1862
1863
1864
1865
1866
1867
1868
1869
1870
1871
1872
1873
1874
1875
1876
1877
1878
1879
1880
1881
1882
1883
1884
1885
1886
1887
1888
1889
1890
1891
1892
1893
1894
1895
1896
1897
1898
1899
1900
1901
1902
1903
1904
1905
1906
1907
1908
1909
1910
1911
1912
1913
1914
1915
1916
1917
1918
1919
1920
1921
1922
1923
1924
1925
1926
1927
1928
1929
1930
1931
1932
1933
1934
1935
1936
1937
1938
1939
1940
1941
1942
1943
1944
1945
1946
1947
1948
1949
1950
1951
1952
1953
1954
1955
1956
1957
1958
1959
1960
1961
1962
1963
1964
1965
1966
1967
1968
1969
1970
1971
1972
1973
1974
1975
1976
1977
1978
1979
1980
1981
1982
1983
1984
1985
1986
1987
1988
1989
1990
1991
1992
1993
1994
1995
1996
1997
1998
1999
2000
2001
2002
2003
2004
2005
2006
2007
2008
2009
2010
2011
2012
2013
2014
2015
2016
2017
2018
2019
2020
2021
2022
2023
2024
2025
2026
2027
2028
2029
2030
2031
2032
2033
2034
2035
2036
2037
2038
2039
2040
2041
2042
2043
2044
2045
2046
2047
2048
2049
2050
2051
2052
2053
2054
2055
2056
2057
2058
2059
2060
2061
2062
2063
2064
2065
2066
2067
2068
2069
2070
2071
2072
2073
2074
2075
2076
2077
2078
2079
2080
2081
2082
2083
2084
2085
2086
2087
2088
2089
2090
2091
2092
2093
2094
2095
2096
2097
2098
2099
2100
2101
2102
2103
2104
2105
2106
2107
2108
2109
2110
2111
2112
2113
2114
2115
2116
2117
2118
2119
2120
2121
2122
2123
2124
2125
2126
2127
2128
2129
2130
2131
2132
2133
2134
2135
2136
2137
2138
2139
2140
2141
2142
2143
2144
2145
2146
2147
2148
2149
2150
2151
2152
2153
2154
2155
2156
2157
2158
2159
2160
2161
2162
2163
2164
2165
2166
2167
2168
2169
2170
2171
2172
2173
2174
2175
2176
2177
2178
2179
2180
2181
2182
2183
2184
2185
2186
2187
2188
2189
2190
2191
2192
2193
2194
2195
2196
2197
2198
2199
2200
2201
2202
2203
2204
2205
2206
2207
2208
2209
2210
2211
2212
2213
2214
2215
2216
2217
2218
2219
2220
2221
2222
2223
2224
2225
2226
2227
2228
2229
2230
2231
2232
2233
2234
2235
2236
2237
2238
2239
2240
2241
2242
2243
2244
2245
2246
2247
2248
2249
2250
2251
2252
2253
2254
2255
2256
2257
2258
2259
2260
2261
2262
2263
2264
2265
2266
2267
2268
2269
2270
2271
2272
2273
2274
2275
2276
2277
2278
2279
2280
2281
2282
2283
2284
2285
2286
2287
2288
2289
2290
2291
2292
2293
2294
2295
2296
2297
2298
2299
2300
2301
2302
2303
2304
2305
2306
2307
2308
2309
2310
2311
2312
2313
2314
2315
2316
2317
2318
2319
2320
2321
2322
2323
2324
2325
2326
2327
2328
2329
2330
2331
2332
2333
2334
2335
2336
2337
2338
2339
2340
2341
2342
2343
2344
2345
2346
2347
2348
2349
2350
2351
2352
2353
2354
2355
2356
2357
2358
2359
2360
2361
2362
2363
2364
2365
2366
2367
2368
2369
2370
2371
2372
2373
2374
2375
2376
2377
2378
2379
2380
2381
2382
2383
2384
2385
2386
2387
2388
2389
2390
2391
2392
2393
2394
2395
2396
2397
2398
2399
2400
2401
2402
2403
2404
2405
2406
2407
2408
2409
2410
2411
2412
2413
2414
2415
2416
2417
2418
2419
2420
2421
2422
2423
2424
2425
2426
2427
2428
2429
2430
2431
2432
2433
2434
2435
2436
2437
2438
2439
2440
2441
2442
2443
2444
2445
2446
2447
2448
2449
2450
2451
2452
2453
2454
2455
2456
2457
2458
2459
2460
2461
2462
2463
2464
2465
2466
2467
2468
2469
2470
2471
2472
2473
2474
2475
2476
2477
2478
2479
2480
2481
2482
2483
2484
2485
2486
2487
2488
2489
2490
2491
2492
2493
2494
2495
2496
2497
2498
2499
2500
2501
2502
2503
2504
2505
2506
2507
2508
2509
2510
2511
2512
2513
2514
2515
2516
2517
2518
2519
2520
2521
2522
2523
2524
2525
2526
2527
2528
2529
2530
2531
2532
2533
2534
2535
2536
2537
2538
2539
2540
2541
2542
2543
2544
2545
2546
2547
2548
2549
2550
2551
2552
2553
2554
2555
2556
2557
2558
2559
2560
2561
2562
2563
2564
2565
2566
2567
2568
2569
2570
2571
2572
2573
2574
2575
2576
2577
2578
2579
2580
2581
2582
2583
2584
2585
2586
2587
2588
2589
2590
2591
2592
2593
2594
2595
2596
2597
2598
2599
2600
2601
2602
2603
2604
2605
2606
2607
2608
2609
2610
2611
2612
2613
2614
2615
2616
2617
2618
2619
2620
2621
2622
2623
2624
2625
2626
2627
2628
2629
2630
2631
2632
2633
2634
2635
2636
2637
2638
2639
2640
2641
2642
2643
2644
2645
2646
2647
2648
2649
2650
2651
2652
2653
2654
2655
2656
2657
2658
2659
2660
2661
2662
2663
2664
2665
2666
2667
2668
2669
2670
2671
2672
2673
2674
2675
2676
2677
2678
2679
2680
2681
2682
2683
2684
2685
2686
2687
2688
2689
2690
2691
2692
2693
2694
2695
2696
2697
2698
2699
2700
2701
2702
2703
2704
2705
2706
2707
2708
2709
2710
2711
2712
2713
2714
2715
2716
2717
2718
2719
2720
2721
2722
2723
2724
2725
2726
2727
2728
2729
2730
2731
2732
2733
2734
2735
2736
2737
2738
2739
2740
2741
2742
2743
2744
2745
2746
2747
2748
2749
2750
2751
2752
2753
2754
2755
2756
2757
2758
2759
2760
2761
2762
2763
2764
2765
2766
2767
2768
2769
2770
2771
2772
2773
2774
2775
2776
2777
2778
2779
2780
2781
2782
2783
2784
2785
2786
2787
2788
2789
2790
2791
2792
2793
2794
2795
2796
2797
2798
2799
2800
2801
2802
2803
2804
2805
2806
2807
2808
2809
2810
2811
2812
2813
2814
2815
2816
2817
2818
2819
2820
2821
2822
2823
2824
2825
2826
2827
2828
2829
2830
2831
2832
2833
2834
2835
2836
2837
2838
2839
2840
2841
2842
2843
2844
2845
2846
2847
2848
2849
2850
2851
2852
2853
2854
2855
2856
2857
2858
2859
2860
2861
2862
2863
2864
2865
2866
2867
2868
2869
2870
2871
2872
2873
2874
2875
2876
2877
2878
2879
2880
2881
2882
2883
2884
2885
2886
2887
2888
2889
2890
2891
2892
2893
2894
2895
2896
2897
2898
2899
2900
2901
2902
2903
2904
2905
2906
2907
2908
2909
2910
2911
2912
2913
2914
2915
2916
2917
2918
2919
2920
2921
2922
2923
2924
2925
2926
2927
2928
2929
2930
2931
2932
2933
2934
2935
2936
2937
2938
2939
2940
2941
2942
2943
2944
2945
2946
2947
2948
2949
2950
2951
2952
2953
2954
2955
2956
2957
2958
2959
2960
2961
2962
2963
2964
2965
2966
2967
2968
2969
2970
2971
2972
2973
2974
2975
2976
2977
2978
2979
2980
2981
2982
2983
2984
2985
2986
2987
2988
2989
2990
2991
2992
2993
2994
2995
2996
2997
2998
2999
3000
3001
3002
3003
3004
3005
3006
3007
3008
3009
3010
3011
3012
3013
3014
3015
3016
3017
3018
3019
3020
3021
3022
3023
3024
3025
3026
3027
3028
3029
3030
3031
3032
3033
3034
3035
3036
3037
3038
3039
3040
3041
3042
3043
3044
3045
3046
3047
3048
3049
3050
3051
3052
3053
3054
3055
3056
3057
3058
3059
3060
3061
3062
3063
3064
3065
3066
3067
3068
3069
3070
3071
3072
3073
3074
3075
3076
3077
3078
3079
3080
3081
3082
3083
3084
3085
3086
3087
3088
3089
3090
3091
3092
3093
3094
3095
3096
3097
3098
3099
3100
3101
3102
3103
3104
3105
3106
3107
3108
3109
3110
3111
3112
3113
3114
3115
3116
3117
3118
3119
3120
3121
3122
3123
3124
3125
3126
3127
3128
3129
3130
3131
3132
3133
3134
3135
3136
3137
3138
3139
3140
3141
3142
3143
3144
3145
3146
3147
3148
3149
3150
3151
3152
3153
3154
3155
3156
3157
3158
3159
3160
3161
3162
3163
3164
3165
3166
3167
3168
3169
3170
3171
3172
3173
3174
3175
3176
3177
3178
3179
3180
3181
3182
3183
3184
3185
3186
3187
3188
3189
3190
3191
3192
3193
3194
3195
3196
3197
3198
3199
3200
3201
3202
3203
3204
3205
3206
3207
3208
3209
3210
3211
3212
3213
3214
3215
3216
3217
3218
3219
3220
3221
3222
3223
3224
3225
3226
3227
3228
3229
3230
3231
3232
3233
3234
3235
3236
3237
3238
3239
3240
3241
3242
3243
3244
3245
3246
3247
3248
3249
3250
3251
3252
3253
3254
3255
3256
3257
3258
3259
3260
3261
3262
3263
3264
3265
3266
3267
3268
3269
3270
3271
3272
3273
3274
3275
3276
3277
3278
3279
3280
3281
3282
3283
3284
3285
3286
3287
3288
3289
3290
3291
3292
3293
3294
3295
3296
3297
3298
3299
3300
3301
3302
3303
3304
3305
3306
3307
3308
3309
3310
3311
3312
3313
3314
3315
3316
3317
3318
3319
3320
3321
3322
3323
3324
3325
3326
3327
3328
3329
3330
3331
3332
3333
3334
3335
3336
3337
3338
3339
3340
3341
3342
3343
3344
3345
3346
3347
3348
3349
3350
3351
3352
3353
3354
3355
3356
3357
3358
3359
3360
3361
3362
3363
3364
3365
3366
3367
3368
3369
3370
3371
3372
3373
3374
3375
3376
3377
3378
3379
3380
3381
3382
3383
3384
3385
3386
3387
3388
3389
3390
3391
3392
3393
3394
3395
3396
3397
3398
3399
3400
3401
3402
3403
3404
3405
3406
3407
3408
3409
3410
3411
3412
3413
3414
3415
3416
3417
3418
3419
3420
3421
3422
3423
3424
3425
3426
3427
3428
3429
3430
3431
3432
|
/** @file
* IPRT - X86 and AMD64 Structures and Definitions.
*
* @note x86.mac is generated from this file by running 'kmk incs' in the root.
*/
/*
* Copyright (C) 2006-2012 Oracle Corporation
*
* This file is part of VirtualBox Open Source Edition (OSE), as
* available from http://www.virtualbox.org. This file is free software;
* you can redistribute it and/or modify it under the terms of the GNU
* General Public License (GPL) as published by the Free Software
* Foundation, in version 2 as it comes in the "COPYING" file of the
* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
*
* The contents of this file may alternatively be used under the terms
* of the Common Development and Distribution License Version 1.0
* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
* VirtualBox OSE distribution, in which case the provisions of the
* CDDL are applicable instead of those of the GPL.
*
* You may elect to license modified versions of this file under the
* terms and conditions of either the GPL or the CDDL or both.
*/
#ifndef ___iprt_x86_h
#define ___iprt_x86_h
#ifndef VBOX_FOR_DTRACE_LIB
# include <iprt/types.h>
# include <iprt/assert.h>
#else
# pragma D depends_on library vbox-types.d
#endif
/* Workaround for Solaris sys/regset.h defining CS, DS */
#ifdef RT_OS_SOLARIS
# undef CS
# undef DS
#endif
/** @defgroup grp_rt_x86 x86 Types and Definitions
* @ingroup grp_rt
* @{
*/
#ifndef VBOX_FOR_DTRACE_LIB
/**
* EFLAGS Bits.
*/
typedef struct X86EFLAGSBITS
{
/** Bit 0 - CF - Carry flag - Status flag. */
unsigned u1CF : 1;
/** Bit 1 - 1 - Reserved flag. */
unsigned u1Reserved0 : 1;
/** Bit 2 - PF - Parity flag - Status flag. */
unsigned u1PF : 1;
/** Bit 3 - 0 - Reserved flag. */
unsigned u1Reserved1 : 1;
/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
unsigned u1AF : 1;
/** Bit 5 - 0 - Reserved flag. */
unsigned u1Reserved2 : 1;
/** Bit 6 - ZF - Zero flag - Status flag. */
unsigned u1ZF : 1;
/** Bit 7 - SF - Signed flag - Status flag. */
unsigned u1SF : 1;
/** Bit 8 - TF - Trap flag - System flag. */
unsigned u1TF : 1;
/** Bit 9 - IF - Interrupt flag - System flag. */
unsigned u1IF : 1;
/** Bit 10 - DF - Direction flag - Control flag. */
unsigned u1DF : 1;
/** Bit 11 - OF - Overflow flag - Status flag. */
unsigned u1OF : 1;
/** Bit 12-13 - IOPL - I/O prvilege level flag - System flag. */
unsigned u2IOPL : 2;
/** Bit 14 - NT - Nested task flag - System flag. */
unsigned u1NT : 1;
/** Bit 15 - 0 - Reserved flag. */
unsigned u1Reserved3 : 1;
/** Bit 16 - RF - Resume flag - System flag. */
unsigned u1RF : 1;
/** Bit 17 - VM - Virtual 8086 mode - System flag. */
unsigned u1VM : 1;
/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
unsigned u1AC : 1;
/** Bit 19 - VIF - Virtual interrupt flag - System flag. */
unsigned u1VIF : 1;
/** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */
unsigned u1VIP : 1;
/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
unsigned u1ID : 1;
/** Bit 22-31 - 0 - Reserved flag. */
unsigned u10Reserved4 : 10;
} X86EFLAGSBITS;
/** Pointer to EFLAGS bits. */
typedef X86EFLAGSBITS *PX86EFLAGSBITS;
/** Pointer to const EFLAGS bits. */
typedef const X86EFLAGSBITS *PCX86EFLAGSBITS;
#endif /* !VBOX_FOR_DTRACE_LIB */
/**
* EFLAGS.
*/
typedef union X86EFLAGS
{
/** The plain unsigned view. */
uint32_t u;
#ifndef VBOX_FOR_DTRACE_LIB
/** The bitfield view. */
X86EFLAGSBITS Bits;
#endif
/** The 8-bit view. */
uint8_t au8[4];
/** The 16-bit view. */
uint16_t au16[2];
/** The 32-bit view. */
uint32_t au32[1];
/** The 32-bit view. */
uint32_t u32;
} X86EFLAGS;
/** Pointer to EFLAGS. */
typedef X86EFLAGS *PX86EFLAGS;
/** Pointer to const EFLAGS. */
typedef const X86EFLAGS *PCX86EFLAGS;
/**
* RFLAGS (32 upper bits are reserved).
*/
typedef union X86RFLAGS
{
/** The plain unsigned view. */
uint64_t u;
#ifndef VBOX_FOR_DTRACE_LIB
/** The bitfield view. */
X86EFLAGSBITS Bits;
#endif
/** The 8-bit view. */
uint8_t au8[8];
/** The 16-bit view. */
uint16_t au16[4];
/** The 32-bit view. */
uint32_t au32[2];
/** The 64-bit view. */
uint64_t au64[1];
/** The 64-bit view. */
uint64_t u64;
} X86RFLAGS;
/** Pointer to RFLAGS. */
typedef X86RFLAGS *PX86RFLAGS;
/** Pointer to const RFLAGS. */
typedef const X86RFLAGS *PCX86RFLAGS;
/** @name EFLAGS
* @{
*/
/** Bit 0 - CF - Carry flag - Status flag. */
#define X86_EFL_CF RT_BIT(0)
#define X86_EFL_CF_BIT 0
/** Bit 1 - Reserved, reads as 1. */
#define X86_EFL_1 RT_BIT(1)
/** Bit 2 - PF - Parity flag - Status flag. */
#define X86_EFL_PF RT_BIT(2)
/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
#define X86_EFL_AF RT_BIT(4)
#define X86_EFL_AF_BIT 4
/** Bit 6 - ZF - Zero flag - Status flag. */
#define X86_EFL_ZF RT_BIT(6)
#define X86_EFL_ZF_BIT 6
/** Bit 7 - SF - Signed flag - Status flag. */
#define X86_EFL_SF RT_BIT(7)
#define X86_EFL_SF_BIT 7
/** Bit 8 - TF - Trap flag - System flag. */
#define X86_EFL_TF RT_BIT(8)
/** Bit 9 - IF - Interrupt flag - System flag. */
#define X86_EFL_IF RT_BIT(9)
/** Bit 10 - DF - Direction flag - Control flag. */
#define X86_EFL_DF RT_BIT(10)
/** Bit 11 - OF - Overflow flag - Status flag. */
#define X86_EFL_OF RT_BIT(11)
#define X86_EFL_OF_BIT 11
/** Bit 12-13 - IOPL - I/O prvilege level flag - System flag. */
#define X86_EFL_IOPL (RT_BIT(12) | RT_BIT(13))
/** Bit 14 - NT - Nested task flag - System flag. */
#define X86_EFL_NT RT_BIT(14)
/** Bit 16 - RF - Resume flag - System flag. */
#define X86_EFL_RF RT_BIT(16)
/** Bit 17 - VM - Virtual 8086 mode - System flag. */
#define X86_EFL_VM RT_BIT(17)
/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
#define X86_EFL_AC RT_BIT(18)
/** Bit 19 - VIF - Virtual interrupt flag - System flag. */
#define X86_EFL_VIF RT_BIT(19)
/** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */
#define X86_EFL_VIP RT_BIT(20)
/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
#define X86_EFL_ID RT_BIT(21)
/** All live bits. */
#define X86_EFL_LIVE_MASK UINT32_C(0x003f7fd5)
/** Read as 1 bits. */
#define X86_EFL_RA1_MASK RT_BIT_32(1)
/** IOPL shift. */
#define X86_EFL_IOPL_SHIFT 12
/** The the IOPL level from the flags. */
#define X86_EFL_GET_IOPL(efl) (((efl) >> X86_EFL_IOPL_SHIFT) & 3)
/** Bits restored by popf */
#define X86_EFL_POPF_BITS ( X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_TF | X86_EFL_IF \
| X86_EFL_DF | X86_EFL_OF | X86_EFL_IOPL | X86_EFL_NT | X86_EFL_AC | X86_EFL_ID )
/** The status bits commonly updated by arithmetic instructions. */
#define X86_EFL_STATUS_BITS ( X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF )
/** @} */
/** CPUID Feature information - ECX.
* CPUID query with EAX=1.
*/
#ifndef VBOX_FOR_DTRACE_LIB
typedef struct X86CPUIDFEATECX
{
/** Bit 0 - SSE3 - Supports SSE3 or not. */
unsigned u1SSE3 : 1;
/** Bit 1 - PCLMULQDQ. */
unsigned u1PCLMULQDQ : 1;
/** Bit 2 - DS Area 64-bit layout. */
unsigned u1DTE64 : 1;
/** Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
unsigned u1Monitor : 1;
/** Bit 4 - CPL-DS - CPL Qualified Debug Store. */
unsigned u1CPLDS : 1;
/** Bit 5 - VMX - Virtual Machine Technology. */
unsigned u1VMX : 1;
/** Bit 6 - SMX: Safer Mode Extensions. */
unsigned u1SMX : 1;
/** Bit 7 - EST - Enh. SpeedStep Tech. */
unsigned u1EST : 1;
/** Bit 8 - TM2 - Terminal Monitor 2. */
unsigned u1TM2 : 1;
/** Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
unsigned u1SSSE3 : 1;
/** Bit 10 - CNTX-ID - L1 Context ID. */
unsigned u1CNTXID : 1;
/** Bit 11 - Reserved. */
unsigned u1Reserved1 : 1;
/** Bit 12 - FMA. */
unsigned u1FMA : 1;
/** Bit 13 - CX16 - CMPXCHG16B. */
unsigned u1CX16 : 1;
/** Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
unsigned u1TPRUpdate : 1;
/** Bit 15 - PDCM - Perf/Debug Capability MSR. */
unsigned u1PDCM : 1;
/** Bit 16 - Reserved. */
unsigned u1Reserved2 : 1;
/** Bit 17 - PCID - Process-context identifiers. */
unsigned u1PCID : 1;
/** Bit 18 - Direct Cache Access. */
unsigned u1DCA : 1;
/** Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
unsigned u1SSE4_1 : 1;
/** Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
unsigned u1SSE4_2 : 1;
/** Bit 21 - x2APIC. */
unsigned u1x2APIC : 1;
/** Bit 22 - MOVBE - Supports MOVBE. */
unsigned u1MOVBE : 1;
/** Bit 23 - POPCNT - Supports POPCNT. */
unsigned u1POPCNT : 1;
/** Bit 24 - TSC-Deadline. */
unsigned u1TSCDEADLINE : 1;
/** Bit 25 - AES. */
unsigned u1AES : 1;
/** Bit 26 - XSAVE - Supports XSAVE. */
unsigned u1XSAVE : 1;
/** Bit 27 - OSXSAVE - Supports OSXSAVE. */
unsigned u1OSXSAVE : 1;
/** Bit 28 - AVX - Supports AVX instruction extensions. */
unsigned u1AVX : 1;
/** Bit 29 - 30 - Reserved */
unsigned u2Reserved3 : 2;
/** Bit 31 - Hypervisor present (we're a guest). */
unsigned u1HVP : 1;
} X86CPUIDFEATECX;
#else /* VBOX_FOR_DTRACE_LIB */
typedef uint32_t X86CPUIDFEATECX;
#endif /* VBOX_FOR_DTRACE_LIB */
/** Pointer to CPUID Feature Information - ECX. */
typedef X86CPUIDFEATECX *PX86CPUIDFEATECX;
/** Pointer to const CPUID Feature Information - ECX. */
typedef const X86CPUIDFEATECX *PCX86CPUIDFEATECX;
/** CPUID Feature Information - EDX.
* CPUID query with EAX=1.
*/
#ifndef VBOX_FOR_DTRACE_LIB /* DTrace different (brain-dead from a C pov) bitfield implementation */
typedef struct X86CPUIDFEATEDX
{
/** Bit 0 - FPU - x87 FPU on Chip. */
unsigned u1FPU : 1;
/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
unsigned u1VME : 1;
/** Bit 2 - DE - Debugging extensions. */
unsigned u1DE : 1;
/** Bit 3 - PSE - Page Size Extension. */
unsigned u1PSE : 1;
/** Bit 4 - TSC - Time Stamp Counter. */
unsigned u1TSC : 1;
/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
unsigned u1MSR : 1;
/** Bit 6 - PAE - Physical Address Extension. */
unsigned u1PAE : 1;
/** Bit 7 - MCE - Machine Check Exception. */
unsigned u1MCE : 1;
/** Bit 8 - CX8 - CMPXCHG8B instruction. */
unsigned u1CX8 : 1;
/** Bit 9 - APIC - APIC On-Chip. */
unsigned u1APIC : 1;
/** Bit 10 - Reserved. */
unsigned u1Reserved1 : 1;
/** Bit 11 - SEP - SYSENTER and SYSEXIT. */
unsigned u1SEP : 1;
/** Bit 12 - MTRR - Memory Type Range Registers. */
unsigned u1MTRR : 1;
/** Bit 13 - PGE - PTE Global Bit. */
unsigned u1PGE : 1;
/** Bit 14 - MCA - Machine Check Architecture. */
unsigned u1MCA : 1;
/** Bit 15 - CMOV - Conditional Move Instructions. */
unsigned u1CMOV : 1;
/** Bit 16 - PAT - Page Attribute Table. */
unsigned u1PAT : 1;
/** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
unsigned u1PSE36 : 1;
/** Bit 18 - PSN - Processor Serial Number. */
unsigned u1PSN : 1;
/** Bit 19 - CLFSH - CLFLUSH Instruction. */
unsigned u1CLFSH : 1;
/** Bit 20 - Reserved. */
unsigned u1Reserved2 : 1;
/** Bit 21 - DS - Debug Store. */
unsigned u1DS : 1;
/** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
unsigned u1ACPI : 1;
/** Bit 23 - MMX - Intel MMX 'Technology'. */
unsigned u1MMX : 1;
/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
unsigned u1FXSR : 1;
/** Bit 25 - SSE - SSE Support. */
unsigned u1SSE : 1;
/** Bit 26 - SSE2 - SSE2 Support. */
unsigned u1SSE2 : 1;
/** Bit 27 - SS - Self Snoop. */
unsigned u1SS : 1;
/** Bit 28 - HTT - Hyper-Threading Technology. */
unsigned u1HTT : 1;
/** Bit 29 - TM - Thermal Monitor. */
unsigned u1TM : 1;
/** Bit 30 - Reserved - . */
unsigned u1Reserved3 : 1;
/** Bit 31 - PBE - Pending Break Enabled. */
unsigned u1PBE : 1;
} X86CPUIDFEATEDX;
#else /* VBOX_FOR_DTRACE_LIB */
typedef uint32_t X86CPUIDFEATEDX;
#endif /* VBOX_FOR_DTRACE_LIB */
/** Pointer to CPUID Feature Information - EDX. */
typedef X86CPUIDFEATEDX *PX86CPUIDFEATEDX;
/** Pointer to const CPUID Feature Information - EDX. */
typedef const X86CPUIDFEATEDX *PCX86CPUIDFEATEDX;
/** @name CPUID Vendor information.
* CPUID query with EAX=0.
* @{
*/
#define X86_CPUID_VENDOR_INTEL_EBX 0x756e6547 /* Genu */
#define X86_CPUID_VENDOR_INTEL_ECX 0x6c65746e /* ntel */
#define X86_CPUID_VENDOR_INTEL_EDX 0x49656e69 /* ineI */
#define X86_CPUID_VENDOR_AMD_EBX 0x68747541 /* Auth */
#define X86_CPUID_VENDOR_AMD_ECX 0x444d4163 /* cAMD */
#define X86_CPUID_VENDOR_AMD_EDX 0x69746e65 /* enti */
#define X86_CPUID_VENDOR_VIA_EBX 0x746e6543 /* Cent */
#define X86_CPUID_VENDOR_VIA_ECX 0x736c7561 /* auls */
#define X86_CPUID_VENDOR_VIA_EDX 0x48727561 /* aurH */
/** @} */
/** @name CPUID Feature information.
* CPUID query with EAX=1.
* @{
*/
/** ECX Bit 0 - SSE3 - Supports SSE3 or not. */
#define X86_CPUID_FEATURE_ECX_SSE3 RT_BIT(0)
/** ECX Bit 1 - PCLMUL - PCLMULQDQ support (for AES-GCM). */
#define X86_CPUID_FEATURE_ECX_PCLMUL RT_BIT(1)
/** ECX Bit 2 - DTES64 - DS Area 64-bit Layout. */
#define X86_CPUID_FEATURE_ECX_DTES64 RT_BIT(2)
/** ECX Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
#define X86_CPUID_FEATURE_ECX_MONITOR RT_BIT(3)
/** ECX Bit 4 - CPL-DS - CPL Qualified Debug Store. */
#define X86_CPUID_FEATURE_ECX_CPLDS RT_BIT(4)
/** ECX Bit 5 - VMX - Virtual Machine Technology. */
#define X86_CPUID_FEATURE_ECX_VMX RT_BIT(5)
/** ECX Bit 6 - SMX - Safer Mode Extensions. */
#define X86_CPUID_FEATURE_ECX_SMX RT_BIT(6)
/** ECX Bit 7 - EST - Enh. SpeedStep Tech. */
#define X86_CPUID_FEATURE_ECX_EST RT_BIT(7)
/** ECX Bit 8 - TM2 - Terminal Monitor 2. */
#define X86_CPUID_FEATURE_ECX_TM2 RT_BIT(8)
/** ECX Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
#define X86_CPUID_FEATURE_ECX_SSSE3 RT_BIT(9)
/** ECX Bit 10 - CNTX-ID - L1 Context ID. */
#define X86_CPUID_FEATURE_ECX_CNTXID RT_BIT(10)
/** ECX Bit 12 - FMA. */
#define X86_CPUID_FEATURE_ECX_FMA RT_BIT(12)
/** ECX Bit 13 - CX16 - CMPXCHG16B. */
#define X86_CPUID_FEATURE_ECX_CX16 RT_BIT(13)
/** ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
#define X86_CPUID_FEATURE_ECX_TPRUPDATE RT_BIT(14)
/** ECX Bit 15 - PDCM - Perf/Debug Capability MSR. */
#define X86_CPUID_FEATURE_ECX_PDCM RT_BIT(15)
/** ECX Bit 17 - PCID - Process-context identifiers. */
#define X86_CPUID_FEATURE_ECX_PCID RT_BIT(17)
/** ECX Bit 18 - DCA - Direct Cache Access. */
#define X86_CPUID_FEATURE_ECX_DCA RT_BIT(18)
/** ECX Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
#define X86_CPUID_FEATURE_ECX_SSE4_1 RT_BIT(19)
/** ECX Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
#define X86_CPUID_FEATURE_ECX_SSE4_2 RT_BIT(20)
/** ECX Bit 21 - x2APIC support. */
#define X86_CPUID_FEATURE_ECX_X2APIC RT_BIT(21)
/** ECX Bit 22 - MOVBE instruction. */
#define X86_CPUID_FEATURE_ECX_MOVBE RT_BIT(22)
/** ECX Bit 23 - POPCNT instruction. */
#define X86_CPUID_FEATURE_ECX_POPCNT RT_BIT(23)
/** ECX Bir 24 - TSC-Deadline. */
#define X86_CPUID_FEATURE_ECX_TSCDEADL RT_BIT(24)
/** ECX Bit 25 - AES instructions. */
#define X86_CPUID_FEATURE_ECX_AES RT_BIT(25)
/** ECX Bit 26 - XSAVE instruction. */
#define X86_CPUID_FEATURE_ECX_XSAVE RT_BIT(26)
/** ECX Bit 27 - OSXSAVE instruction. */
#define X86_CPUID_FEATURE_ECX_OSXSAVE RT_BIT(27)
/** ECX Bit 28 - AVX. */
#define X86_CPUID_FEATURE_ECX_AVX RT_BIT(28)
/** ECX Bit 29 - F16C - Half-precision convert instruction support. */
#define X86_CPUID_FEATURE_ECX_F16C RT_BIT(29)
/** ECX Bit 31 - Hypervisor Present (software only). */
#define X86_CPUID_FEATURE_ECX_HVP RT_BIT(31)
/** Bit 0 - FPU - x87 FPU on Chip. */
#define X86_CPUID_FEATURE_EDX_FPU RT_BIT(0)
/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
#define X86_CPUID_FEATURE_EDX_VME RT_BIT(1)
/** Bit 2 - DE - Debugging extensions. */
#define X86_CPUID_FEATURE_EDX_DE RT_BIT(2)
/** Bit 3 - PSE - Page Size Extension. */
#define X86_CPUID_FEATURE_EDX_PSE RT_BIT(3)
/** Bit 4 - TSC - Time Stamp Counter. */
#define X86_CPUID_FEATURE_EDX_TSC RT_BIT(4)
/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
#define X86_CPUID_FEATURE_EDX_MSR RT_BIT(5)
/** Bit 6 - PAE - Physical Address Extension. */
#define X86_CPUID_FEATURE_EDX_PAE RT_BIT(6)
/** Bit 7 - MCE - Machine Check Exception. */
#define X86_CPUID_FEATURE_EDX_MCE RT_BIT(7)
/** Bit 8 - CX8 - CMPXCHG8B instruction. */
#define X86_CPUID_FEATURE_EDX_CX8 RT_BIT(8)
/** Bit 9 - APIC - APIC On-Chip. */
#define X86_CPUID_FEATURE_EDX_APIC RT_BIT(9)
/** Bit 11 - SEP - SYSENTER and SYSEXIT Present. */
#define X86_CPUID_FEATURE_EDX_SEP RT_BIT(11)
/** Bit 12 - MTRR - Memory Type Range Registers. */
#define X86_CPUID_FEATURE_EDX_MTRR RT_BIT(12)
/** Bit 13 - PGE - PTE Global Bit. */
#define X86_CPUID_FEATURE_EDX_PGE RT_BIT(13)
/** Bit 14 - MCA - Machine Check Architecture. */
#define X86_CPUID_FEATURE_EDX_MCA RT_BIT(14)
/** Bit 15 - CMOV - Conditional Move Instructions. */
#define X86_CPUID_FEATURE_EDX_CMOV RT_BIT(15)
/** Bit 16 - PAT - Page Attribute Table. */
#define X86_CPUID_FEATURE_EDX_PAT RT_BIT(16)
/** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
#define X86_CPUID_FEATURE_EDX_PSE36 RT_BIT(17)
/** Bit 18 - PSN - Processor Serial Number. */
#define X86_CPUID_FEATURE_EDX_PSN RT_BIT(18)
/** Bit 19 - CLFSH - CLFLUSH Instruction. */
#define X86_CPUID_FEATURE_EDX_CLFSH RT_BIT(19)
/** Bit 21 - DS - Debug Store. */
#define X86_CPUID_FEATURE_EDX_DS RT_BIT(21)
/** Bit 22 - ACPI - Termal Monitor and Software Controlled Clock Facilities. */
#define X86_CPUID_FEATURE_EDX_ACPI RT_BIT(22)
/** Bit 23 - MMX - Intel MMX Technology. */
#define X86_CPUID_FEATURE_EDX_MMX RT_BIT(23)
/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
#define X86_CPUID_FEATURE_EDX_FXSR RT_BIT(24)
/** Bit 25 - SSE - SSE Support. */
#define X86_CPUID_FEATURE_EDX_SSE RT_BIT(25)
/** Bit 26 - SSE2 - SSE2 Support. */
#define X86_CPUID_FEATURE_EDX_SSE2 RT_BIT(26)
/** Bit 27 - SS - Self Snoop. */
#define X86_CPUID_FEATURE_EDX_SS RT_BIT(27)
/** Bit 28 - HTT - Hyper-Threading Technology. */
#define X86_CPUID_FEATURE_EDX_HTT RT_BIT(28)
/** Bit 29 - TM - Therm. Monitor. */
#define X86_CPUID_FEATURE_EDX_TM RT_BIT(29)
/** Bit 31 - PBE - Pending Break Enabled. */
#define X86_CPUID_FEATURE_EDX_PBE RT_BIT(31)
/** @} */
/** @name CPUID mwait/monitor information.
* CPUID query with EAX=5.
* @{
*/
/** ECX Bit 0 - MWAITEXT - Supports mwait/monitor extensions or not. */
#define X86_CPUID_MWAIT_ECX_EXT RT_BIT(0)
/** ECX Bit 1 - MWAITBREAK - Break mwait for external interrupt even if EFLAGS.IF=0. */
#define X86_CPUID_MWAIT_ECX_BREAKIRQIF0 RT_BIT(1)
/** @} */
/** @name CPUID Extended Feature information.
* CPUID query with EAX=0x80000001.
* @{
*/
/** ECX Bit 0 - LAHF/SAHF support in 64-bit mode. */
#define X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF RT_BIT(0)
/** EDX Bit 11 - SYSCALL/SYSRET. */
#define X86_CPUID_EXT_FEATURE_EDX_SYSCALL RT_BIT(11)
/** EDX Bit 20 - No-Execute/Execute-Disable. */
#define X86_CPUID_EXT_FEATURE_EDX_NX RT_BIT(20)
/** EDX Bit 26 - 1 GB large page. */
#define X86_CPUID_EXT_FEATURE_EDX_PAGE1GB RT_BIT(26)
/** EDX Bit 27 - RDTSCP. */
#define X86_CPUID_EXT_FEATURE_EDX_RDTSCP RT_BIT(27)
/** EDX Bit 29 - AMD Long Mode/Intel-64 Instructions. */
#define X86_CPUID_EXT_FEATURE_EDX_LONG_MODE RT_BIT(29)
/** @}*/
/** @name CPUID AMD Feature information.
* CPUID query with EAX=0x80000001.
* @{
*/
/** Bit 0 - FPU - x87 FPU on Chip. */
#define X86_CPUID_AMD_FEATURE_EDX_FPU RT_BIT(0)
/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
#define X86_CPUID_AMD_FEATURE_EDX_VME RT_BIT(1)
/** Bit 2 - DE - Debugging extensions. */
#define X86_CPUID_AMD_FEATURE_EDX_DE RT_BIT(2)
/** Bit 3 - PSE - Page Size Extension. */
#define X86_CPUID_AMD_FEATURE_EDX_PSE RT_BIT(3)
/** Bit 4 - TSC - Time Stamp Counter. */
#define X86_CPUID_AMD_FEATURE_EDX_TSC RT_BIT(4)
/** Bit 5 - MSR - K86 Model Specific Registers RDMSR and WRMSR Instructions. */
#define X86_CPUID_AMD_FEATURE_EDX_MSR RT_BIT(5)
/** Bit 6 - PAE - Physical Address Extension. */
#define X86_CPUID_AMD_FEATURE_EDX_PAE RT_BIT(6)
/** Bit 7 - MCE - Machine Check Exception. */
#define X86_CPUID_AMD_FEATURE_EDX_MCE RT_BIT(7)
/** Bit 8 - CX8 - CMPXCHG8B instruction. */
#define X86_CPUID_AMD_FEATURE_EDX_CX8 RT_BIT(8)
/** Bit 9 - APIC - APIC On-Chip. */
#define X86_CPUID_AMD_FEATURE_EDX_APIC RT_BIT(9)
/** Bit 12 - MTRR - Memory Type Range Registers. */
#define X86_CPUID_AMD_FEATURE_EDX_MTRR RT_BIT(12)
/** Bit 13 - PGE - PTE Global Bit. */
#define X86_CPUID_AMD_FEATURE_EDX_PGE RT_BIT(13)
/** Bit 14 - MCA - Machine Check Architecture. */
#define X86_CPUID_AMD_FEATURE_EDX_MCA RT_BIT(14)
/** Bit 15 - CMOV - Conditional Move Instructions. */
#define X86_CPUID_AMD_FEATURE_EDX_CMOV RT_BIT(15)
/** Bit 16 - PAT - Page Attribute Table. */
#define X86_CPUID_AMD_FEATURE_EDX_PAT RT_BIT(16)
/** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
#define X86_CPUID_AMD_FEATURE_EDX_PSE36 RT_BIT(17)
/** Bit 22 - AXMMX - AMD Extensions to MMX Instructions. */
#define X86_CPUID_AMD_FEATURE_EDX_AXMMX RT_BIT(22)
/** Bit 23 - MMX - Intel MMX Technology. */
#define X86_CPUID_AMD_FEATURE_EDX_MMX RT_BIT(23)
/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
#define X86_CPUID_AMD_FEATURE_EDX_FXSR RT_BIT(24)
/** Bit 25 - FFXSR - AMD fast FXSAVE and FXRSTOR Instructions. */
#define X86_CPUID_AMD_FEATURE_EDX_FFXSR RT_BIT(25)
/** Bit 30 - 3DNOWEXT - AMD Extensions to 3DNow. */
#define X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX RT_BIT(30)
/** Bit 31 - 3DNOW - AMD 3DNow. */
#define X86_CPUID_AMD_FEATURE_EDX_3DNOW RT_BIT(31)
/** Bit 1 - CMPL - Core multi-processing legacy mode. */
#define X86_CPUID_AMD_FEATURE_ECX_CMPL RT_BIT(1)
/** Bit 2 - SVM - AMD VM extensions. */
#define X86_CPUID_AMD_FEATURE_ECX_SVM RT_BIT(2)
/** Bit 3 - EXTAPIC - AMD extended APIC registers starting at 0x400. */
#define X86_CPUID_AMD_FEATURE_ECX_EXT_APIC RT_BIT(3)
/** Bit 4 - CR8L - AMD LOCK MOV CR0 means MOV CR8. */
#define X86_CPUID_AMD_FEATURE_ECX_CR8L RT_BIT(4)
/** Bit 5 - ABM - AMD Advanced bit manipulation. LZCNT instruction support. */
#define X86_CPUID_AMD_FEATURE_ECX_ABM RT_BIT(5)
/** Bit 6 - SSE4A - AMD EXTRQ, INSERTQ, MOVNTSS, and MOVNTSD instruction support. */
#define X86_CPUID_AMD_FEATURE_ECX_SSE4A RT_BIT(6)
/** Bit 7 - MISALIGNSSE - AMD Misaligned SSE mode. */
#define X86_CPUID_AMD_FEATURE_ECX_MISALNSSE RT_BIT(7)
/** Bit 8 - 3DNOWPRF - AMD PREFETCH and PREFETCHW instruction support. */
#define X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF RT_BIT(8)
/** Bit 9 - OSVW - AMD OS visible workaround. */
#define X86_CPUID_AMD_FEATURE_ECX_OSVW RT_BIT(9)
/** Bit 10 - IBS - Instruct based sampling. */
#define X86_CPUID_AMD_FEATURE_ECX_IBS RT_BIT(10)
/** Bit 11 - SSE5 - SSE5 instruction support. */
#define X86_CPUID_AMD_FEATURE_ECX_SSE5 RT_BIT(11)
/** Bit 12 - SKINIT - AMD SKINIT: SKINIT, STGI, and DEV support. */
#define X86_CPUID_AMD_FEATURE_ECX_SKINIT RT_BIT(12)
/** Bit 13 - WDT - AMD Watchdog timer support. */
#define X86_CPUID_AMD_FEATURE_ECX_WDT RT_BIT(13)
/** @} */
/** @name CPUID AMD Feature information.
* CPUID query with EAX=0x80000007.
* @{
*/
/** Bit 0 - TS - Temperature Sensor. */
#define X86_CPUID_AMD_ADVPOWER_EDX_TS RT_BIT(0)
/** Bit 1 - FID - Frequency ID Control. */
#define X86_CPUID_AMD_ADVPOWER_EDX_FID RT_BIT(1)
/** Bit 2 - VID - Voltage ID Control. */
#define X86_CPUID_AMD_ADVPOWER_EDX_VID RT_BIT(2)
/** Bit 3 - TTP - THERMTRIP. */
#define X86_CPUID_AMD_ADVPOWER_EDX_TTP RT_BIT(3)
/** Bit 4 - TM - Hardware Thermal Control. */
#define X86_CPUID_AMD_ADVPOWER_EDX_TM RT_BIT(4)
/** Bit 5 - STC - Software Thermal Control. */
#define X86_CPUID_AMD_ADVPOWER_EDX_STC RT_BIT(5)
/** Bit 6 - MC - 100 Mhz Multiplier Control. */
#define X86_CPUID_AMD_ADVPOWER_EDX_MC RT_BIT(6)
/** Bit 7 - HWPSTATE - Hardware P-State Control. */
#define X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE RT_BIT(7)
/** Bit 8 - TSCINVAR - TSC Invariant. */
#define X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR RT_BIT(8)
/** @} */
/** @name CR0
* @{ */
/** Bit 0 - PE - Protection Enabled */
#define X86_CR0_PE RT_BIT(0)
#define X86_CR0_PROTECTION_ENABLE RT_BIT(0)
/** Bit 1 - MP - Monitor Coprocessor */
#define X86_CR0_MP RT_BIT(1)
#define X86_CR0_MONITOR_COPROCESSOR RT_BIT(1)
/** Bit 2 - EM - Emulation. */
#define X86_CR0_EM RT_BIT(2)
#define X86_CR0_EMULATE_FPU RT_BIT(2)
/** Bit 3 - TS - Task Switch. */
#define X86_CR0_TS RT_BIT(3)
#define X86_CR0_TASK_SWITCH RT_BIT(3)
/** Bit 4 - ET - Extension flag. ('hardcoded' to 1) */
#define X86_CR0_ET RT_BIT(4)
#define X86_CR0_EXTENSION_TYPE RT_BIT(4)
/** Bit 5 - NE - Numeric error. */
#define X86_CR0_NE RT_BIT(5)
#define X86_CR0_NUMERIC_ERROR RT_BIT(5)
/** Bit 16 - WP - Write Protect. */
#define X86_CR0_WP RT_BIT(16)
#define X86_CR0_WRITE_PROTECT RT_BIT(16)
/** Bit 18 - AM - Alignment Mask. */
#define X86_CR0_AM RT_BIT(18)
#define X86_CR0_ALIGMENT_MASK RT_BIT(18)
/** Bit 29 - NW - Not Write-though. */
#define X86_CR0_NW RT_BIT(29)
#define X86_CR0_NOT_WRITE_THROUGH RT_BIT(29)
/** Bit 30 - WP - Cache Disable. */
#define X86_CR0_CD RT_BIT(30)
#define X86_CR0_CACHE_DISABLE RT_BIT(30)
/** Bit 31 - PG - Paging. */
#define X86_CR0_PG RT_BIT(31)
#define X86_CR0_PAGING RT_BIT(31)
/** @} */
/** @name CR3
* @{ */
/** Bit 3 - PWT - Page-level Writes Transparent. */
#define X86_CR3_PWT RT_BIT(3)
/** Bit 4 - PCD - Page-level Cache Disable. */
#define X86_CR3_PCD RT_BIT(4)
/** Bits 12-31 - - Page directory page number. */
#define X86_CR3_PAGE_MASK (0xfffff000)
/** Bits 5-31 - - PAE Page directory page number. */
#define X86_CR3_PAE_PAGE_MASK (0xffffffe0)
/** Bits 12-51 - - AMD64 Page directory page number. */
#define X86_CR3_AMD64_PAGE_MASK UINT64_C(0x000ffffffffff000)
/** @} */
/** @name CR4
* @{ */
/** Bit 0 - VME - Virtual-8086 Mode Extensions. */
#define X86_CR4_VME RT_BIT(0)
/** Bit 1 - PVI - Protected-Mode Virtual Interrupts. */
#define X86_CR4_PVI RT_BIT(1)
/** Bit 2 - TSD - Time Stamp Disable. */
#define X86_CR4_TSD RT_BIT(2)
/** Bit 3 - DE - Debugging Extensions. */
#define X86_CR4_DE RT_BIT(3)
/** Bit 4 - PSE - Page Size Extension. */
#define X86_CR4_PSE RT_BIT(4)
/** Bit 5 - PAE - Physical Address Extension. */
#define X86_CR4_PAE RT_BIT(5)
/** Bit 6 - MCE - Machine-Check Enable. */
#define X86_CR4_MCE RT_BIT(6)
/** Bit 7 - PGE - Page Global Enable. */
#define X86_CR4_PGE RT_BIT(7)
/** Bit 8 - PCE - Performance-Monitoring Counter Enable. */
#define X86_CR4_PCE RT_BIT(8)
/** Bit 9 - OSFSXR - Operating System Support for FXSAVE and FXRSTORE instruction. */
#define X86_CR4_OSFSXR RT_BIT(9)
/** Bit 10 - OSXMMEEXCPT - Operating System Support for Unmasked SIMD Floating-Point Exceptions. */
#define X86_CR4_OSXMMEEXCPT RT_BIT(10)
/** Bit 13 - VMXE - VMX mode is enabled. */
#define X86_CR4_VMXE RT_BIT(13)
/** Bit 14 - SMXE - Safer Mode Extensions Enabled. */
#define X86_CR4_SMXE RT_BIT(14)
/** Bit 17 - PCIDE - Process-Context Identifiers Enabled. */
#define X86_CR4_PCIDE RT_BIT(17)
/** Bit 18 - OSXSAVE - Operating System Support for XSAVE and processor
* extended states. */
#define X86_CR4_OSXSAVE RT_BIT(18)
/** Bit 20 - SMEP - Supervisor-mode Execution Prevention enabled. */
#define X86_CR4_SMEP RT_BIT(20)
/** @} */
/** @name DR6
* @{ */
/** Bit 0 - B0 - Breakpoint 0 condition detected. */
#define X86_DR6_B0 RT_BIT(0)
/** Bit 1 - B1 - Breakpoint 1 condition detected. */
#define X86_DR6_B1 RT_BIT(1)
/** Bit 2 - B2 - Breakpoint 2 condition detected. */
#define X86_DR6_B2 RT_BIT(2)
/** Bit 3 - B3 - Breakpoint 3 condition detected. */
#define X86_DR6_B3 RT_BIT(3)
/** Mask of all the Bx bits. */
#define X86_DR6_B_MASK UINT64_C(0x0000000f)
/** Bit 13 - BD - Debug register access detected. Corresponds to the X86_DR7_GD bit. */
#define X86_DR6_BD RT_BIT(13)
/** Bit 14 - BS - Single step */
#define X86_DR6_BS RT_BIT(14)
/** Bit 15 - BT - Task switch. (TSS T bit.) */
#define X86_DR6_BT RT_BIT(15)
/** Value of DR6 after powerup/reset. */
#define X86_DR6_INIT_VAL UINT64_C(0xFFFF0FF0)
/** Bits which must be 1s in DR6. */
#define X86_DR6_RA1_MASK UINT64_C(0xffff0ff0)
/** Bits which must be 0s in DR6. */
#define X86_DR6_RAZ_MASK RT_BIT_64(12)
/** Bits which must be 0s on writes to DR6. */
#define X86_DR6_MBZ_MASK UINT64_C(0xffffffff00000000)
/** @} */
/** Get the DR6.Bx bit for a the given breakpoint. */
#define X86_DR6_B(iBp) RT_BIT_64(iBp)
/** @name DR7
* @{ */
/** Bit 0 - L0 - Local breakpoint enable. Cleared on task switch. */
#define X86_DR7_L0 RT_BIT(0)
/** Bit 1 - G0 - Global breakpoint enable. Not cleared on task switch. */
#define X86_DR7_G0 RT_BIT(1)
/** Bit 2 - L1 - Local breakpoint enable. Cleared on task switch. */
#define X86_DR7_L1 RT_BIT(2)
/** Bit 3 - G1 - Global breakpoint enable. Not cleared on task switch. */
#define X86_DR7_G1 RT_BIT(3)
/** Bit 4 - L2 - Local breakpoint enable. Cleared on task switch. */
#define X86_DR7_L2 RT_BIT(4)
/** Bit 5 - G2 - Global breakpoint enable. Not cleared on task switch. */
#define X86_DR7_G2 RT_BIT(5)
/** Bit 6 - L3 - Local breakpoint enable. Cleared on task switch. */
#define X86_DR7_L3 RT_BIT(6)
/** Bit 7 - G3 - Global breakpoint enable. Not cleared on task switch. */
#define X86_DR7_G3 RT_BIT(7)
/** Bit 8 - LE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
#define X86_DR7_LE RT_BIT(8)
/** Bit 9 - GE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
#define X86_DR7_GE RT_BIT(9)
/** L0, L1, L2, and L3. */
#define X86_DR7_LE_ALL UINT64_C(0x0000000000000055)
/** L0, L1, L2, and L3. */
#define X86_DR7_GE_ALL UINT64_C(0x00000000000000aa)
/** Bit 13 - GD - General detect enable. Enables emulators to get exceptions when
* any DR register is accessed. */
#define X86_DR7_GD RT_BIT(13)
/** Bit 16 & 17 - R/W0 - Read write field 0. Values X86_DR7_RW_*. */
#define X86_DR7_RW0_MASK (3 << 16)
/** Bit 18 & 19 - LEN0 - Length field 0. Values X86_DR7_LEN_*. */
#define X86_DR7_LEN0_MASK (3 << 18)
/** Bit 20 & 21 - R/W1 - Read write field 0. Values X86_DR7_RW_*. */
#define X86_DR7_RW1_MASK (3 << 20)
/** Bit 22 & 23 - LEN1 - Length field 0. Values X86_DR7_LEN_*. */
#define X86_DR7_LEN1_MASK (3 << 22)
/** Bit 24 & 25 - R/W2 - Read write field 0. Values X86_DR7_RW_*. */
#define X86_DR7_RW2_MASK (3 << 24)
/** Bit 26 & 27 - LEN2 - Length field 0. Values X86_DR7_LEN_*. */
#define X86_DR7_LEN2_MASK (3 << 26)
/** Bit 28 & 29 - R/W3 - Read write field 0. Values X86_DR7_RW_*. */
#define X86_DR7_RW3_MASK (3 << 28)
/** Bit 30 & 31 - LEN3 - Length field 0. Values X86_DR7_LEN_*. */
#define X86_DR7_LEN3_MASK (3 << 30)
/** Bits which reads as 1s. */
#define X86_DR7_RA1_MASK (RT_BIT(10))
/** Bits which reads as zeros. */
#define X86_DR7_RAZ_MASK UINT64_C(0x0000d800)
/** Bits which must be 0s when writing to DR7. */
#define X86_DR7_MBZ_MASK UINT64_C(0xffffffff00000000)
/** Calcs the L bit of Nth breakpoint.
* @param iBp The breakpoint number [0..3].
*/
#define X86_DR7_L(iBp) ( UINT32_C(1) << (iBp * 2) )
/** Calcs the G bit of Nth breakpoint.
* @param iBp The breakpoint number [0..3].
*/
#define X86_DR7_G(iBp) ( UINT32_C(1) << (iBp * 2 + 1) )
/** Calcs the L and G bits of Nth breakpoint.
* @param iBp The breakpoint number [0..3].
*/
#define X86_DR7_L_G(iBp) ( UINT32_C(3) << (iBp * 2) )
/** @name Read/Write values.
* @{ */
/** Break on instruction fetch only. */
#define X86_DR7_RW_EO 0U
/** Break on write only. */
#define X86_DR7_RW_WO 1U
/** Break on I/O read/write. This is only defined if CR4.DE is set. */
#define X86_DR7_RW_IO 2U
/** Break on read or write (but not instruction fetches). */
#define X86_DR7_RW_RW 3U
/** @} */
/** Shifts a X86_DR7_RW_* value to its right place.
* @param iBp The breakpoint number [0..3].
* @param fRw One of the X86_DR7_RW_* value.
*/
#define X86_DR7_RW(iBp, fRw) ( (fRw) << ((iBp) * 4 + 16) )
/** Fetch the the R/Wx bits for a given breakpoint (so it can be compared with
* one of the X86_DR7_RW_XXX constants).
*
* @returns X86_DR7_RW_XXX
* @param uDR7 DR7 value
* @param iBp The breakpoint number [0..3].
*/
#define X86_DR7_GET_RW(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 16) ) & UINT32_C(3) )
/** R/W0, R/W1, R/W2, and R/W3. */
#define X86_DR7_RW_ALL_MASKS UINT32_C(0x33330000)
/** Checks if there are any I/O breakpoint types configured in the RW
* registers. Does NOT check if these are enabled, sorry. */
#define X86_DR7_ANY_RW_IO(uDR7) \
( ( UINT32_C(0x22220000) & (uDR7) ) /* any candidates? */ \
&& ( ( (UINT32_C(0x22220000) & (uDR7) ) >> 1 ) & ~(uDR7) ) )
AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x33330000)) == 0);
AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x22220000)) == 1);
AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x32320000)) == 1);
AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x23230000)) == 1);
AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00000000)) == 0);
AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00010000)) == 0);
AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00020000)) == 1);
AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00030000)) == 0);
AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00040000)) == 0);
/** @name Length values.
* @{ */
#define X86_DR7_LEN_BYTE 0U
#define X86_DR7_LEN_WORD 1U
#define X86_DR7_LEN_QWORD 2U /**< AMD64 long mode only. */
#define X86_DR7_LEN_DWORD 3U
/** @} */
/** Shifts a X86_DR7_LEN_* value to its right place.
* @param iBp The breakpoint number [0..3].
* @param cb One of the X86_DR7_LEN_* values.
*/
#define X86_DR7_LEN(iBp, cb) ( (cb) << ((iBp) * 4 + 18) )
/** Fetch the breakpoint length bits from the DR7 value.
* @param uDR7 DR7 value
* @param iBp The breakpoint number [0..3].
*/
#define X86_DR7_GET_LEN(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 18) ) & UINT32_C(0x3) )
/** Mask used to check if any breakpoints are enabled. */
#define X86_DR7_ENABLED_MASK UINT32_C(0x000000ff)
/** LEN0, LEN1, LEN2, and LEN3. */
#define X86_DR7_LEN_ALL_MASKS UINT32_C(0xcccc0000)
/** R/W0, R/W1, R/W2, R/W3,LEN0, LEN1, LEN2, and LEN3. */
#define X86_DR7_RW_LEN_ALL_MASKS UINT32_C(0xffff0000)
/** Value of DR7 after powerup/reset. */
#define X86_DR7_INIT_VAL 0x400
/** @} */
/** @name Machine Specific Registers
* @{
*/
/** Machine check address register (P5). */
#define MSR_P5_MC_ADDR UINT32_C(0x00000000)
/** Machine check type register (P5). */
#define MSR_P5_MC_TYPE UINT32_C(0x00000001)
/** Time Stamp Counter. */
#define MSR_IA32_TSC 0x10
#define MSR_IA32_CESR UINT32_C(0x00000011)
#define MSR_IA32_CTR0 UINT32_C(0x00000012)
#define MSR_IA32_CTR1 UINT32_C(0x00000013)
#define MSR_IA32_PLATFORM_ID 0x17
#ifndef MSR_IA32_APICBASE /* qemu cpu.h kludge */
# define MSR_IA32_APICBASE 0x1b
/** Local APIC enabled. */
# define MSR_IA32_APICBASE_EN RT_BIT_64(11)
/** X2APIC enabled (requires the EN bit to be set). */
# define MSR_IA32_APICBASE_EXTD RT_BIT_64(10)
/** The processor is the boot strap processor (BSP). */
# define MSR_IA32_APICBASE_BSP RT_BIT_64(8)
/** Minimum base address mask, consult CPUID leaf 0x80000008 for the actual
* width. */
# define MSR_IA32_APICBASE_BASE_MIN UINT64_C(0x0000000ffffff000)
#endif
/** Undocumented intel MSR for reporting thread and core counts.
* Judging from the XNU sources, it seems to be introduced in Nehalem. The
* first 16 bits is the thread count. The next 16 bits the core count, except
* on Westmere where it seems it's only the next 4 bits for some reason. */
#define MSR_CORE_THREAD_COUNT 0x35
/** CPU Feature control. */
#define MSR_IA32_FEATURE_CONTROL 0x3A
#define MSR_IA32_FEATURE_CONTROL_LOCK RT_BIT(0)
#define MSR_IA32_FEATURE_CONTROL_SMX_VMXON RT_BIT(1)
#define MSR_IA32_FEATURE_CONTROL_VMXON RT_BIT(2)
/** BIOS update trigger (microcode update). */
#define MSR_IA32_BIOS_UPDT_TRIG 0x79
/** BIOS update signature (microcode). */
#define MSR_IA32_BIOS_SIGN_ID 0x8B
/** General performance counter no. 0. */
#define MSR_IA32_PMC0 0xC1
/** General performance counter no. 1. */
#define MSR_IA32_PMC1 0xC2
/** General performance counter no. 2. */
#define MSR_IA32_PMC2 0xC3
/** General performance counter no. 3. */
#define MSR_IA32_PMC3 0xC4
/** Nehalem power control. */
#define MSR_IA32_PLATFORM_INFO 0xCE
/** Get FSB clock status (Intel-specific). */
#define MSR_IA32_FSB_CLOCK_STS 0xCD
/** C-State configuration control. Intel specific: Nehalem, Sandy Bridge. */
#define MSR_PKG_CST_CONFIG_CONTROL UINT32_C(0x000000e2)
/** C0 Maximum Frequency Clock Count */
#define MSR_IA32_MPERF 0xE7
/** C0 Actual Frequency Clock Count */
#define MSR_IA32_APERF 0xE8
/** MTRR Capabilities. */
#define MSR_IA32_MTRR_CAP 0xFE
/** Cache control/info. */
#define MSR_BBL_CR_CTL3 UINT32_C(0x11e)
#ifndef MSR_IA32_SYSENTER_CS /* qemu cpu.h kludge */
/** SYSENTER_CS - the R0 CS, indirectly giving R0 SS, R3 CS and R3 DS.
* R0 SS == CS + 8
* R3 CS == CS + 16
* R3 SS == CS + 24
*/
#define MSR_IA32_SYSENTER_CS 0x174
/** SYSENTER_ESP - the R0 ESP. */
#define MSR_IA32_SYSENTER_ESP 0x175
/** SYSENTER_EIP - the R0 EIP. */
#define MSR_IA32_SYSENTER_EIP 0x176
#endif
/** Machine Check Global Capabilities Register. */
#define MSR_IA32_MCG_CAP 0x179
/** Machine Check Global Status Register. */
#define MSR_IA32_MCG_STATUS 0x17A
/** Machine Check Global Control Register. */
#define MSR_IA32_MCG_CTRL 0x17B
/** Page Attribute Table. */
#define MSR_IA32_CR_PAT 0x277
/** Performance counter MSRs. (Intel only) */
#define MSR_IA32_PERFEVTSEL0 0x186
#define MSR_IA32_PERFEVTSEL1 0x187
/** Flexible ratio, seems to be undocumented, used by XNU (tsc.c).
* The 16th bit whether flex ratio is being used, in which case bits 15:8
* holds a ratio that Apple takes for TSC granularity.
*
* @note This MSR conflics the P4 MSR_MCG_R12 register. */
#define MSR_FLEX_RATIO 0x194
/** Performance state value and starting with Intel core more.
* Apple uses the >=core features to determine TSC granularity on older CPUs. */
#define MSR_IA32_PERF_STATUS 0x198
#define MSR_IA32_PERF_CTL 0x199
#define MSR_IA32_THERM_STATUS 0x19c
/** Enable misc. processor features (R/W). */
#define MSR_IA32_MISC_ENABLE 0x1A0
/** Enable fast-strings feature (for REP MOVS and REP STORS). */
#define MSR_IA32_MISC_ENABLE_FAST_STRINGS RT_BIT_64(0)
/** Automatic Thermal Control Circuit Enable (R/W). */
#define MSR_IA32_MISC_ENABLE_TCC RT_BIT_64(3)
/** Performance Monitoring Available (R). */
#define MSR_IA32_MISC_ENABLE_PERF_MON RT_BIT_64(7)
/** Branch Trace Storage Unavailable (R/O). */
#define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL RT_BIT_64(11)
/** Precise Event Based Sampling (PEBS) Unavailable (R/O). */
#define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL RT_BIT_64(12)
/** Enhanced Intel SpeedStep Technology Enable (R/W). */
#define MSR_IA32_MISC_ENABLE_SST_ENABLE RT_BIT_64(16)
/** If MONITOR/MWAIT is supported (R/W). */
#define MSR_IA32_MISC_ENABLE_MONITOR RT_BIT_64(18)
/** Limit CPUID Maxval to 3 leafs (R/W). */
#define MSR_IA32_MISC_ENABLE_LIMIT_CPUID RT_BIT_64(22)
/** When set to 1, xTPR messages are disabled (R/W). */
#define MSR_IA32_MISC_ENABLE_XTPR_MSG_DISABLE RT_BIT_64(23)
/** When set to 1, the Execute Disable Bit feature (XD Bit) is disabled (R/W). */
#define MSR_IA32_MISC_ENABLE_XD_DISABLE RT_BIT_64(34)
/** Trace/Profile Resource Control (R/W) */
#define MSR_IA32_DEBUGCTL UINT32_C(0x000001d9)
/** The number (0..3 or 0..15) of the last branch record register on P4 and
* related Xeons. */
#define MSR_P4_LASTBRANCH_TOS UINT32_C(0x000001da)
/** @name Last branch registers for P4 and Xeon, models 0 thru 2.
* @{ */
#define MSR_P4_LASTBRANCH_0 UINT32_C(0x000001db)
#define MSR_P4_LASTBRANCH_1 UINT32_C(0x000001dc)
#define MSR_P4_LASTBRANCH_2 UINT32_C(0x000001dd)
#define MSR_P4_LASTBRANCH_3 UINT32_C(0x000001de)
/** @} */
#define IA32_MTRR_PHYSBASE0 0x200
#define IA32_MTRR_PHYSMASK0 0x201
#define IA32_MTRR_PHYSBASE1 0x202
#define IA32_MTRR_PHYSMASK1 0x203
#define IA32_MTRR_PHYSBASE2 0x204
#define IA32_MTRR_PHYSMASK2 0x205
#define IA32_MTRR_PHYSBASE3 0x206
#define IA32_MTRR_PHYSMASK3 0x207
#define IA32_MTRR_PHYSBASE4 0x208
#define IA32_MTRR_PHYSMASK4 0x209
#define IA32_MTRR_PHYSBASE5 0x20a
#define IA32_MTRR_PHYSMASK5 0x20b
#define IA32_MTRR_PHYSBASE6 0x20c
#define IA32_MTRR_PHYSMASK6 0x20d
#define IA32_MTRR_PHYSBASE7 0x20e
#define IA32_MTRR_PHYSMASK7 0x20f
#define IA32_MTRR_PHYSBASE8 0x210
#define IA32_MTRR_PHYSMASK8 0x211
#define IA32_MTRR_PHYSBASE9 0x212
#define IA32_MTRR_PHYSMASK9 0x213
/** Fixed range MTRRs.
* @{ */
#define IA32_MTRR_FIX64K_00000 0x250
#define IA32_MTRR_FIX16K_80000 0x258
#define IA32_MTRR_FIX16K_A0000 0x259
#define IA32_MTRR_FIX4K_C0000 0x268
#define IA32_MTRR_FIX4K_C8000 0x269
#define IA32_MTRR_FIX4K_D0000 0x26a
#define IA32_MTRR_FIX4K_D8000 0x26b
#define IA32_MTRR_FIX4K_E0000 0x26c
#define IA32_MTRR_FIX4K_E8000 0x26d
#define IA32_MTRR_FIX4K_F0000 0x26e
#define IA32_MTRR_FIX4K_F8000 0x26f
/** @} */
/** MTRR Default Range. */
#define MSR_IA32_MTRR_DEF_TYPE 0x2FF
#define MSR_IA32_MC0_CTL 0x400
#define MSR_IA32_MC0_STATUS 0x401
/** Basic VMX information. */
#define MSR_IA32_VMX_BASIC_INFO 0x480
/** Allowed settings for pin-based VM execution controls */
#define MSR_IA32_VMX_PINBASED_CTLS 0x481
/** Allowed settings for proc-based VM execution controls */
#define MSR_IA32_VMX_PROCBASED_CTLS 0x482
/** Allowed settings for the VMX exit controls. */
#define MSR_IA32_VMX_EXIT_CTLS 0x483
/** Allowed settings for the VMX entry controls. */
#define MSR_IA32_VMX_ENTRY_CTLS 0x484
/** Misc VMX info. */
#define MSR_IA32_VMX_MISC 0x485
/** Fixed cleared bits in CR0. */
#define MSR_IA32_VMX_CR0_FIXED0 0x486
/** Fixed set bits in CR0. */
#define MSR_IA32_VMX_CR0_FIXED1 0x487
/** Fixed cleared bits in CR4. */
#define MSR_IA32_VMX_CR4_FIXED0 0x488
/** Fixed set bits in CR4. */
#define MSR_IA32_VMX_CR4_FIXED1 0x489
/** Information for enumerating fields in the VMCS. */
#define MSR_IA32_VMX_VMCS_ENUM 0x48A
/** Allowed settings for the VM-functions controls. */
#define MSR_IA32_VMX_VMFUNC 0x491
/** Allowed settings for secondary proc-based VM execution controls */
#define MSR_IA32_VMX_PROCBASED_CTLS2 0x48B
/** EPT capabilities. */
#define MSR_IA32_VMX_EPT_VPID_CAP 0x48C
/** DS Save Area (R/W). */
#define MSR_IA32_DS_AREA 0x600
/** Running Average Power Limit (RAPL) power units. */
#define MSR_RAPL_POWER_UNIT 0x606
/** X2APIC MSR ranges. */
#define MSR_IA32_X2APIC_START 0x800
#define MSR_IA32_X2APIC_TPR 0x808
#define MSR_IA32_X2APIC_END 0xBFF
/** K6 EFER - Extended Feature Enable Register. */
#define MSR_K6_EFER UINT32_C(0xc0000080)
/** @todo document EFER */
/** Bit 0 - SCE - System call extensions (SYSCALL / SYSRET). (R/W) */
#define MSR_K6_EFER_SCE RT_BIT(0)
/** Bit 8 - LME - Long mode enabled. (R/W) */
#define MSR_K6_EFER_LME RT_BIT(8)
/** Bit 10 - LMA - Long mode active. (R) */
#define MSR_K6_EFER_LMA RT_BIT(10)
/** Bit 11 - NXE - No-Execute Page Protection Enabled. (R/W) */
#define MSR_K6_EFER_NXE RT_BIT(11)
/** Bit 12 - SVME - Secure VM Extension Enabled. (R/W) */
#define MSR_K6_EFER_SVME RT_BIT(12)
/** Bit 13 - LMSLE - Long Mode Segment Limit Enable. (R/W?) */
#define MSR_K6_EFER_LMSLE RT_BIT(13)
/** Bit 14 - FFXSR - Fast FXSAVE / FXRSTOR (skip XMM*). (R/W) */
#define MSR_K6_EFER_FFXSR RT_BIT(14)
/** K6 STAR - SYSCALL/RET targets. */
#define MSR_K6_STAR UINT32_C(0xc0000081)
/** Shift value for getting the SYSRET CS and SS value. */
#define MSR_K6_STAR_SYSRET_CS_SS_SHIFT 48
/** Shift value for getting the SYSCALL CS and SS value. */
#define MSR_K6_STAR_SYSCALL_CS_SS_SHIFT 32
/** Selector mask for use after shifting. */
#define MSR_K6_STAR_SEL_MASK UINT32_C(0xffff)
/** The mask which give the SYSCALL EIP. */
#define MSR_K6_STAR_SYSCALL_EIP_MASK UINT32_C(0xffffffff)
/** K6 WHCR - Write Handling Control Register. */
#define MSR_K6_WHCR UINT32_C(0xc0000082)
/** K6 UWCCR - UC/WC Cacheability Control Register. */
#define MSR_K6_UWCCR UINT32_C(0xc0000085)
/** K6 PSOR - Processor State Observability Register. */
#define MSR_K6_PSOR UINT32_C(0xc0000087)
/** K6 PFIR - Page Flush/Invalidate Register. */
#define MSR_K6_PFIR UINT32_C(0xc0000088)
/** Performance counter MSRs. (AMD only) */
#define MSR_K7_EVNTSEL0 UINT32_C(0xc0010000)
#define MSR_K7_EVNTSEL1 UINT32_C(0xc0010001)
#define MSR_K7_EVNTSEL2 UINT32_C(0xc0010002)
#define MSR_K7_EVNTSEL3 UINT32_C(0xc0010003)
#define MSR_K7_PERFCTR0 UINT32_C(0xc0010004)
#define MSR_K7_PERFCTR1 UINT32_C(0xc0010005)
#define MSR_K7_PERFCTR2 UINT32_C(0xc0010006)
#define MSR_K7_PERFCTR3 UINT32_C(0xc0010007)
/** K8 LSTAR - Long mode SYSCALL target (RIP). */
#define MSR_K8_LSTAR UINT32_C(0xc0000082)
/** K8 CSTAR - Compatibility mode SYSCALL target (RIP). */
#define MSR_K8_CSTAR UINT32_C(0xc0000083)
/** K8 SF_MASK - SYSCALL flag mask. (aka SFMASK) */
#define MSR_K8_SF_MASK UINT32_C(0xc0000084)
/** K8 FS.base - The 64-bit base FS register. */
#define MSR_K8_FS_BASE UINT32_C(0xc0000100)
/** K8 GS.base - The 64-bit base GS register. */
#define MSR_K8_GS_BASE UINT32_C(0xc0000101)
/** K8 KernelGSbase - Used with SWAPGS. */
#define MSR_K8_KERNEL_GS_BASE UINT32_C(0xc0000102)
/** K8 TSC_AUX - Used with RDTSCP. */
#define MSR_K8_TSC_AUX UINT32_C(0xc0000103)
#define MSR_K8_SYSCFG UINT32_C(0xc0010010)
#define MSR_K8_HWCR UINT32_C(0xc0010015)
#define MSR_K8_IORRBASE0 UINT32_C(0xc0010016)
#define MSR_K8_IORRMASK0 UINT32_C(0xc0010017)
#define MSR_K8_IORRBASE1 UINT32_C(0xc0010018)
#define MSR_K8_IORRMASK1 UINT32_C(0xc0010019)
#define MSR_K8_TOP_MEM1 UINT32_C(0xc001001a)
#define MSR_K8_TOP_MEM2 UINT32_C(0xc001001d)
/** North bridge config? See BIOS & Kernel dev guides for
* details. */
#define MSR_K8_NB_CFG UINT32_C(0xc001001f)
/** Hypertransport interrupt pending register.
* "BIOS and Kernel Developer's Guide for AMD NPT Family 0Fh Processors" */
#define MSR_K8_INT_PENDING UINT32_C(0xc0010055)
#define MSR_K8_VM_CR UINT32_C(0xc0010114)
#define MSR_K8_VM_CR_SVM_DISABLE RT_BIT(4)
#define MSR_K8_IGNNE UINT32_C(0xc0010115)
#define MSR_K8_SMM_CTL UINT32_C(0xc0010116)
/** SVM - VM_HSAVE_PA - Physical address for saving and restoring
* host state during world switch. */
#define MSR_K8_VM_HSAVE_PA UINT32_C(0xc0010117)
/** @} */
/** @name Page Table / Directory / Directory Pointers / L4.
* @{
*/
/** Page table/directory entry as an unsigned integer. */
typedef uint32_t X86PGUINT;
/** Pointer to a page table/directory table entry as an unsigned integer. */
typedef X86PGUINT *PX86PGUINT;
/** Pointer to an const page table/directory table entry as an unsigned integer. */
typedef X86PGUINT const *PCX86PGUINT;
/** Number of entries in a 32-bit PT/PD. */
#define X86_PG_ENTRIES 1024
/** PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
typedef uint64_t X86PGPAEUINT;
/** Pointer to a PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
typedef X86PGPAEUINT *PX86PGPAEUINT;
/** Pointer to an const PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
typedef X86PGPAEUINT const *PCX86PGPAEUINT;
/** Number of entries in a PAE PT/PD. */
#define X86_PG_PAE_ENTRIES 512
/** Number of entries in a PAE PDPT. */
#define X86_PG_PAE_PDPE_ENTRIES 4
/** Number of entries in an AMD64 PT/PD/PDPT/L4/L5. */
#define X86_PG_AMD64_ENTRIES X86_PG_PAE_ENTRIES
/** Number of entries in an AMD64 PDPT.
* Just for complementing X86_PG_PAE_PDPE_ENTRIES, using X86_PG_AMD64_ENTRIES for this is fine too. */
#define X86_PG_AMD64_PDPE_ENTRIES X86_PG_AMD64_ENTRIES
/** The size of a 4KB page. */
#define X86_PAGE_4K_SIZE _4K
/** The page shift of a 4KB page. */
#define X86_PAGE_4K_SHIFT 12
/** The 4KB page offset mask. */
#define X86_PAGE_4K_OFFSET_MASK 0xfff
/** The 4KB page base mask for virtual addresses. */
#define X86_PAGE_4K_BASE_MASK 0xfffffffffffff000ULL
/** The 4KB page base mask for virtual addresses - 32bit version. */
#define X86_PAGE_4K_BASE_MASK_32 0xfffff000U
/** The size of a 2MB page. */
#define X86_PAGE_2M_SIZE _2M
/** The page shift of a 2MB page. */
#define X86_PAGE_2M_SHIFT 21
/** The 2MB page offset mask. */
#define X86_PAGE_2M_OFFSET_MASK 0x001fffff
/** The 2MB page base mask for virtual addresses. */
#define X86_PAGE_2M_BASE_MASK 0xffffffffffe00000ULL
/** The 2MB page base mask for virtual addresses - 32bit version. */
#define X86_PAGE_2M_BASE_MASK_32 0xffe00000U
/** The size of a 4MB page. */
#define X86_PAGE_4M_SIZE _4M
/** The page shift of a 4MB page. */
#define X86_PAGE_4M_SHIFT 22
/** The 4MB page offset mask. */
#define X86_PAGE_4M_OFFSET_MASK 0x003fffff
/** The 4MB page base mask for virtual addresses. */
#define X86_PAGE_4M_BASE_MASK 0xffffffffffc00000ULL
/** The 4MB page base mask for virtual addresses - 32bit version. */
#define X86_PAGE_4M_BASE_MASK_32 0xffc00000U
/**
* Check if the given address is canonical.
*/
#define X86_IS_CANONICAL(a_u64Addr) ((uint64_t)(a_u64Addr) + UINT64_C(0x800000000000) < UINT64_C(0x1000000000000))
/** @name Page Table Entry
* @{
*/
/** Bit 0 - P - Present bit. */
#define X86_PTE_BIT_P 0
/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
#define X86_PTE_BIT_RW 1
/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
#define X86_PTE_BIT_US 2
/** Bit 3 - PWT - Page level write thru bit. */
#define X86_PTE_BIT_PWT 3
/** Bit 4 - PCD - Page level cache disable bit. */
#define X86_PTE_BIT_PCD 4
/** Bit 5 - A - Access bit. */
#define X86_PTE_BIT_A 5
/** Bit 6 - D - Dirty bit. */
#define X86_PTE_BIT_D 6
/** Bit 7 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
#define X86_PTE_BIT_PAT 7
/** Bit 8 - G - Global flag. */
#define X86_PTE_BIT_G 8
/** Bit 0 - P - Present bit mask. */
#define X86_PTE_P RT_BIT(0)
/** Bit 1 - R/W - Read (clear) / Write (set) bit mask. */
#define X86_PTE_RW RT_BIT(1)
/** Bit 2 - U/S - User (set) / Supervisor (clear) bit mask. */
#define X86_PTE_US RT_BIT(2)
/** Bit 3 - PWT - Page level write thru bit mask. */
#define X86_PTE_PWT RT_BIT(3)
/** Bit 4 - PCD - Page level cache disable bit mask. */
#define X86_PTE_PCD RT_BIT(4)
/** Bit 5 - A - Access bit mask. */
#define X86_PTE_A RT_BIT(5)
/** Bit 6 - D - Dirty bit mask. */
#define X86_PTE_D RT_BIT(6)
/** Bit 7 - PAT - Page Attribute Table index bit mask. Reserved and 0 if not supported. */
#define X86_PTE_PAT RT_BIT(7)
/** Bit 8 - G - Global bit mask. */
#define X86_PTE_G RT_BIT(8)
/** Bits 9-11 - - Available for use to system software. */
#define X86_PTE_AVL_MASK (RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
/** Bits 12-31 - - Physical Page number of the next level. */
#define X86_PTE_PG_MASK ( 0xfffff000 )
/** Bits 12-51 - - PAE - Physical Page number of the next level. */
#define X86_PTE_PAE_PG_MASK UINT64_C(0x000ffffffffff000)
/** Bits 63 - NX - PAE/LM - No execution flag. */
#define X86_PTE_PAE_NX RT_BIT_64(63)
/** Bits 62-52 - - PAE - MBZ bits when NX is active. */
#define X86_PTE_PAE_MBZ_MASK_NX UINT64_C(0x7ff0000000000000)
/** Bits 63-52 - - PAE - MBZ bits when no NX. */
#define X86_PTE_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff0000000000000)
/** No bits - - LM - MBZ bits when NX is active. */
#define X86_PTE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000000)
/** Bits 63 - - LM - MBZ bits when no NX. */
#define X86_PTE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000000)
/**
* Page table entry.
*/
typedef struct X86PTEBITS
{
/** Flags whether(=1) or not the page is present. */
unsigned u1Present : 1;
/** Read(=0) / Write(=1) flag. */
unsigned u1Write : 1;
/** User(=1) / Supervisor (=0) flag. */
unsigned u1User : 1;
/** Write Thru flag. If PAT enabled, bit 0 of the index. */
unsigned u1WriteThru : 1;
/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
unsigned u1CacheDisable : 1;
/** Accessed flag.
* Indicates that the page have been read or written to. */
unsigned u1Accessed : 1;
/** Dirty flag.
* Indicates that the page has been written to. */
unsigned u1Dirty : 1;
/** Reserved / If PAT enabled, bit 2 of the index. */
unsigned u1PAT : 1;
/** Global flag. (Ignored in all but final level.) */
unsigned u1Global : 1;
/** Available for use to system software. */
unsigned u3Available : 3;
/** Physical Page number of the next level. */
unsigned u20PageNo : 20;
} X86PTEBITS;
/** Pointer to a page table entry. */
typedef X86PTEBITS *PX86PTEBITS;
/** Pointer to a const page table entry. */
typedef const X86PTEBITS *PCX86PTEBITS;
/**
* Page table entry.
*/
typedef union X86PTE
{
/** Unsigned integer view */
X86PGUINT u;
/** Bit field view. */
X86PTEBITS n;
/** 32-bit view. */
uint32_t au32[1];
/** 16-bit view. */
uint16_t au16[2];
/** 8-bit view. */
uint8_t au8[4];
} X86PTE;
/** Pointer to a page table entry. */
typedef X86PTE *PX86PTE;
/** Pointer to a const page table entry. */
typedef const X86PTE *PCX86PTE;
/**
* PAE page table entry.
*/
typedef struct X86PTEPAEBITS
{
/** Flags whether(=1) or not the page is present. */
uint32_t u1Present : 1;
/** Read(=0) / Write(=1) flag. */
uint32_t u1Write : 1;
/** User(=1) / Supervisor(=0) flag. */
uint32_t u1User : 1;
/** Write Thru flag. If PAT enabled, bit 0 of the index. */
uint32_t u1WriteThru : 1;
/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
uint32_t u1CacheDisable : 1;
/** Accessed flag.
* Indicates that the page have been read or written to. */
uint32_t u1Accessed : 1;
/** Dirty flag.
* Indicates that the page has been written to. */
uint32_t u1Dirty : 1;
/** Reserved / If PAT enabled, bit 2 of the index. */
uint32_t u1PAT : 1;
/** Global flag. (Ignored in all but final level.) */
uint32_t u1Global : 1;
/** Available for use to system software. */
uint32_t u3Available : 3;
/** Physical Page number of the next level - Low Part. Don't use this. */
uint32_t u20PageNoLow : 20;
/** Physical Page number of the next level - High Part. Don't use this. */
uint32_t u20PageNoHigh : 20;
/** MBZ bits */
uint32_t u11Reserved : 11;
/** No Execute flag. */
uint32_t u1NoExecute : 1;
} X86PTEPAEBITS;
/** Pointer to a page table entry. */
typedef X86PTEPAEBITS *PX86PTEPAEBITS;
/** Pointer to a page table entry. */
typedef const X86PTEPAEBITS *PCX86PTEPAEBITS;
/**
* PAE Page table entry.
*/
typedef union X86PTEPAE
{
/** Unsigned integer view */
X86PGPAEUINT u;
/** Bit field view. */
X86PTEPAEBITS n;
/** 32-bit view. */
uint32_t au32[2];
/** 16-bit view. */
uint16_t au16[4];
/** 8-bit view. */
uint8_t au8[8];
} X86PTEPAE;
/** Pointer to a PAE page table entry. */
typedef X86PTEPAE *PX86PTEPAE;
/** Pointer to a const PAE page table entry. */
typedef const X86PTEPAE *PCX86PTEPAE;
/** @} */
/**
* Page table.
*/
typedef struct X86PT
{
/** PTE Array. */
X86PTE a[X86_PG_ENTRIES];
} X86PT;
/** Pointer to a page table. */
typedef X86PT *PX86PT;
/** Pointer to a const page table. */
typedef const X86PT *PCX86PT;
/** The page shift to get the PT index. */
#define X86_PT_SHIFT 12
/** The PT index mask (apply to a shifted page address). */
#define X86_PT_MASK 0x3ff
/**
* Page directory.
*/
typedef struct X86PTPAE
{
/** PTE Array. */
X86PTEPAE a[X86_PG_PAE_ENTRIES];
} X86PTPAE;
/** Pointer to a page table. */
typedef X86PTPAE *PX86PTPAE;
/** Pointer to a const page table. */
typedef const X86PTPAE *PCX86PTPAE;
/** The page shift to get the PA PTE index. */
#define X86_PT_PAE_SHIFT 12
/** The PAE PT index mask (apply to a shifted page address). */
#define X86_PT_PAE_MASK 0x1ff
/** @name 4KB Page Directory Entry
* @{
*/
/** Bit 0 - P - Present bit. */
#define X86_PDE_P RT_BIT(0)
/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
#define X86_PDE_RW RT_BIT(1)
/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
#define X86_PDE_US RT_BIT(2)
/** Bit 3 - PWT - Page level write thru bit. */
#define X86_PDE_PWT RT_BIT(3)
/** Bit 4 - PCD - Page level cache disable bit. */
#define X86_PDE_PCD RT_BIT(4)
/** Bit 5 - A - Access bit. */
#define X86_PDE_A RT_BIT(5)
/** Bit 7 - PS - Page size attribute.
* Clear mean 4KB pages, set means large pages (2/4MB). */
#define X86_PDE_PS RT_BIT(7)
/** Bits 9-11 - - Available for use to system software. */
#define X86_PDE_AVL_MASK (RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
/** Bits 12-31 - - Physical Page number of the next level. */
#define X86_PDE_PG_MASK ( 0xfffff000 )
/** Bits 12-51 - - PAE - Physical Page number of the next level. */
#define X86_PDE_PAE_PG_MASK UINT64_C(0x000ffffffffff000)
/** Bits 63 - NX - PAE/LM - No execution flag. */
#define X86_PDE_PAE_NX RT_BIT_64(63)
/** Bits 62-52, 7 - - PAE - MBZ bits when NX is active. */
#define X86_PDE_PAE_MBZ_MASK_NX UINT64_C(0x7ff0000000000080)
/** Bits 63-52, 7 - - PAE - MBZ bits when no NX. */
#define X86_PDE_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff0000000000080)
/** Bit 7 - - LM - MBZ bits when NX is active. */
#define X86_PDE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000080)
/** Bits 63, 7 - - LM - MBZ bits when no NX. */
#define X86_PDE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000080)
/**
* Page directory entry.
*/
typedef struct X86PDEBITS
{
/** Flags whether(=1) or not the page is present. */
unsigned u1Present : 1;
/** Read(=0) / Write(=1) flag. */
unsigned u1Write : 1;
/** User(=1) / Supervisor (=0) flag. */
unsigned u1User : 1;
/** Write Thru flag. If PAT enabled, bit 0 of the index. */
unsigned u1WriteThru : 1;
/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
unsigned u1CacheDisable : 1;
/** Accessed flag.
* Indicates that the page has been read or written to. */
unsigned u1Accessed : 1;
/** Reserved / Ignored (dirty bit). */
unsigned u1Reserved0 : 1;
/** Size bit if PSE is enabled - in any event it's 0. */
unsigned u1Size : 1;
/** Reserved / Ignored (global bit). */
unsigned u1Reserved1 : 1;
/** Available for use to system software. */
unsigned u3Available : 3;
/** Physical Page number of the next level. */
unsigned u20PageNo : 20;
} X86PDEBITS;
/** Pointer to a page directory entry. */
typedef X86PDEBITS *PX86PDEBITS;
/** Pointer to a const page directory entry. */
typedef const X86PDEBITS *PCX86PDEBITS;
/**
* PAE page directory entry.
*/
typedef struct X86PDEPAEBITS
{
/** Flags whether(=1) or not the page is present. */
uint32_t u1Present : 1;
/** Read(=0) / Write(=1) flag. */
uint32_t u1Write : 1;
/** User(=1) / Supervisor (=0) flag. */
uint32_t u1User : 1;
/** Write Thru flag. If PAT enabled, bit 0 of the index. */
uint32_t u1WriteThru : 1;
/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
uint32_t u1CacheDisable : 1;
/** Accessed flag.
* Indicates that the page has been read or written to. */
uint32_t u1Accessed : 1;
/** Reserved / Ignored (dirty bit). */
uint32_t u1Reserved0 : 1;
/** Size bit if PSE is enabled - in any event it's 0. */
uint32_t u1Size : 1;
/** Reserved / Ignored (global bit). / */
uint32_t u1Reserved1 : 1;
/** Available for use to system software. */
uint32_t u3Available : 3;
/** Physical Page number of the next level - Low Part. Don't use! */
uint32_t u20PageNoLow : 20;
/** Physical Page number of the next level - High Part. Don't use! */
uint32_t u20PageNoHigh : 20;
/** MBZ bits */
uint32_t u11Reserved : 11;
/** No Execute flag. */
uint32_t u1NoExecute : 1;
} X86PDEPAEBITS;
/** Pointer to a page directory entry. */
typedef X86PDEPAEBITS *PX86PDEPAEBITS;
/** Pointer to a const page directory entry. */
typedef const X86PDEPAEBITS *PCX86PDEPAEBITS;
/** @} */
/** @name 2/4MB Page Directory Entry
* @{
*/
/** Bit 0 - P - Present bit. */
#define X86_PDE4M_P RT_BIT(0)
/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
#define X86_PDE4M_RW RT_BIT(1)
/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
#define X86_PDE4M_US RT_BIT(2)
/** Bit 3 - PWT - Page level write thru bit. */
#define X86_PDE4M_PWT RT_BIT(3)
/** Bit 4 - PCD - Page level cache disable bit. */
#define X86_PDE4M_PCD RT_BIT(4)
/** Bit 5 - A - Access bit. */
#define X86_PDE4M_A RT_BIT(5)
/** Bit 6 - D - Dirty bit. */
#define X86_PDE4M_D RT_BIT(6)
/** Bit 7 - PS - Page size attribute. Clear mean 4KB pages, set means large pages (2/4MB). */
#define X86_PDE4M_PS RT_BIT(7)
/** Bit 8 - G - Global flag. */
#define X86_PDE4M_G RT_BIT(8)
/** Bits 9-11 - AVL - Available for use to system software. */
#define X86_PDE4M_AVL (RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
/** Bit 12 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
#define X86_PDE4M_PAT RT_BIT(12)
/** Shift to get from X86_PTE_PAT to X86_PDE4M_PAT. */
#define X86_PDE4M_PAT_SHIFT (12 - 7)
/** Bits 22-31 - - Physical Page number. */
#define X86_PDE4M_PG_MASK ( 0xffc00000 )
/** Bits 20-13 - - Physical Page number high part (32-39 bits). AMD64 hack. */
#define X86_PDE4M_PG_HIGH_MASK ( 0x001fe000 )
/** The number of bits to the high part of the page number. */
#define X86_PDE4M_PG_HIGH_SHIFT 19
/** Bit 21 - - MBZ bits for AMD CPUs, no PSE36. */
#define X86_PDE4M_MBZ_MASK RT_BIT_32(21)
/** Bits 21-51 - - PAE/LM - Physical Page number.
* (Bits 40-51 (long mode) & bits 36-51 (pae legacy) are reserved according to the Intel docs; AMD allows for more.) */
#define X86_PDE2M_PAE_PG_MASK UINT64_C(0x000fffffffe00000)
/** Bits 63 - NX - PAE/LM - No execution flag. */
#define X86_PDE2M_PAE_NX RT_BIT_64(63)
/** Bits 62-52, 20-13 - - PAE - MBZ bits when NX is active. */
#define X86_PDE2M_PAE_MBZ_MASK_NX UINT64_C(0x7ff00000001fe000)
/** Bits 63-52, 20-13 - - PAE - MBZ bits when no NX. */
#define X86_PDE2M_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff00000001fe000)
/** Bits 20-13 - - LM - MBZ bits when NX is active. */
#define X86_PDE2M_LM_MBZ_MASK_NX UINT64_C(0x00000000001fe000)
/** Bits 63, 20-13 - - LM - MBZ bits when no NX. */
#define X86_PDE2M_LM_MBZ_MASK_NO_NX UINT64_C(0x80000000001fe000)
/**
* 4MB page directory entry.
*/
typedef struct X86PDE4MBITS
{
/** Flags whether(=1) or not the page is present. */
unsigned u1Present : 1;
/** Read(=0) / Write(=1) flag. */
unsigned u1Write : 1;
/** User(=1) / Supervisor (=0) flag. */
unsigned u1User : 1;
/** Write Thru flag. If PAT enabled, bit 0 of the index. */
unsigned u1WriteThru : 1;
/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
unsigned u1CacheDisable : 1;
/** Accessed flag.
* Indicates that the page have been read or written to. */
unsigned u1Accessed : 1;
/** Dirty flag.
* Indicates that the page has been written to. */
unsigned u1Dirty : 1;
/** Page size flag - always 1 for 4MB entries. */
unsigned u1Size : 1;
/** Global flag. */
unsigned u1Global : 1;
/** Available for use to system software. */
unsigned u3Available : 3;
/** Reserved / If PAT enabled, bit 2 of the index. */
unsigned u1PAT : 1;
/** Bits 32-39 of the page number on AMD64.
* This AMD64 hack allows accessing 40bits of physical memory without PAE. */
unsigned u8PageNoHigh : 8;
/** Reserved. */
unsigned u1Reserved : 1;
/** Physical Page number of the page. */
unsigned u10PageNo : 10;
} X86PDE4MBITS;
/** Pointer to a page table entry. */
typedef X86PDE4MBITS *PX86PDE4MBITS;
/** Pointer to a const page table entry. */
typedef const X86PDE4MBITS *PCX86PDE4MBITS;
/**
* 2MB PAE page directory entry.
*/
typedef struct X86PDE2MPAEBITS
{
/** Flags whether(=1) or not the page is present. */
uint32_t u1Present : 1;
/** Read(=0) / Write(=1) flag. */
uint32_t u1Write : 1;
/** User(=1) / Supervisor(=0) flag. */
uint32_t u1User : 1;
/** Write Thru flag. If PAT enabled, bit 0 of the index. */
uint32_t u1WriteThru : 1;
/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
uint32_t u1CacheDisable : 1;
/** Accessed flag.
* Indicates that the page have been read or written to. */
uint32_t u1Accessed : 1;
/** Dirty flag.
* Indicates that the page has been written to. */
uint32_t u1Dirty : 1;
/** Page size flag - always 1 for 2MB entries. */
uint32_t u1Size : 1;
/** Global flag. */
uint32_t u1Global : 1;
/** Available for use to system software. */
uint32_t u3Available : 3;
/** Reserved / If PAT enabled, bit 2 of the index. */
uint32_t u1PAT : 1;
/** Reserved. */
uint32_t u9Reserved : 9;
/** Physical Page number of the next level - Low part. Don't use! */
uint32_t u10PageNoLow : 10;
/** Physical Page number of the next level - High part. Don't use! */
uint32_t u20PageNoHigh : 20;
/** MBZ bits */
uint32_t u11Reserved : 11;
/** No Execute flag. */
uint32_t u1NoExecute : 1;
} X86PDE2MPAEBITS;
/** Pointer to a 2MB PAE page table entry. */
typedef X86PDE2MPAEBITS *PX86PDE2MPAEBITS;
/** Pointer to a 2MB PAE page table entry. */
typedef const X86PDE2MPAEBITS *PCX86PDE2MPAEBITS;
/** @} */
/**
* Page directory entry.
*/
typedef union X86PDE
{
/** Unsigned integer view. */
X86PGUINT u;
/** Normal view. */
X86PDEBITS n;
/** 4MB view (big). */
X86PDE4MBITS b;
/** 8 bit unsigned integer view. */
uint8_t au8[4];
/** 16 bit unsigned integer view. */
uint16_t au16[2];
/** 32 bit unsigned integer view. */
uint32_t au32[1];
} X86PDE;
/** Pointer to a page directory entry. */
typedef X86PDE *PX86PDE;
/** Pointer to a const page directory entry. */
typedef const X86PDE *PCX86PDE;
/**
* PAE page directory entry.
*/
typedef union X86PDEPAE
{
/** Unsigned integer view. */
X86PGPAEUINT u;
/** Normal view. */
X86PDEPAEBITS n;
/** 2MB page view (big). */
X86PDE2MPAEBITS b;
/** 8 bit unsigned integer view. */
uint8_t au8[8];
/** 16 bit unsigned integer view. */
uint16_t au16[4];
/** 32 bit unsigned integer view. */
uint32_t au32[2];
} X86PDEPAE;
/** Pointer to a page directory entry. */
typedef X86PDEPAE *PX86PDEPAE;
/** Pointer to a const page directory entry. */
typedef const X86PDEPAE *PCX86PDEPAE;
/**
* Page directory.
*/
typedef struct X86PD
{
/** PDE Array. */
X86PDE a[X86_PG_ENTRIES];
} X86PD;
/** Pointer to a page directory. */
typedef X86PD *PX86PD;
/** Pointer to a const page directory. */
typedef const X86PD *PCX86PD;
/** The page shift to get the PD index. */
#define X86_PD_SHIFT 22
/** The PD index mask (apply to a shifted page address). */
#define X86_PD_MASK 0x3ff
/**
* PAE page directory.
*/
typedef struct X86PDPAE
{
/** PDE Array. */
X86PDEPAE a[X86_PG_PAE_ENTRIES];
} X86PDPAE;
/** Pointer to a PAE page directory. */
typedef X86PDPAE *PX86PDPAE;
/** Pointer to a const PAE page directory. */
typedef const X86PDPAE *PCX86PDPAE;
/** The page shift to get the PAE PD index. */
#define X86_PD_PAE_SHIFT 21
/** The PAE PD index mask (apply to a shifted page address). */
#define X86_PD_PAE_MASK 0x1ff
/** @name Page Directory Pointer Table Entry (PAE)
* @{
*/
/** Bit 0 - P - Present bit. */
#define X86_PDPE_P RT_BIT(0)
/** Bit 1 - R/W - Read (clear) / Write (set) bit. Long Mode only. */
#define X86_PDPE_RW RT_BIT(1)
/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. Long Mode only. */
#define X86_PDPE_US RT_BIT(2)
/** Bit 3 - PWT - Page level write thru bit. */
#define X86_PDPE_PWT RT_BIT(3)
/** Bit 4 - PCD - Page level cache disable bit. */
#define X86_PDPE_PCD RT_BIT(4)
/** Bit 5 - A - Access bit. Long Mode only. */
#define X86_PDPE_A RT_BIT(5)
/** Bit 7 - PS - Page size (1GB). Long Mode only. */
#define X86_PDPE_LM_PS RT_BIT(7)
/** Bits 9-11 - - Available for use to system software. */
#define X86_PDPE_AVL_MASK (RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
/** Bits 12-51 - - PAE - Physical Page number of the next level. */
#define X86_PDPE_PG_MASK UINT64_C(0x000ffffffffff000)
/** Bits 63-52, 8-5, 2-1 - - PAE - MBZ bits (NX is long mode only). */
#define X86_PDPE_PAE_MBZ_MASK UINT64_C(0xfff00000000001e6)
/** Bits 63 - NX - LM - No execution flag. Long Mode only. */
#define X86_PDPE_LM_NX RT_BIT_64(63)
/** Bits 8, 7 - - LM - MBZ bits when NX is active. */
#define X86_PDPE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000180)
/** Bits 63, 8, 7 - - LM - MBZ bits when no NX. */
#define X86_PDPE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000180)
/** Bits 29-13 - - LM - MBZ bits for 1GB page entry when NX is active. */
#define X86_PDPE1G_LM_MBZ_MASK_NX UINT64_C(0x000000003fffe000)
/** Bits 63, 29-13 - - LM - MBZ bits for 1GB page entry when no NX. */
#define X86_PDPE1G_LM_MBZ_MASK_NO_NX UINT64_C(0x800000003fffe000)
/**
* Page directory pointer table entry.
*/
typedef struct X86PDPEBITS
{
/** Flags whether(=1) or not the page is present. */
uint32_t u1Present : 1;
/** Chunk of reserved bits. */
uint32_t u2Reserved : 2;
/** Write Thru flag. If PAT enabled, bit 0 of the index. */
uint32_t u1WriteThru : 1;
/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
uint32_t u1CacheDisable : 1;
/** Chunk of reserved bits. */
uint32_t u4Reserved : 4;
/** Available for use to system software. */
uint32_t u3Available : 3;
/** Physical Page number of the next level - Low Part. Don't use! */
uint32_t u20PageNoLow : 20;
/** Physical Page number of the next level - High Part. Don't use! */
uint32_t u20PageNoHigh : 20;
/** MBZ bits */
uint32_t u12Reserved : 12;
} X86PDPEBITS;
/** Pointer to a page directory pointer table entry. */
typedef X86PDPEBITS *PX86PTPEBITS;
/** Pointer to a const page directory pointer table entry. */
typedef const X86PDPEBITS *PCX86PTPEBITS;
/**
* Page directory pointer table entry. AMD64 version
*/
typedef struct X86PDPEAMD64BITS
{
/** Flags whether(=1) or not the page is present. */
uint32_t u1Present : 1;
/** Read(=0) / Write(=1) flag. */
uint32_t u1Write : 1;
/** User(=1) / Supervisor (=0) flag. */
uint32_t u1User : 1;
/** Write Thru flag. If PAT enabled, bit 0 of the index. */
uint32_t u1WriteThru : 1;
/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
uint32_t u1CacheDisable : 1;
/** Accessed flag.
* Indicates that the page have been read or written to. */
uint32_t u1Accessed : 1;
/** Chunk of reserved bits. */
uint32_t u3Reserved : 3;
/** Available for use to system software. */
uint32_t u3Available : 3;
/** Physical Page number of the next level - Low Part. Don't use! */
uint32_t u20PageNoLow : 20;
/** Physical Page number of the next level - High Part. Don't use! */
uint32_t u20PageNoHigh : 20;
/** MBZ bits */
uint32_t u11Reserved : 11;
/** No Execute flag. */
uint32_t u1NoExecute : 1;
} X86PDPEAMD64BITS;
/** Pointer to a page directory pointer table entry. */
typedef X86PDPEAMD64BITS *PX86PDPEAMD64BITS;
/** Pointer to a const page directory pointer table entry. */
typedef const X86PDPEAMD64BITS *PCX86PDPEAMD64BITS;
/**
* Page directory pointer table entry.
*/
typedef union X86PDPE
{
/** Unsigned integer view. */
X86PGPAEUINT u;
/** Normal view. */
X86PDPEBITS n;
/** AMD64 view. */
X86PDPEAMD64BITS lm;
/** 8 bit unsigned integer view. */
uint8_t au8[8];
/** 16 bit unsigned integer view. */
uint16_t au16[4];
/** 32 bit unsigned integer view. */
uint32_t au32[2];
} X86PDPE;
/** Pointer to a page directory pointer table entry. */
typedef X86PDPE *PX86PDPE;
/** Pointer to a const page directory pointer table entry. */
typedef const X86PDPE *PCX86PDPE;
/**
* Page directory pointer table.
*/
typedef struct X86PDPT
{
/** PDE Array. */
X86PDPE a[X86_PG_AMD64_PDPE_ENTRIES];
} X86PDPT;
/** Pointer to a page directory pointer table. */
typedef X86PDPT *PX86PDPT;
/** Pointer to a const page directory pointer table. */
typedef const X86PDPT *PCX86PDPT;
/** The page shift to get the PDPT index. */
#define X86_PDPT_SHIFT 30
/** The PDPT index mask (apply to a shifted page address). (32 bits PAE) */
#define X86_PDPT_MASK_PAE 0x3
/** The PDPT index mask (apply to a shifted page address). (64 bits PAE)*/
#define X86_PDPT_MASK_AMD64 0x1ff
/** @} */
/** @name Page Map Level-4 Entry (Long Mode PAE)
* @{
*/
/** Bit 0 - P - Present bit. */
#define X86_PML4E_P RT_BIT(0)
/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
#define X86_PML4E_RW RT_BIT(1)
/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
#define X86_PML4E_US RT_BIT(2)
/** Bit 3 - PWT - Page level write thru bit. */
#define X86_PML4E_PWT RT_BIT(3)
/** Bit 4 - PCD - Page level cache disable bit. */
#define X86_PML4E_PCD RT_BIT(4)
/** Bit 5 - A - Access bit. */
#define X86_PML4E_A RT_BIT(5)
/** Bits 9-11 - - Available for use to system software. */
#define X86_PML4E_AVL_MASK (RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
/** Bits 12-51 - - PAE - Physical Page number of the next level. */
#define X86_PML4E_PG_MASK UINT64_C(0x000ffffffffff000)
/** Bits 8, 7 - - MBZ bits when NX is active. */
#define X86_PML4E_MBZ_MASK_NX UINT64_C(0x0000000000000080)
/** Bits 63, 7 - - MBZ bits when no NX. */
#define X86_PML4E_MBZ_MASK_NO_NX UINT64_C(0x8000000000000080)
/** Bits 63 - NX - PAE - No execution flag. */
#define X86_PML4E_NX RT_BIT_64(63)
/**
* Page Map Level-4 Entry
*/
typedef struct X86PML4EBITS
{
/** Flags whether(=1) or not the page is present. */
uint32_t u1Present : 1;
/** Read(=0) / Write(=1) flag. */
uint32_t u1Write : 1;
/** User(=1) / Supervisor (=0) flag. */
uint32_t u1User : 1;
/** Write Thru flag. If PAT enabled, bit 0 of the index. */
uint32_t u1WriteThru : 1;
/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
uint32_t u1CacheDisable : 1;
/** Accessed flag.
* Indicates that the page have been read or written to. */
uint32_t u1Accessed : 1;
/** Chunk of reserved bits. */
uint32_t u3Reserved : 3;
/** Available for use to system software. */
uint32_t u3Available : 3;
/** Physical Page number of the next level - Low Part. Don't use! */
uint32_t u20PageNoLow : 20;
/** Physical Page number of the next level - High Part. Don't use! */
uint32_t u20PageNoHigh : 20;
/** MBZ bits */
uint32_t u11Reserved : 11;
/** No Execute flag. */
uint32_t u1NoExecute : 1;
} X86PML4EBITS;
/** Pointer to a page map level-4 entry. */
typedef X86PML4EBITS *PX86PML4EBITS;
/** Pointer to a const page map level-4 entry. */
typedef const X86PML4EBITS *PCX86PML4EBITS;
/**
* Page Map Level-4 Entry.
*/
typedef union X86PML4E
{
/** Unsigned integer view. */
X86PGPAEUINT u;
/** Normal view. */
X86PML4EBITS n;
/** 8 bit unsigned integer view. */
uint8_t au8[8];
/** 16 bit unsigned integer view. */
uint16_t au16[4];
/** 32 bit unsigned integer view. */
uint32_t au32[2];
} X86PML4E;
/** Pointer to a page map level-4 entry. */
typedef X86PML4E *PX86PML4E;
/** Pointer to a const page map level-4 entry. */
typedef const X86PML4E *PCX86PML4E;
/**
* Page Map Level-4.
*/
typedef struct X86PML4
{
/** PDE Array. */
X86PML4E a[X86_PG_PAE_ENTRIES];
} X86PML4;
/** Pointer to a page map level-4. */
typedef X86PML4 *PX86PML4;
/** Pointer to a const page map level-4. */
typedef const X86PML4 *PCX86PML4;
/** The page shift to get the PML4 index. */
#define X86_PML4_SHIFT 39
/** The PML4 index mask (apply to a shifted page address). */
#define X86_PML4_MASK 0x1ff
/** @} */
/** @} */
/**
* 80-bit MMX/FPU register type.
*/
typedef struct X86FPUMMX
{
uint8_t reg[10];
} X86FPUMMX;
/** Pointer to a 80-bit MMX/FPU register type. */
typedef X86FPUMMX *PX86FPUMMX;
/** Pointer to a const 80-bit MMX/FPU register type. */
typedef const X86FPUMMX *PCX86FPUMMX;
/**
* 32-bit FPU state (aka FSAVE/FRSTOR Memory Region).
* @todo verify this...
*/
#pragma pack(1)
typedef struct X86FPUSTATE
{
/** 0x00 - Control word. */
uint16_t FCW;
/** 0x02 - Alignment word */
uint16_t Dummy1;
/** 0x04 - Status word. */
uint16_t FSW;
/** 0x06 - Alignment word */
uint16_t Dummy2;
/** 0x08 - Tag word */
uint16_t FTW;
/** 0x0a - Alignment word */
uint16_t Dummy3;
/** 0x0c - Instruction pointer. */
uint32_t FPUIP;
/** 0x10 - Code selector. */
uint16_t CS;
/** 0x12 - Opcode. */
uint16_t FOP;
/** 0x14 - FOO. */
uint32_t FPUOO;
/** 0x18 - FOS. */
uint32_t FPUOS;
/** 0x1c */
union
{
/** MMX view. */
uint64_t mmx;
/** FPU view - todo. */
X86FPUMMX fpu;
/** Extended precision floating point view. */
RTFLOAT80U r80;
/** Extended precision floating point view v2. */
RTFLOAT80U2 r80Ex;
/** 8-bit view. */
uint8_t au8[16];
/** 16-bit view. */
uint16_t au16[8];
/** 32-bit view. */
uint32_t au32[4];
/** 64-bit view. */
uint64_t au64[2];
/** 128-bit view. (yeah, very helpful) */
uint128_t au128[1];
} regs[8];
} X86FPUSTATE;
#pragma pack()
/** Pointer to a FPU state. */
typedef X86FPUSTATE *PX86FPUSTATE;
/** Pointer to a const FPU state. */
typedef const X86FPUSTATE *PCX86FPUSTATE;
/**
* FPU Extended state (aka FXSAVE/FXRSTORE Memory Region).
*/
#pragma pack(1)
typedef struct X86FXSTATE
{
/** 0x00 - Control word. */
uint16_t FCW;
/** 0x02 - Status word. */
uint16_t FSW;
/** 0x04 - Tag word. (The upper byte is always zero.) */
uint16_t FTW;
/** 0x06 - Opcode. */
uint16_t FOP;
/** 0x08 - Instruction pointer. */
uint32_t FPUIP;
/** 0x0c - Code selector. */
uint16_t CS;
uint16_t Rsrvd1;
/** 0x10 - Data pointer. */
uint32_t FPUDP;
/** 0x14 - Data segment */
uint16_t DS;
/** 0x16 */
uint16_t Rsrvd2;
/** 0x18 */
uint32_t MXCSR;
/** 0x1c */
uint32_t MXCSR_MASK;
/** 0x20 */
union
{
/** MMX view. */
uint64_t mmx;
/** FPU view - todo. */
X86FPUMMX fpu;
/** Extended precision floating point view. */
RTFLOAT80U r80;
/** Extended precision floating point view v2 */
RTFLOAT80U2 r80Ex;
/** 8-bit view. */
uint8_t au8[16];
/** 16-bit view. */
uint16_t au16[8];
/** 32-bit view. */
uint32_t au32[4];
/** 64-bit view. */
uint64_t au64[2];
/** 128-bit view. (yeah, very helpful) */
uint128_t au128[1];
} aRegs[8];
/* - offset 160 - */
union
{
/** XMM Register view *. */
uint128_t xmm;
/** 8-bit view. */
uint8_t au8[16];
/** 16-bit view. */
uint16_t au16[8];
/** 32-bit view. */
uint32_t au32[4];
/** 64-bit view. */
uint64_t au64[2];
/** 128-bit view. (yeah, very helpful) */
uint128_t au128[1];
} aXMM[16]; /* 8 registers in 32 bits mode; 16 in long mode */
/* - offset 416 - */
uint32_t au32RsrvdRest[(512 - 416) / sizeof(uint32_t)];
} X86FXSTATE;
#pragma pack()
/** Pointer to a FPU Extended state. */
typedef X86FXSTATE *PX86FXSTATE;
/** Pointer to a const FPU Extended state. */
typedef const X86FXSTATE *PCX86FXSTATE;
/** @name FPU status word flags.
* @{ */
/** Exception Flag: Invalid operation. */
#define X86_FSW_IE RT_BIT(0)
/** Exception Flag: Denormalized operand. */
#define X86_FSW_DE RT_BIT(1)
/** Exception Flag: Zero divide. */
#define X86_FSW_ZE RT_BIT(2)
/** Exception Flag: Overflow. */
#define X86_FSW_OE RT_BIT(3)
/** Exception Flag: Underflow. */
#define X86_FSW_UE RT_BIT(4)
/** Exception Flag: Precision. */
#define X86_FSW_PE RT_BIT(5)
/** Stack fault. */
#define X86_FSW_SF RT_BIT(6)
/** Error summary status. */
#define X86_FSW_ES RT_BIT(7)
/** Mask of exceptions flags, excluding the summary bit. */
#define X86_FSW_XCPT_MASK UINT16_C(0x007f)
/** Mask of exceptions flags, including the summary bit. */
#define X86_FSW_XCPT_ES_MASK UINT16_C(0x00ff)
/** Condition code 0. */
#define X86_FSW_C0 RT_BIT(8)
/** Condition code 1. */
#define X86_FSW_C1 RT_BIT(9)
/** Condition code 2. */
#define X86_FSW_C2 RT_BIT(10)
/** Top of the stack mask. */
#define X86_FSW_TOP_MASK UINT16_C(0x3800)
/** TOP shift value. */
#define X86_FSW_TOP_SHIFT 11
/** Mask for getting TOP value after shifting it right. */
#define X86_FSW_TOP_SMASK UINT16_C(0x0007)
/** Get the TOP value. */
#define X86_FSW_TOP_GET(a_uFsw) (((a_uFsw) >> X86_FSW_TOP_SHIFT) & X86_FSW_TOP_SMASK)
/** Condition code 3. */
#define X86_FSW_C3 RT_BIT(14)
/** Mask of exceptions flags, including the summary bit. */
#define X86_FSW_C_MASK UINT16_C(0x4700)
/** FPU busy. */
#define X86_FSW_B RT_BIT(15)
/** @} */
/** @name FPU control word flags.
* @{ */
/** Exception Mask: Invalid operation. */
#define X86_FCW_IM RT_BIT(0)
/** Exception Mask: Denormalized operand. */
#define X86_FCW_DM RT_BIT(1)
/** Exception Mask: Zero divide. */
#define X86_FCW_ZM RT_BIT(2)
/** Exception Mask: Overflow. */
#define X86_FCW_OM RT_BIT(3)
/** Exception Mask: Underflow. */
#define X86_FCW_UM RT_BIT(4)
/** Exception Mask: Precision. */
#define X86_FCW_PM RT_BIT(5)
/** Mask all exceptions, the value typically loaded (by for instance fninit).
* @remarks This includes reserved bit 6. */
#define X86_FCW_MASK_ALL UINT16_C(0x007f)
/** Mask all exceptions. Same as X86_FSW_XCPT_MASK. */
#define X86_FCW_XCPT_MASK UINT16_C(0x003f)
/** Precision control mask. */
#define X86_FCW_PC_MASK UINT16_C(0x0300)
/** Precision control: 24-bit. */
#define X86_FCW_PC_24 UINT16_C(0x0000)
/** Precision control: Reserved. */
#define X86_FCW_PC_RSVD UINT16_C(0x0100)
/** Precision control: 53-bit. */
#define X86_FCW_PC_53 UINT16_C(0x0200)
/** Precision control: 64-bit. */
#define X86_FCW_PC_64 UINT16_C(0x0300)
/** Rounding control mask. */
#define X86_FCW_RC_MASK UINT16_C(0x0c00)
/** Rounding control: To nearest. */
#define X86_FCW_RC_NEAREST UINT16_C(0x0000)
/** Rounding control: Down. */
#define X86_FCW_RC_DOWN UINT16_C(0x0400)
/** Rounding control: Up. */
#define X86_FCW_RC_UP UINT16_C(0x0800)
/** Rounding control: Towards zero. */
#define X86_FCW_RC_ZERO UINT16_C(0x0c00)
/** Bits which should be zero, apparently. */
#define X86_FCW_ZERO_MASK UINT16_C(0xf080)
/** @} */
/** @name SSE MXCSR
* @{ */
/** Exception Flag: Invalid operation. */
#define X86_MSXCR_IE RT_BIT(0)
/** Exception Flag: Denormalized operand. */
#define X86_MSXCR_DE RT_BIT(1)
/** Exception Flag: Zero divide. */
#define X86_MSXCR_ZE RT_BIT(2)
/** Exception Flag: Overflow. */
#define X86_MSXCR_OE RT_BIT(3)
/** Exception Flag: Underflow. */
#define X86_MSXCR_UE RT_BIT(4)
/** Exception Flag: Precision. */
#define X86_MSXCR_PE RT_BIT(5)
/** Denormals are zero. */
#define X86_MSXCR_DAZ RT_BIT(6)
/** Exception Mask: Invalid operation. */
#define X86_MSXCR_IM RT_BIT(7)
/** Exception Mask: Denormalized operand. */
#define X86_MSXCR_DM RT_BIT(8)
/** Exception Mask: Zero divide. */
#define X86_MSXCR_ZM RT_BIT(9)
/** Exception Mask: Overflow. */
#define X86_MSXCR_OM RT_BIT(10)
/** Exception Mask: Underflow. */
#define X86_MSXCR_UM RT_BIT(11)
/** Exception Mask: Precision. */
#define X86_MSXCR_PM RT_BIT(12)
/** Rounding control mask. */
#define X86_MSXCR_RC_MASK UINT16_C(0x6000)
/** Rounding control: To nearest. */
#define X86_MSXCR_RC_NEAREST UINT16_C(0x0000)
/** Rounding control: Down. */
#define X86_MSXCR_RC_DOWN UINT16_C(0x2000)
/** Rounding control: Up. */
#define X86_MSXCR_RC_UP UINT16_C(0x4000)
/** Rounding control: Towards zero. */
#define X86_MSXCR_RC_ZERO UINT16_C(0x6000)
/** Flush-to-zero for masked underflow. */
#define X86_MSXCR_FZ RT_BIT(15)
/** Misaligned Exception Mask. */
#define X86_MSXCR_MM RT_BIT(16)
/** @} */
/** @name Selector Descriptor
* @{
*/
#ifndef VBOX_FOR_DTRACE_LIB
/**
* Descriptor attributes (as seen by VT-x).
*/
typedef struct X86DESCATTRBITS
{
/** 00 - Segment Type. */
unsigned u4Type : 4;
/** 04 - Descriptor Type. System(=0) or code/data selector */
unsigned u1DescType : 1;
/** 05 - Descriptor Privelege level. */
unsigned u2Dpl : 2;
/** 07 - Flags selector present(=1) or not. */
unsigned u1Present : 1;
/** 08 - Segment limit 16-19. */
unsigned u4LimitHigh : 4;
/** 0c - Available for system software. */
unsigned u1Available : 1;
/** 0d - 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
unsigned u1Long : 1;
/** 0e - This flags meaning depends on the segment type. Try make sense out
* of the intel manual yourself. */
unsigned u1DefBig : 1;
/** 0f - Granularity of the limit. If set 4KB granularity is used, if
* clear byte. */
unsigned u1Granularity : 1;
/** 10 - "Unusable" selector, special Intel (VT-x only?) bit. */
unsigned u1Unusable : 1;
} X86DESCATTRBITS;
#endif /* !VBOX_FOR_DTRACE_LIB */
/** @name X86DESCATTR masks
* @{ */
#define X86DESCATTR_TYPE UINT32_C(0x0000000f)
#define X86DESCATTR_DT UINT32_C(0x00000010)
#define X86DESCATTR_DPL UINT32_C(0x00000060)
#define X86DESCATTR_DPL_SHIFT 5 /**< Shift count for the DPL value. */
#define X86DESCATTR_P UINT32_C(0x00000080)
#define X86DESCATTR_LIMIT_HIGH UINT32_C(0x00000f00)
#define X86DESCATTR_AVL UINT32_C(0x00001000)
#define X86DESCATTR_L UINT32_C(0x00002000)
#define X86DESCATTR_D UINT32_C(0x00004000)
#define X86DESCATTR_G UINT32_C(0x00008000)
#define X86DESCATTR_UNUSABLE UINT32_C(0x00010000)
/** @} */
#pragma pack(1)
typedef union X86DESCATTR
{
/** Unsigned integer view. */
uint32_t u;
#ifndef VBOX_FOR_DTRACE_LIB
/** Normal view. */
X86DESCATTRBITS n;
#endif
} X86DESCATTR;
#pragma pack()
/** Pointer to descriptor attributes. */
typedef X86DESCATTR *PX86DESCATTR;
/** Pointer to const descriptor attributes. */
typedef const X86DESCATTR *PCX86DESCATTR;
#ifndef VBOX_FOR_DTRACE_LIB
/**
* Generic descriptor table entry
*/
#pragma pack(1)
typedef struct X86DESCGENERIC
{
/** 00 - Limit - Low word. */
unsigned u16LimitLow : 16;
/** 10 - Base address - lowe word.
* Don't try set this to 24 because MSC is doing stupid things then. */
unsigned u16BaseLow : 16;
/** 20 - Base address - first 8 bits of high word. */
unsigned u8BaseHigh1 : 8;
/** 28 - Segment Type. */
unsigned u4Type : 4;
/** 2c - Descriptor Type. System(=0) or code/data selector */
unsigned u1DescType : 1;
/** 2d - Descriptor Privelege level. */
unsigned u2Dpl : 2;
/** 2f - Flags selector present(=1) or not. */
unsigned u1Present : 1;
/** 30 - Segment limit 16-19. */
unsigned u4LimitHigh : 4;
/** 34 - Available for system software. */
unsigned u1Available : 1;
/** 35 - 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
unsigned u1Long : 1;
/** 36 - This flags meaning depends on the segment type. Try make sense out
* of the intel manual yourself. */
unsigned u1DefBig : 1;
/** 37 - Granularity of the limit. If set 4KB granularity is used, if
* clear byte. */
unsigned u1Granularity : 1;
/** 38 - Base address - highest 8 bits. */
unsigned u8BaseHigh2 : 8;
} X86DESCGENERIC;
#pragma pack()
/** Pointer to a generic descriptor entry. */
typedef X86DESCGENERIC *PX86DESCGENERIC;
/** Pointer to a const generic descriptor entry. */
typedef const X86DESCGENERIC *PCX86DESCGENERIC;
/** @name Bit offsets of X86DESCGENERIC members.
* @{*/
#define X86DESCGENERIC_BIT_OFF_LIMIT_LOW (0) /**< Bit offset of X86DESCGENERIC::u16LimitLow. */
#define X86DESCGENERIC_BIT_OFF_BASE_LOW (16) /**< Bit offset of X86DESCGENERIC::u16BaseLow. */
#define X86DESCGENERIC_BIT_OFF_BASE_HIGH1 (32) /**< Bit offset of X86DESCGENERIC::u8BaseHigh1. */
#define X86DESCGENERIC_BIT_OFF_TYPE (40) /**< Bit offset of X86DESCGENERIC::u4Type. */
#define X86DESCGENERIC_BIT_OFF_DESC_TYPE (44) /**< Bit offset of X86DESCGENERIC::u1DescType. */
#define X86DESCGENERIC_BIT_OFF_DPL (45) /**< Bit offset of X86DESCGENERIC::u2Dpl. */
#define X86DESCGENERIC_BIT_OFF_PRESENT (47) /**< Bit offset of X86DESCGENERIC::uu1Present. */
#define X86DESCGENERIC_BIT_OFF_LIMIT_HIGH (48) /**< Bit offset of X86DESCGENERIC::u4LimitHigh. */
#define X86DESCGENERIC_BIT_OFF_AVAILABLE (52) /**< Bit offset of X86DESCGENERIC::u1Available. */
#define X86DESCGENERIC_BIT_OFF_LONG (53) /**< Bit offset of X86DESCGENERIC::u1Long. */
#define X86DESCGENERIC_BIT_OFF_DEF_BIG (54) /**< Bit offset of X86DESCGENERIC::u1DefBig. */
#define X86DESCGENERIC_BIT_OFF_GRANULARITY (55) /**< Bit offset of X86DESCGENERIC::u1Granularity. */
#define X86DESCGENERIC_BIT_OFF_BASE_HIGH2 (56) /**< Bit offset of X86DESCGENERIC::u8BaseHigh2. */
/** @} */
/**
* Call-, Interrupt-, Trap- or Task-gate descriptor (legacy).
*/
typedef struct X86DESCGATE
{
/** 00 - Target code segment offset - Low word.
* Ignored if task-gate. */
unsigned u16OffsetLow : 16;
/** 10 - Target code segment selector for call-, interrupt- and trap-gates,
* TSS selector if task-gate. */
unsigned u16Sel : 16;
/** 20 - Number of parameters for a call-gate.
* Ignored if interrupt-, trap- or task-gate. */
unsigned u4ParmCount : 4;
/** 24 - Reserved / ignored. */
unsigned u4Reserved : 4;
/** 28 - Segment Type. */
unsigned u4Type : 4;
/** 2c - Descriptor Type (0 = system). */
unsigned u1DescType : 1;
/** 2d - Descriptor Privelege level. */
unsigned u2Dpl : 2;
/** 2f - Flags selector present(=1) or not. */
unsigned u1Present : 1;
/** 30 - Target code segment offset - High word.
* Ignored if task-gate. */
unsigned u16OffsetHigh : 16;
} X86DESCGATE;
/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
typedef X86DESCGATE *PX86DESCGATE;
/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
typedef const X86DESCGATE *PCX86DESCGATE;
#endif /* VBOX_FOR_DTRACE_LIB */
/**
* Descriptor table entry.
*/
#pragma pack(1)
typedef union X86DESC
{
#ifndef VBOX_FOR_DTRACE_LIB
/** Generic descriptor view. */
X86DESCGENERIC Gen;
/** Gate descriptor view. */
X86DESCGATE Gate;
#endif
/** 8 bit unsigned integer view. */
uint8_t au8[8];
/** 16 bit unsigned integer view. */
uint16_t au16[4];
/** 32 bit unsigned integer view. */
uint32_t au32[2];
/** 64 bit unsigned integer view. */
uint64_t au64[1];
/** Unsigned integer view. */
uint64_t u;
} X86DESC;
#ifndef VBOX_FOR_DTRACE_LIB
AssertCompileSize(X86DESC, 8);
#endif
#pragma pack()
/** Pointer to descriptor table entry. */
typedef X86DESC *PX86DESC;
/** Pointer to const descriptor table entry. */
typedef const X86DESC *PCX86DESC;
/** @def X86DESC_BASE
* Return the base address of a descriptor.
*/
#define X86DESC_BASE(a_pDesc) /*ASM-NOINC*/ \
( ((uint32_t)((a_pDesc)->Gen.u8BaseHigh2) << 24) \
| ( (a_pDesc)->Gen.u8BaseHigh1 << 16) \
| ( (a_pDesc)->Gen.u16BaseLow ) )
/** @def X86DESC_LIMIT
* Return the limit of a descriptor.
*/
#define X86DESC_LIMIT(a_pDesc) /*ASM-NOINC*/ \
( ((uint32_t)((a_pDesc)->Gen.u4LimitHigh) << 16) \
| ( (a_pDesc)->Gen.u16LimitLow ) )
/** @def X86DESC_LIMIT_G
* Return the limit of a descriptor with the granularity bit taken into account.
* @returns Selector limit (uint32_t).
* @param a_pDesc Pointer to the descriptor.
*/
#define X86DESC_LIMIT_G(a_pDesc) /*ASM-NOINC*/ \
( (a_pDesc)->Gen.u1Granularity \
? ( ( ((uint32_t)(a_pDesc)->Gen.u4LimitHigh << 16) | (a_pDesc)->Gen.u16LimitLow ) << 12 ) | UINT32_C(0xfff) \
: ((uint32_t)(a_pDesc)->Gen.u4LimitHigh << 16) | (a_pDesc)->Gen.u16LimitLow \
)
/** @def X86DESC_GET_HID_ATTR
* Get the descriptor attributes for the hidden register.
*/
#define X86DESC_GET_HID_ATTR(a_pDesc) /*ASM-NOINC*/ \
( ((a_pDesc)->u >> (16+16+8)) & UINT32_C(0xf0ff) ) /** @todo do we have a define for 0xf0ff? */
#ifndef VBOX_FOR_DTRACE_LIB
/**
* 64 bits generic descriptor table entry
* Note: most of these bits have no meaning in long mode.
*/
#pragma pack(1)
typedef struct X86DESC64GENERIC
{
/** Limit - Low word - *IGNORED*. */
unsigned u16LimitLow : 16;
/** Base address - low word. - *IGNORED*
* Don't try set this to 24 because MSC is doing stupid things then. */
unsigned u16BaseLow : 16;
/** Base address - first 8 bits of high word. - *IGNORED* */
unsigned u8BaseHigh1 : 8;
/** Segment Type. */
unsigned u4Type : 4;
/** Descriptor Type. System(=0) or code/data selector */
unsigned u1DescType : 1;
/** Descriptor Privelege level. */
unsigned u2Dpl : 2;
/** Flags selector present(=1) or not. */
unsigned u1Present : 1;
/** Segment limit 16-19. - *IGNORED* */
unsigned u4LimitHigh : 4;
/** Available for system software. - *IGNORED* */
unsigned u1Available : 1;
/** Long mode flag. */
unsigned u1Long : 1;
/** This flags meaning depends on the segment type. Try make sense out
* of the intel manual yourself. */
unsigned u1DefBig : 1;
/** Granularity of the limit. If set 4KB granularity is used, if
* clear byte. - *IGNORED* */
unsigned u1Granularity : 1;
/** Base address - highest 8 bits. - *IGNORED* */
unsigned u8BaseHigh2 : 8;
/** Base address - bits 63-32. */
unsigned u32BaseHigh3 : 32;
unsigned u8Reserved : 8;
unsigned u5Zeros : 5;
unsigned u19Reserved : 19;
} X86DESC64GENERIC;
#pragma pack()
/** Pointer to a generic descriptor entry. */
typedef X86DESC64GENERIC *PX86DESC64GENERIC;
/** Pointer to a const generic descriptor entry. */
typedef const X86DESC64GENERIC *PCX86DESC64GENERIC;
/**
* System descriptor table entry (64 bits)
*
* @remarks This is, save a couple of comments, identical to X86DESC64GENERIC...
*/
#pragma pack(1)
typedef struct X86DESC64SYSTEM
{
/** Limit - Low word. */
unsigned u16LimitLow : 16;
/** Base address - lowe word.
* Don't try set this to 24 because MSC is doing stupid things then. */
unsigned u16BaseLow : 16;
/** Base address - first 8 bits of high word. */
unsigned u8BaseHigh1 : 8;
/** Segment Type. */
unsigned u4Type : 4;
/** Descriptor Type. System(=0) or code/data selector */
unsigned u1DescType : 1;
/** Descriptor Privelege level. */
unsigned u2Dpl : 2;
/** Flags selector present(=1) or not. */
unsigned u1Present : 1;
/** Segment limit 16-19. */
unsigned u4LimitHigh : 4;
/** Available for system software. */
unsigned u1Available : 1;
/** Reserved - 0. */
unsigned u1Reserved : 1;
/** This flags meaning depends on the segment type. Try make sense out
* of the intel manual yourself. */
unsigned u1DefBig : 1;
/** Granularity of the limit. If set 4KB granularity is used, if
* clear byte. */
unsigned u1Granularity : 1;
/** Base address - bits 31-24. */
unsigned u8BaseHigh2 : 8;
/** Base address - bits 63-32. */
unsigned u32BaseHigh3 : 32;
unsigned u8Reserved : 8;
unsigned u5Zeros : 5;
unsigned u19Reserved : 19;
} X86DESC64SYSTEM;
#pragma pack()
/** Pointer to a system descriptor entry. */
typedef X86DESC64SYSTEM *PX86DESC64SYSTEM;
/** Pointer to a const system descriptor entry. */
typedef const X86DESC64SYSTEM *PCX86DESC64SYSTEM;
/**
* Call-, Interrupt-, Trap- or Task-gate descriptor (64-bit).
*/
typedef struct X86DESC64GATE
{
/** Target code segment offset - Low word. */
unsigned u16OffsetLow : 16;
/** Target code segment selector. */
unsigned u16Sel : 16;
/** Interrupt stack table for interrupt- and trap-gates.
* Ignored by call-gates. */
unsigned u3IST : 3;
/** Reserved / ignored. */
unsigned u5Reserved : 5;
/** Segment Type. */
unsigned u4Type : 4;
/** Descriptor Type (0 = system). */
unsigned u1DescType : 1;
/** Descriptor Privelege level. */
unsigned u2Dpl : 2;
/** Flags selector present(=1) or not. */
unsigned u1Present : 1;
/** Target code segment offset - High word.
* Ignored if task-gate. */
unsigned u16OffsetHigh : 16;
/** Target code segment offset - Top dword.
* Ignored if task-gate. */
unsigned u32OffsetTop : 32;
/** Reserved / ignored / must be zero.
* For call-gates bits 8 thru 12 must be zero, the other gates ignores this. */
unsigned u32Reserved : 32;
} X86DESC64GATE;
AssertCompileSize(X86DESC64GATE, 16);
/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
typedef X86DESC64GATE *PX86DESC64GATE;
/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
typedef const X86DESC64GATE *PCX86DESC64GATE;
#endif /* VBOX_FOR_DTRACE_LIB */
/**
* Descriptor table entry.
*/
#pragma pack(1)
typedef union X86DESC64
{
#ifndef VBOX_FOR_DTRACE_LIB
/** Generic descriptor view. */
X86DESC64GENERIC Gen;
/** System descriptor view. */
X86DESC64SYSTEM System;
/** Gate descriptor view. */
X86DESC64GATE Gate;
#endif
/** 8 bit unsigned integer view. */
uint8_t au8[16];
/** 16 bit unsigned integer view. */
uint16_t au16[8];
/** 32 bit unsigned integer view. */
uint32_t au32[4];
/** 64 bit unsigned integer view. */
uint64_t au64[2];
} X86DESC64;
#ifndef VBOX_FOR_DTRACE_LIB
AssertCompileSize(X86DESC64, 16);
#endif
#pragma pack()
/** Pointer to descriptor table entry. */
typedef X86DESC64 *PX86DESC64;
/** Pointer to const descriptor table entry. */
typedef const X86DESC64 *PCX86DESC64;
/** @def X86DESC64_BASE
* Return the base of a 64-bit descriptor.
*/
#define X86DESC64_BASE(a_pDesc) /*ASM-NOINC*/ \
( ((uint64_t)((a_pDesc)->Gen.u32BaseHigh3) << 32) \
| ((uint32_t)((a_pDesc)->Gen.u8BaseHigh2) << 24) \
| ( (a_pDesc)->Gen.u8BaseHigh1 << 16) \
| ( (a_pDesc)->Gen.u16BaseLow ) )
/** @name Host system descriptor table entry - Use with care!
* @{ */
/** Host system descriptor table entry. */
#if HC_ARCH_BITS == 64
typedef X86DESC64 X86DESCHC;
#else
typedef X86DESC X86DESCHC;
#endif
/** Pointer to a host system descriptor table entry. */
#if HC_ARCH_BITS == 64
typedef PX86DESC64 PX86DESCHC;
#else
typedef PX86DESC PX86DESCHC;
#endif
/** Pointer to a const host system descriptor table entry. */
#if HC_ARCH_BITS == 64
typedef PCX86DESC64 PCX86DESCHC;
#else
typedef PCX86DESC PCX86DESCHC;
#endif
/** @} */
/** @name Selector Descriptor Types.
* @{
*/
/** @name Non-System Selector Types.
* @{ */
/** Code(=set)/Data(=clear) bit. */
#define X86_SEL_TYPE_CODE 8
/** Memory(=set)/System(=clear) bit. */
#define X86_SEL_TYPE_MEMORY RT_BIT(4)
/** Accessed bit. */
#define X86_SEL_TYPE_ACCESSED 1
/** Expand down bit (for data selectors only). */
#define X86_SEL_TYPE_DOWN 4
/** Conforming bit (for code selectors only). */
#define X86_SEL_TYPE_CONF 4
/** Write bit (for data selectors only). */
#define X86_SEL_TYPE_WRITE 2
/** Read bit (for code selectors only). */
#define X86_SEL_TYPE_READ 2
/** The bit number of the code segment read bit (relative to u4Type). */
#define X86_SEL_TYPE_READ_BIT 1
/** Read only selector type. */
#define X86_SEL_TYPE_RO 0
/** Accessed read only selector type. */
#define X86_SEL_TYPE_RO_ACC (0 | X86_SEL_TYPE_ACCESSED)
/** Read write selector type. */
#define X86_SEL_TYPE_RW 2
/** Accessed read write selector type. */
#define X86_SEL_TYPE_RW_ACC (2 | X86_SEL_TYPE_ACCESSED)
/** Expand down read only selector type. */
#define X86_SEL_TYPE_RO_DOWN 4
/** Accessed expand down read only selector type. */
#define X86_SEL_TYPE_RO_DOWN_ACC (4 | X86_SEL_TYPE_ACCESSED)
/** Expand down read write selector type. */
#define X86_SEL_TYPE_RW_DOWN 6
/** Accessed expand down read write selector type. */
#define X86_SEL_TYPE_RW_DOWN_ACC (6 | X86_SEL_TYPE_ACCESSED)
/** Execute only selector type. */
#define X86_SEL_TYPE_EO (0 | X86_SEL_TYPE_CODE)
/** Accessed execute only selector type. */
#define X86_SEL_TYPE_EO_ACC (0 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
/** Execute and read selector type. */
#define X86_SEL_TYPE_ER (2 | X86_SEL_TYPE_CODE)
/** Accessed execute and read selector type. */
#define X86_SEL_TYPE_ER_ACC (2 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
/** Conforming execute only selector type. */
#define X86_SEL_TYPE_EO_CONF (4 | X86_SEL_TYPE_CODE)
/** Accessed Conforming execute only selector type. */
#define X86_SEL_TYPE_EO_CONF_ACC (4 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
/** Conforming execute and write selector type. */
#define X86_SEL_TYPE_ER_CONF (6 | X86_SEL_TYPE_CODE)
/** Accessed Conforming execute and write selector type. */
#define X86_SEL_TYPE_ER_CONF_ACC (6 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
/** @} */
/** @name System Selector Types.
* @{ */
/** The TSS busy bit mask. */
#define X86_SEL_TYPE_SYS_TSS_BUSY_MASK 2
/** Undefined system selector type. */
#define X86_SEL_TYPE_SYS_UNDEFINED 0
/** 286 TSS selector. */
#define X86_SEL_TYPE_SYS_286_TSS_AVAIL 1
/** LDT selector. */
#define X86_SEL_TYPE_SYS_LDT 2
/** 286 TSS selector - Busy. */
#define X86_SEL_TYPE_SYS_286_TSS_BUSY 3
/** 286 Callgate selector. */
#define X86_SEL_TYPE_SYS_286_CALL_GATE 4
/** Taskgate selector. */
#define X86_SEL_TYPE_SYS_TASK_GATE 5
/** 286 Interrupt gate selector. */
#define X86_SEL_TYPE_SYS_286_INT_GATE 6
/** 286 Trapgate selector. */
#define X86_SEL_TYPE_SYS_286_TRAP_GATE 7
/** Undefined system selector. */
#define X86_SEL_TYPE_SYS_UNDEFINED2 8
/** 386 TSS selector. */
#define X86_SEL_TYPE_SYS_386_TSS_AVAIL 9
/** Undefined system selector. */
#define X86_SEL_TYPE_SYS_UNDEFINED3 0xA
/** 386 TSS selector - Busy. */
#define X86_SEL_TYPE_SYS_386_TSS_BUSY 0xB
/** 386 Callgate selector. */
#define X86_SEL_TYPE_SYS_386_CALL_GATE 0xC
/** Undefined system selector. */
#define X86_SEL_TYPE_SYS_UNDEFINED4 0xD
/** 386 Interruptgate selector. */
#define X86_SEL_TYPE_SYS_386_INT_GATE 0xE
/** 386 Trapgate selector. */
#define X86_SEL_TYPE_SYS_386_TRAP_GATE 0xF
/** @} */
/** @name AMD64 System Selector Types.
* @{ */
/** LDT selector. */
#define AMD64_SEL_TYPE_SYS_LDT 2
/** TSS selector - Busy. */
#define AMD64_SEL_TYPE_SYS_TSS_AVAIL 9
/** TSS selector - Busy. */
#define AMD64_SEL_TYPE_SYS_TSS_BUSY 0xB
/** Callgate selector. */
#define AMD64_SEL_TYPE_SYS_CALL_GATE 0xC
/** Interruptgate selector. */
#define AMD64_SEL_TYPE_SYS_INT_GATE 0xE
/** Trapgate selector. */
#define AMD64_SEL_TYPE_SYS_TRAP_GATE 0xF
/** @} */
/** @} */
/** @name Descriptor Table Entry Flag Masks.
* These are for the 2nd 32-bit word of a descriptor.
* @{ */
/** Bits 8-11 - TYPE - Descriptor type mask. */
#define X86_DESC_TYPE_MASK (RT_BIT(8) | RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
/** Bit 12 - S - System (=0) or Code/Data (=1). */
#define X86_DESC_S RT_BIT(12)
/** Bits 13-14 - DPL - Descriptor Privilege Level. */
#define X86_DESC_DPL (RT_BIT(13) | RT_BIT(14))
/** Bit 15 - P - Present. */
#define X86_DESC_P RT_BIT(15)
/** Bit 20 - AVL - Available for system software. */
#define X86_DESC_AVL RT_BIT(20)
/** Bit 22 - DB - Default operation size. 0 = 16 bit, 1 = 32 bit. */
#define X86_DESC_DB RT_BIT(22)
/** Bit 23 - G - Granularity of the limit. If set 4KB granularity is
* used, if clear byte. */
#define X86_DESC_G RT_BIT(23)
/** @} */
/** @} */
/** @name Task Segments.
* @{
*/
/**
* 16-bit Task Segment (TSS).
*/
#pragma pack(1)
typedef struct X86TSS16
{
/** Back link to previous task. (static) */
RTSEL selPrev;
/** Ring-0 stack pointer. (static) */
uint16_t sp0;
/** Ring-0 stack segment. (static) */
RTSEL ss0;
/** Ring-1 stack pointer. (static) */
uint16_t sp1;
/** Ring-1 stack segment. (static) */
RTSEL ss1;
/** Ring-2 stack pointer. (static) */
uint16_t sp2;
/** Ring-2 stack segment. (static) */
RTSEL ss2;
/** IP before task switch. */
uint16_t ip;
/** FLAGS before task switch. */
uint16_t flags;
/** AX before task switch. */
uint16_t ax;
/** CX before task switch. */
uint16_t cx;
/** DX before task switch. */
uint16_t dx;
/** BX before task switch. */
uint16_t bx;
/** SP before task switch. */
uint16_t sp;
/** BP before task switch. */
uint16_t bp;
/** SI before task switch. */
uint16_t si;
/** DI before task switch. */
uint16_t di;
/** ES before task switch. */
RTSEL es;
/** CS before task switch. */
RTSEL cs;
/** SS before task switch. */
RTSEL ss;
/** DS before task switch. */
RTSEL ds;
/** LDTR before task switch. */
RTSEL selLdt;
} X86TSS16;
#ifndef VBOX_FOR_DTRACE_LIB
AssertCompileSize(X86TSS16, 44);
#endif
#pragma pack()
/** Pointer to a 16-bit task segment. */
typedef X86TSS16 *PX86TSS16;
/** Pointer to a const 16-bit task segment. */
typedef const X86TSS16 *PCX86TSS16;
/**
* 32-bit Task Segment (TSS).
*/
#pragma pack(1)
typedef struct X86TSS32
{
/** Back link to previous task. (static) */
RTSEL selPrev;
uint16_t padding1;
/** Ring-0 stack pointer. (static) */
uint32_t esp0;
/** Ring-0 stack segment. (static) */
RTSEL ss0;
uint16_t padding_ss0;
/** Ring-1 stack pointer. (static) */
uint32_t esp1;
/** Ring-1 stack segment. (static) */
RTSEL ss1;
uint16_t padding_ss1;
/** Ring-2 stack pointer. (static) */
uint32_t esp2;
/** Ring-2 stack segment. (static) */
RTSEL ss2;
uint16_t padding_ss2;
/** Page directory for the task. (static) */
uint32_t cr3;
/** EIP before task switch. */
uint32_t eip;
/** EFLAGS before task switch. */
uint32_t eflags;
/** EAX before task switch. */
uint32_t eax;
/** ECX before task switch. */
uint32_t ecx;
/** EDX before task switch. */
uint32_t edx;
/** EBX before task switch. */
uint32_t ebx;
/** ESP before task switch. */
uint32_t esp;
/** EBP before task switch. */
uint32_t ebp;
/** ESI before task switch. */
uint32_t esi;
/** EDI before task switch. */
uint32_t edi;
/** ES before task switch. */
RTSEL es;
uint16_t padding_es;
/** CS before task switch. */
RTSEL cs;
uint16_t padding_cs;
/** SS before task switch. */
RTSEL ss;
uint16_t padding_ss;
/** DS before task switch. */
RTSEL ds;
uint16_t padding_ds;
/** FS before task switch. */
RTSEL fs;
uint16_t padding_fs;
/** GS before task switch. */
RTSEL gs;
uint16_t padding_gs;
/** LDTR before task switch. */
RTSEL selLdt;
uint16_t padding_ldt;
/** Debug trap flag */
uint16_t fDebugTrap;
/** Offset relative to the TSS of the start of the I/O Bitmap
* and the end of the interrupt redirection bitmap. */
uint16_t offIoBitmap;
/** 32 bytes for the virtual interrupt redirection bitmap. (VME) */
uint8_t IntRedirBitmap[32];
} X86TSS32;
#pragma pack()
/** Pointer to task segment. */
typedef X86TSS32 *PX86TSS32;
/** Pointer to const task segment. */
typedef const X86TSS32 *PCX86TSS32;
/**
* 64-bit Task segment.
*/
#pragma pack(1)
typedef struct X86TSS64
{
/** Reserved. */
uint32_t u32Reserved;
/** Ring-0 stack pointer. (static) */
uint64_t rsp0;
/** Ring-1 stack pointer. (static) */
uint64_t rsp1;
/** Ring-2 stack pointer. (static) */
uint64_t rsp2;
/** Reserved. */
uint32_t u32Reserved2[2];
/* IST */
uint64_t ist1;
uint64_t ist2;
uint64_t ist3;
uint64_t ist4;
uint64_t ist5;
uint64_t ist6;
uint64_t ist7;
/* Reserved. */
uint16_t u16Reserved[5];
/** Offset relative to the TSS of the start of the I/O Bitmap
* and the end of the interrupt redirection bitmap. */
uint16_t offIoBitmap;
/** 32 bytes for the virtual interrupt redirection bitmap. (VME) */
uint8_t IntRedirBitmap[32];
} X86TSS64;
#pragma pack()
/** Pointer to a 64-bit task segment. */
typedef X86TSS64 *PX86TSS64;
/** Pointer to a const 64-bit task segment. */
typedef const X86TSS64 *PCX86TSS64;
#ifndef VBOX_FOR_DTRACE_LIB
AssertCompileSize(X86TSS64, 136);
#endif
/** @} */
/** @name Selectors.
* @{
*/
/**
* The shift used to convert a selector from and to index an index (C).
*/
#define X86_SEL_SHIFT 3
/**
* The mask used to mask off the table indicator and RPL of an selector.
*/
#define X86_SEL_MASK 0xfff8U
/**
* The mask used to mask off the RPL of an selector.
* This is suitable for checking for NULL selectors.
*/
#define X86_SEL_MASK_OFF_RPL 0xfffcU
/**
* The bit indicating that a selector is in the LDT and not in the GDT.
*/
#define X86_SEL_LDT 0x0004U
/**
* The bit mask for getting the RPL of a selector.
*/
#define X86_SEL_RPL 0x0003U
/**
* The mask covering both RPL and LDT.
* This is incidentally the same as sizeof(X86DESC) - 1, so good for limit
* checks.
*/
#define X86_SEL_RPL_LDT 0x0007U
/** @} */
/**
* x86 Exceptions/Faults/Traps.
*/
typedef enum X86XCPT
{
/** \#DE - Divide error. */
X86_XCPT_DE = 0x00,
/** \#DB - Debug event (single step, DRx, ..) */
X86_XCPT_DB = 0x01,
/** NMI - Non-Maskable Interrupt */
X86_XCPT_NMI = 0x02,
/** \#BP - Breakpoint (INT3). */
X86_XCPT_BP = 0x03,
/** \#OF - Overflow (INTO). */
X86_XCPT_OF = 0x04,
/** \#BR - Bound range exceeded (BOUND). */
X86_XCPT_BR = 0x05,
/** \#UD - Undefined opcode. */
X86_XCPT_UD = 0x06,
/** \#NM - Device not available (math coprocessor device). */
X86_XCPT_NM = 0x07,
/** \#DF - Double fault. */
X86_XCPT_DF = 0x08,
/** ??? - Coprocessor segment overrun (obsolete). */
X86_XCPT_CO_SEG_OVERRUN = 0x09,
/** \#TS - Taskswitch (TSS). */
X86_XCPT_TS = 0x0a,
/** \#NP - Segment no present. */
X86_XCPT_NP = 0x0b,
/** \#SS - Stack segment fault. */
X86_XCPT_SS = 0x0c,
/** \#GP - General protection fault. */
X86_XCPT_GP = 0x0d,
/** \#PF - Page fault. */
X86_XCPT_PF = 0x0e,
/* 0x0f is reserved (to avoid conflict with spurious interrupts in BIOS setup). */
/** \#MF - Math fault (FPU). */
X86_XCPT_MF = 0x10,
/** \#AC - Alignment check. */
X86_XCPT_AC = 0x11,
/** \#MC - Machine check. */
X86_XCPT_MC = 0x12,
/** \#XF - SIMD Floating-Pointer Exception. */
X86_XCPT_XF = 0x13,
/** \#VE - Virtualzation Exception. */
X86_XCPT_VE = 0x14,
/** \#SX - Security Exception. */
X86_XCPT_SX = 0x1f
} X86XCPT;
/** Pointer to a x86 exception code. */
typedef X86XCPT *PX86XCPT;
/** Pointer to a const x86 exception code. */
typedef const X86XCPT *PCX86XCPT;
/** The maximum exception value. */
#define X86_XCPT_MAX (X86_XCPT_SX)
/** @name Trap Error Codes
* @{
*/
/** External indicator. */
#define X86_TRAP_ERR_EXTERNAL 1
/** IDT indicator. */
#define X86_TRAP_ERR_IDT 2
/** Descriptor table indicator - If set LDT, if clear GDT. */
#define X86_TRAP_ERR_TI 4
/** Mask for getting the selector. */
#define X86_TRAP_ERR_SEL_MASK 0xfff8
/** Shift for getting the selector table index (C type index). */
#define X86_TRAP_ERR_SEL_SHIFT 3
/** @} */
/** @name \#PF Trap Error Codes
* @{
*/
/** Bit 0 - P - Not present (clear) or page level protection (set) fault. */
#define X86_TRAP_PF_P RT_BIT(0)
/** Bit 1 - R/W - Read (clear) or write (set) access. */
#define X86_TRAP_PF_RW RT_BIT(1)
/** Bit 2 - U/S - CPU executing in user mode (set) or supervisor mode (clear). */
#define X86_TRAP_PF_US RT_BIT(2)
/** Bit 3 - RSVD- Reserved bit violation (set), i.e. reserved bit was set to 1. */
#define X86_TRAP_PF_RSVD RT_BIT(3)
/** Bit 4 - I/D - Instruction fetch (set) / Data access (clear) - PAE + NXE. */
#define X86_TRAP_PF_ID RT_BIT(4)
/** @} */
#pragma pack(1)
/**
* 16-bit IDTR.
*/
typedef struct X86IDTR16
{
/** Offset. */
uint16_t offSel;
/** Selector. */
uint16_t uSel;
} X86IDTR16, *PX86IDTR16;
#pragma pack()
#pragma pack(1)
/**
* 32-bit IDTR/GDTR.
*/
typedef struct X86XDTR32
{
/** Size of the descriptor table. */
uint16_t cb;
/** Address of the descriptor table. */
#ifndef VBOX_FOR_DTRACE_LIB
uint32_t uAddr;
#else
uint16_t au16Addr[2];
#endif
} X86XDTR32, *PX86XDTR32;
#pragma pack()
#pragma pack(1)
/**
* 64-bit IDTR/GDTR.
*/
typedef struct X86XDTR64
{
/** Size of the descriptor table. */
uint16_t cb;
/** Address of the descriptor table. */
#ifndef VBOX_FOR_DTRACE_LIB
uint64_t uAddr;
#else
uint16_t au16Addr[4];
#endif
} X86XDTR64, *PX86XDTR64;
#pragma pack()
/** @name ModR/M
* @{ */
#define X86_MODRM_RM_MASK UINT8_C(0x07)
#define X86_MODRM_REG_MASK UINT8_C(0x38)
#define X86_MODRM_REG_SMASK UINT8_C(0x07)
#define X86_MODRM_REG_SHIFT 3
#define X86_MODRM_MOD_MASK UINT8_C(0xc0)
#define X86_MODRM_MOD_SMASK UINT8_C(0x03)
#define X86_MODRM_MOD_SHIFT 6
#ifndef VBOX_FOR_DTRACE_LIB
AssertCompile((X86_MODRM_RM_MASK | X86_MODRM_REG_MASK | X86_MODRM_MOD_MASK) == 0xff);
AssertCompile((X86_MODRM_REG_MASK >> X86_MODRM_REG_SHIFT) == X86_MODRM_REG_SMASK);
AssertCompile((X86_MODRM_MOD_MASK >> X86_MODRM_MOD_SHIFT) == X86_MODRM_MOD_SMASK);
#endif
/** @} */
/** @name SIB
* @{ */
#define X86_SIB_BASE_MASK UINT8_C(0x07)
#define X86_SIB_INDEX_MASK UINT8_C(0x38)
#define X86_SIB_INDEX_SMASK UINT8_C(0x07)
#define X86_SIB_INDEX_SHIFT 3
#define X86_SIB_SCALE_MASK UINT8_C(0xc0)
#define X86_SIB_SCALE_SMASK UINT8_C(0x03)
#define X86_SIB_SCALE_SHIFT 6
#ifndef VBOX_FOR_DTRACE_LIB
AssertCompile((X86_SIB_BASE_MASK | X86_SIB_INDEX_MASK | X86_SIB_SCALE_MASK) == 0xff);
AssertCompile((X86_SIB_INDEX_MASK >> X86_SIB_INDEX_SHIFT) == X86_SIB_INDEX_SMASK);
AssertCompile((X86_SIB_SCALE_MASK >> X86_SIB_SCALE_SHIFT) == X86_SIB_SCALE_SMASK);
#endif
/** @} */
/** @name General register indexes
* @{ */
#define X86_GREG_xAX 0
#define X86_GREG_xCX 1
#define X86_GREG_xDX 2
#define X86_GREG_xBX 3
#define X86_GREG_xSP 4
#define X86_GREG_xBP 5
#define X86_GREG_xSI 6
#define X86_GREG_xDI 7
#define X86_GREG_x8 8
#define X86_GREG_x9 9
#define X86_GREG_x10 10
#define X86_GREG_x11 11
#define X86_GREG_x12 12
#define X86_GREG_x13 13
#define X86_GREG_x14 14
#define X86_GREG_x15 15
/** @} */
/** @name X86_SREG_XXX - Segment register indexes.
* @{ */
#define X86_SREG_ES 0
#define X86_SREG_CS 1
#define X86_SREG_SS 2
#define X86_SREG_DS 3
#define X86_SREG_FS 4
#define X86_SREG_GS 5
/** @} */
/** Segment register count. */
#define X86_SREG_COUNT 6
/** @name X86_OP_XXX - Prefixes
* @{ */
#define X86_OP_PRF_CS UINT8_C(0x2e)
#define X86_OP_PRF_SS UINT8_C(0x36)
#define X86_OP_PRF_DS UINT8_C(0x3e)
#define X86_OP_PRF_ES UINT8_C(0x26)
#define X86_OP_PRF_FS UINT8_C(0x64)
#define X86_OP_PRF_GS UINT8_C(0x65)
#define X86_OP_PRF_SIZE_OP UINT8_C(0x66)
#define X86_OP_PRF_SIZE_ADDR UINT8_C(0x67)
#define X86_OP_PRF_LOCK UINT8_C(0xf0)
#define X86_OP_PRF_REPZ UINT8_C(0xf2)
#define X86_OP_PRF_REPNZ UINT8_C(0xf3)
#define X86_OP_REX_B UINT8_C(0x41)
#define X86_OP_REX_X UINT8_C(0x42)
#define X86_OP_REX_R UINT8_C(0x44)
#define X86_OP_REX_W UINT8_C(0x48)
/** @} */
/** @} */
#endif
|