diff options
Diffstat (limited to 'include/iprt/x86.mac')
| -rw-r--r-- | include/iprt/x86.mac | 146 |
1 files changed, 122 insertions, 24 deletions
diff --git a/include/iprt/x86.mac b/include/iprt/x86.mac index d9765261..bf10b660 100644 --- a/include/iprt/x86.mac +++ b/include/iprt/x86.mac @@ -12,15 +12,20 @@ %ifndef VBOX_FOR_DTRACE_LIB %endif %define X86_EFL_CF RT_BIT(0) +%define X86_EFL_CF_BIT 0 %define X86_EFL_1 RT_BIT(1) %define X86_EFL_PF RT_BIT(2) %define X86_EFL_AF RT_BIT(4) +%define X86_EFL_AF_BIT 4 %define X86_EFL_ZF RT_BIT(6) +%define X86_EFL_ZF_BIT 6 %define X86_EFL_SF RT_BIT(7) +%define X86_EFL_SF_BIT 7 %define X86_EFL_TF RT_BIT(8) %define X86_EFL_IF RT_BIT(9) %define X86_EFL_DF RT_BIT(10) %define X86_EFL_OF RT_BIT(11) +%define X86_EFL_OF_BIT 11 %define X86_EFL_IOPL (RT_BIT(12) | RT_BIT(13)) %define X86_EFL_NT RT_BIT(14) %define X86_EFL_RF RT_BIT(16) @@ -29,9 +34,13 @@ %define X86_EFL_VIF RT_BIT(19) %define X86_EFL_VIP RT_BIT(20) %define X86_EFL_ID RT_BIT(21) +%define X86_EFL_LIVE_MASK 0x003f7fd5 +%define X86_EFL_RA1_MASK RT_BIT_32(1) %define X86_EFL_IOPL_SHIFT 12 %define X86_EFL_GET_IOPL(efl) (((efl) >> X86_EFL_IOPL_SHIFT) & 3) -%define X86_EFL_POPF_BITS (X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_TF | X86_EFL_IF | X86_EFL_DF | X86_EFL_OF | X86_EFL_IOPL | X86_EFL_NT | X86_EFL_AC | X86_EFL_ID) +%define X86_EFL_POPF_BITS ( X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_TF | X86_EFL_IF \ + | X86_EFL_DF | X86_EFL_OF | X86_EFL_IOPL | X86_EFL_NT | X86_EFL_AC | X86_EFL_ID ) +%define X86_EFL_STATUS_BITS ( X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF ) %ifndef VBOX_FOR_DTRACE_LIB %else %endif @@ -74,6 +83,7 @@ %define X86_CPUID_FEATURE_ECX_XSAVE RT_BIT(26) %define X86_CPUID_FEATURE_ECX_OSXSAVE RT_BIT(27) %define X86_CPUID_FEATURE_ECX_AVX RT_BIT(28) +%define X86_CPUID_FEATURE_ECX_F16C RT_BIT(29) %define X86_CPUID_FEATURE_ECX_HVP RT_BIT(31) %define X86_CPUID_FEATURE_EDX_FPU RT_BIT(0) %define X86_CPUID_FEATURE_EDX_VME RT_BIT(1) @@ -203,10 +213,15 @@ %define X86_DR6_B1 RT_BIT(1) %define X86_DR6_B2 RT_BIT(2) %define X86_DR6_B3 RT_BIT(3) +%define X86_DR6_B_MASK 0x0000000f %define X86_DR6_BD RT_BIT(13) %define X86_DR6_BS RT_BIT(14) %define X86_DR6_BT RT_BIT(15) %define X86_DR6_INIT_VAL 0xFFFF0FF0 +%define X86_DR6_RA1_MASK 0xffff0ff0 +%define X86_DR6_RAZ_MASK RT_BIT_64(12) +%define X86_DR6_MBZ_MASK 0xffffffff00000000 +%define X86_DR6_B(iBp) RT_BIT_64(iBp) %define X86_DR7_L0 RT_BIT(0) %define X86_DR7_G0 RT_BIT(1) %define X86_DR7_L1 RT_BIT(2) @@ -217,6 +232,8 @@ %define X86_DR7_G3 RT_BIT(7) %define X86_DR7_LE RT_BIT(8) %define X86_DR7_GE RT_BIT(9) +%define X86_DR7_LE_ALL 0x0000000000000055 +%define X86_DR7_GE_ALL 0x00000000000000aa %define X86_DR7_GD RT_BIT(13) %define X86_DR7_RW0_MASK (3 << 16) %define X86_DR7_LEN0_MASK (3 << 18) @@ -226,30 +243,49 @@ %define X86_DR7_LEN2_MASK (3 << 26) %define X86_DR7_RW3_MASK (3 << 28) %define X86_DR7_LEN3_MASK (3 << 30) -%define X86_DR7_MB1_MASK (RT_BIT(10)) +%define X86_DR7_RA1_MASK (RT_BIT(10)) +%define X86_DR7_RAZ_MASK 0x0000d800 +%define X86_DR7_MBZ_MASK 0xffffffff00000000 %define X86_DR7_L(iBp) ( 1 << (iBp * 2) ) %define X86_DR7_G(iBp) ( 1 << (iBp * 2 + 1) ) +%define X86_DR7_L_G(iBp) ( 3 << (iBp * 2) ) %define X86_DR7_RW_EO 0 %define X86_DR7_RW_WO 1 %define X86_DR7_RW_IO 2 %define X86_DR7_RW_RW 3 %define X86_DR7_RW(iBp, fRw) ( (fRw) << ((iBp) * 4 + 16) ) +%define X86_DR7_GET_RW(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 16) ) & 3 ) +%define X86_DR7_RW_ALL_MASKS 0x33330000 +%define X86_DR7_ANY_RW_IO(uDR7) \ + ( ( 0x22220000 & (uDR7) ) %define X86_DR7_LEN_BYTE 0 %define X86_DR7_LEN_WORD 1 %define X86_DR7_LEN_QWORD 2 %define X86_DR7_LEN_DWORD 3 %define X86_DR7_LEN(iBp, cb) ( (cb) << ((iBp) * 4 + 18) ) -%define X86_DR7_GET_LEN(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 18) ) & 0x3) -%define X86_DR7_ENABLED_MASK (RT_BIT(0) | RT_BIT(1) | RT_BIT(2) | RT_BIT(3) | RT_BIT(4) | RT_BIT(5) | RT_BIT(6) | RT_BIT(7)) -%define X86_DR7_IO_ENABLED_MASK (X86_DR7_RW(0, X86_DR7_RW_IO) | X86_DR7_RW(1, X86_DR7_RW_IO) | X86_DR7_RW(2, X86_DR7_RW_IO) | X86_DR7_RW(3, X86_DR7_RW_IO)) +%define X86_DR7_GET_LEN(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 18) ) & 0x3 ) +%define X86_DR7_ENABLED_MASK 0x000000ff +%define X86_DR7_LEN_ALL_MASKS 0xcccc0000 +%define X86_DR7_RW_LEN_ALL_MASKS 0xffff0000 %define X86_DR7_INIT_VAL 0x400 +%define MSR_P5_MC_ADDR 0x00000000 +%define MSR_P5_MC_TYPE 0x00000001 %define MSR_IA32_TSC 0x10 +%define MSR_IA32_CESR 0x00000011 +%define MSR_IA32_CTR0 0x00000012 +%define MSR_IA32_CTR1 0x00000013 %define MSR_IA32_PLATFORM_ID 0x17 %ifndef MSR_IA32_APICBASE -%define MSR_IA32_APICBASE 0x1b + %define MSR_IA32_APICBASE 0x1b + %define MSR_IA32_APICBASE_EN RT_BIT_64(11) + %define MSR_IA32_APICBASE_EXTD RT_BIT_64(10) + %define MSR_IA32_APICBASE_BSP RT_BIT_64(8) + %define MSR_IA32_APICBASE_BASE_MIN 0x0000000ffffff000 %endif +%define MSR_CORE_THREAD_COUNT 0x35 %define MSR_IA32_FEATURE_CONTROL 0x3A %define MSR_IA32_FEATURE_CONTROL_LOCK RT_BIT(0) +%define MSR_IA32_FEATURE_CONTROL_SMX_VMXON RT_BIT(1) %define MSR_IA32_FEATURE_CONTROL_VMXON RT_BIT(2) %define MSR_IA32_BIOS_UPDT_TRIG 0x79 %define MSR_IA32_BIOS_SIGN_ID 0x8B @@ -259,34 +295,43 @@ %define MSR_IA32_PMC3 0xC4 %define MSR_IA32_PLATFORM_INFO 0xCE %define MSR_IA32_FSB_CLOCK_STS 0xCD +%define MSR_PKG_CST_CONFIG_CONTROL 0x000000e2 +%define MSR_IA32_MPERF 0xE7 +%define MSR_IA32_APERF 0xE8 %define MSR_IA32_MTRR_CAP 0xFE +%define MSR_BBL_CR_CTL3 0x11e %ifndef MSR_IA32_SYSENTER_CS %define MSR_IA32_SYSENTER_CS 0x174 %define MSR_IA32_SYSENTER_ESP 0x175 %define MSR_IA32_SYSENTER_EIP 0x176 %endif -%define MSR_IA32_MCP_CAP 0x179 -%define MSR_IA32_MCP_STATUS 0x17A -%define MSR_IA32_MCP_CTRL 0x17B -%define MSR_IA32_DEBUGCTL 0x1D9 +%define MSR_IA32_MCG_CAP 0x179 +%define MSR_IA32_MCG_STATUS 0x17A +%define MSR_IA32_MCG_CTRL 0x17B %define MSR_IA32_CR_PAT 0x277 %define MSR_IA32_PERFEVTSEL0 0x186 %define MSR_IA32_PERFEVTSEL1 0x187 -%define MSR_IA32_FLEX_RATIO 0x194 +%define MSR_FLEX_RATIO 0x194 %define MSR_IA32_PERF_STATUS 0x198 %define MSR_IA32_PERF_CTL 0x199 %define MSR_IA32_THERM_STATUS 0x19c %define MSR_IA32_MISC_ENABLE 0x1A0 -%define MSR_IA32_MISC_ENABLE_FAST_STRINGS RT_BIT(0) -%define MSR_IA32_MISC_ENABLE_TCC RT_BIT(3) -%define MSR_IA32_MISC_ENABLE_PERF_MON RT_BIT(7) -%define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL RT_BIT(11) -%define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL RT_BIT(12) -%define MSR_IA32_MISC_ENABLE_SST_ENABLE RT_BIT(16) -%define MSR_IA32_MISC_ENABLE_MONITOR RT_BIT(18) -%define MSR_IA32_MISC_ENABLE_LIMIT_CPUID RT_BIT(22) -%define MSR_IA32_MISC_ENABLE_XTPR_MSG_DISABLE RT_BIT(23) -%define MSR_IA32_MISC_ENABLE_XD_DISABLE RT_BIT(34) +%define MSR_IA32_MISC_ENABLE_FAST_STRINGS RT_BIT_64(0) +%define MSR_IA32_MISC_ENABLE_TCC RT_BIT_64(3) +%define MSR_IA32_MISC_ENABLE_PERF_MON RT_BIT_64(7) +%define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL RT_BIT_64(11) +%define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL RT_BIT_64(12) +%define MSR_IA32_MISC_ENABLE_SST_ENABLE RT_BIT_64(16) +%define MSR_IA32_MISC_ENABLE_MONITOR RT_BIT_64(18) +%define MSR_IA32_MISC_ENABLE_LIMIT_CPUID RT_BIT_64(22) +%define MSR_IA32_MISC_ENABLE_XTPR_MSG_DISABLE RT_BIT_64(23) +%define MSR_IA32_MISC_ENABLE_XD_DISABLE RT_BIT_64(34) +%define MSR_IA32_DEBUGCTL 0x000001d9 +%define MSR_P4_LASTBRANCH_TOS 0x000001da +%define MSR_P4_LASTBRANCH_0 0x000001db +%define MSR_P4_LASTBRANCH_1 0x000001dc +%define MSR_P4_LASTBRANCH_2 0x000001dd +%define MSR_P4_LASTBRANCH_3 0x000001de %define IA32_MTRR_PHYSBASE0 0x200 %define IA32_MTRR_PHYSMASK0 0x201 %define IA32_MTRR_PHYSBASE1 0x202 @@ -332,11 +377,14 @@ %define MSR_IA32_VMX_CR4_FIXED0 0x488 %define MSR_IA32_VMX_CR4_FIXED1 0x489 %define MSR_IA32_VMX_VMCS_ENUM 0x48A +%define MSR_IA32_VMX_VMFUNC 0x491 %define MSR_IA32_VMX_PROCBASED_CTLS2 0x48B -%define MSR_IA32_VMX_EPT_CAPS 0x48C +%define MSR_IA32_VMX_EPT_VPID_CAP 0x48C %define MSR_IA32_DS_AREA 0x600 -%define MSR_IA32_APIC_START 0x800 -%define MSR_IA32_APIC_END 0x900 +%define MSR_RAPL_POWER_UNIT 0x606 +%define MSR_IA32_X2APIC_START 0x800 +%define MSR_IA32_X2APIC_TPR 0x808 +%define MSR_IA32_X2APIC_END 0xBFF %define MSR_K6_EFER 0xc0000080 %define MSR_K6_EFER_SCE RT_BIT(0) %define MSR_K6_EFER_LME RT_BIT(8) @@ -377,6 +425,8 @@ %define MSR_K8_IORRMASK1 0xc0010019 %define MSR_K8_TOP_MEM1 0xc001001a %define MSR_K8_TOP_MEM2 0xc001001d +%define MSR_K8_NB_CFG 0xc001001f +%define MSR_K8_INT_PENDING 0xc0010055 %define MSR_K8_VM_CR 0xc0010114 %define MSR_K8_VM_CR_SVM_DISABLE RT_BIT(4) %define MSR_K8_IGNNE 0xc0010115 @@ -402,6 +452,7 @@ %define X86_PAGE_4M_OFFSET_MASK 0x003fffff %define X86_PAGE_4M_BASE_MASK 0xffffffffffc00000 %define X86_PAGE_4M_BASE_MASK_32 0xffc00000 +%define X86_IS_CANONICAL(a_u64Addr) ((uint64_t)(a_u64Addr) + 0x800000000000 < UINT64_C(0x1000000000000)) %define X86_PTE_BIT_P 0 %define X86_PTE_BIT_RW 1 %define X86_PTE_BIT_US 2 @@ -543,8 +594,39 @@ %define X86_FCW_RC_UP 0x0800 %define X86_FCW_RC_ZERO 0x0c00 %define X86_FCW_ZERO_MASK 0xf080 +%define X86_MSXCR_IE RT_BIT(0) +%define X86_MSXCR_DE RT_BIT(1) +%define X86_MSXCR_ZE RT_BIT(2) +%define X86_MSXCR_OE RT_BIT(3) +%define X86_MSXCR_UE RT_BIT(4) +%define X86_MSXCR_PE RT_BIT(5) +%define X86_MSXCR_DAZ RT_BIT(6) +%define X86_MSXCR_IM RT_BIT(7) +%define X86_MSXCR_DM RT_BIT(8) +%define X86_MSXCR_ZM RT_BIT(9) +%define X86_MSXCR_OM RT_BIT(10) +%define X86_MSXCR_UM RT_BIT(11) +%define X86_MSXCR_PM RT_BIT(12) +%define X86_MSXCR_RC_MASK 0x6000 +%define X86_MSXCR_RC_NEAREST 0x0000 +%define X86_MSXCR_RC_DOWN 0x2000 +%define X86_MSXCR_RC_UP 0x4000 +%define X86_MSXCR_RC_ZERO 0x6000 +%define X86_MSXCR_FZ RT_BIT(15) +%define X86_MSXCR_MM RT_BIT(16) %ifndef VBOX_FOR_DTRACE_LIB %endif +%define X86DESCATTR_TYPE 0x0000000f +%define X86DESCATTR_DT 0x00000010 +%define X86DESCATTR_DPL 0x00000060 +%define X86DESCATTR_DPL_SHIFT 5 +%define X86DESCATTR_P 0x00000080 +%define X86DESCATTR_LIMIT_HIGH 0x00000f00 +%define X86DESCATTR_AVL 0x00001000 +%define X86DESCATTR_L 0x00002000 +%define X86DESCATTR_D 0x00004000 +%define X86DESCATTR_G 0x00008000 +%define X86DESCATTR_UNUSABLE 0x00010000 %ifndef VBOX_FOR_DTRACE_LIB %endif %ifndef VBOX_FOR_DTRACE_LIB @@ -645,6 +727,7 @@ %define X86_SEL_LDT 0x0004 %define X86_SEL_RPL 0x0003 %define X86_SEL_RPL_LDT 0x0007 +%define X86_XCPT_MAX (X86_XCPT_SX) %define X86_TRAP_ERR_EXTERNAL 1 %define X86_TRAP_ERR_IDT 2 %define X86_TRAP_ERR_TI 4 @@ -702,5 +785,20 @@ %define X86_SREG_FS 4 %define X86_SREG_GS 5 %define X86_SREG_COUNT 6 +%define X86_OP_PRF_CS 0x2e +%define X86_OP_PRF_SS 0x36 +%define X86_OP_PRF_DS 0x3e +%define X86_OP_PRF_ES 0x26 +%define X86_OP_PRF_FS 0x64 +%define X86_OP_PRF_GS 0x65 +%define X86_OP_PRF_SIZE_OP 0x66 +%define X86_OP_PRF_SIZE_ADDR 0x67 +%define X86_OP_PRF_LOCK 0xf0 +%define X86_OP_PRF_REPZ 0xf2 +%define X86_OP_PRF_REPNZ 0xf3 +%define X86_OP_REX_B 0x41 +%define X86_OP_REX_X 0x42 +%define X86_OP_REX_R 0x44 +%define X86_OP_REX_W 0x48 %endif %include "iprt/x86extra.mac" |