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authorLorry Tar Creator <lorry-tar-importer@baserock.org>2014-03-26 19:21:20 +0000
committer <>2014-05-08 15:03:54 +0000
commitfb123f93f9f5ce42c8e5785d2f8e0edaf951740e (patch)
treec2103d76aec5f1f10892cd1d3a38e24f665ae5db /src/recompiler/target-i386/cpu.h
parent58ed4748338f9466599adfc8a9171280ed99e23f (diff)
downloadVirtualBox-master.tar.gz
Imported from /home/lorry/working-area/delta_VirtualBox/VirtualBox-4.3.10.tar.bz2.HEADVirtualBox-4.3.10master
Diffstat (limited to 'src/recompiler/target-i386/cpu.h')
-rw-r--r--src/recompiler/target-i386/cpu.h38
1 files changed, 32 insertions, 6 deletions
diff --git a/src/recompiler/target-i386/cpu.h b/src/recompiler/target-i386/cpu.h
index b5159bf9..2adbd869 100644
--- a/src/recompiler/target-i386/cpu.h
+++ b/src/recompiler/target-i386/cpu.h
@@ -65,6 +65,7 @@
# include <VBox/vmm/vmm.h>
# include <VBox/vmm/stam.h>
# include <VBox/vmm/cpumctx.h>
+# undef MSR_IA32_APICBASE_BSP
#endif /* VBOX */
#define R_EAX 0
@@ -115,6 +116,10 @@
#define DESC_W_MASK (1 << 9) /* data: writable */
#define DESC_TSS_BUSY_MASK (1 << 9)
+#ifdef VBOX
+# define DESC_INTEL_UNUSABLE RT_BIT_32(16+8) /**< Internal VT-x bit for NULL sectors. */
+# define DESC_RAW_FLAG_BITS UINT32_C(0x00ffffff) /**< Flag bits we load from the descriptor. */
+#endif
/* eflags masks */
#define CC_C 0x0001
@@ -909,7 +914,7 @@ typedef struct CPUX86State_Ver16 {
# define CPU_RAW_RING0 0x0002 /* Set after first time RawR0 is executed, never cleared. */
# define CPU_EMULATE_SINGLE_INSTR 0x0040 /* Execute a single instruction in emulation mode */
# define CPU_EMULATE_SINGLE_STEP 0x0080 /* go into single step mode */
-# define CPU_RAW_HWACC 0x0100 /* Set after first time HWACC is executed, never cleared. */
+# define CPU_RAW_HM 0x0100 /* Set after first time HWACC is executed, never cleared. */
/** @} */
#endif /* !VBOX */
@@ -930,11 +935,19 @@ void cpu_set_ferr(CPUX86State *s);
/* this function must always be used to load data in the segment
cache: it synchronizes the hflags with the segment cache values */
+#ifndef VBOX
static inline void cpu_x86_load_seg_cache(CPUX86State *env,
int seg_reg, unsigned int selector,
target_ulong base,
unsigned int limit,
unsigned int flags)
+#else
+static inline void cpu_x86_load_seg_cache_with_clean_flags(CPUX86State *env,
+ int seg_reg, unsigned int selector,
+ target_ulong base,
+ unsigned int limit,
+ unsigned int flags)
+#endif
{
SegmentCache *sc;
unsigned int new_hflags;
@@ -943,12 +956,8 @@ static inline void cpu_x86_load_seg_cache(CPUX86State *env,
sc->selector = selector;
sc->base = base;
sc->limit = limit;
-#ifndef VBOX
- sc->flags = flags;
-#else
- if (flags & DESC_P_MASK)
- flags |= DESC_A_MASK; /* Make sure the A bit is set to avoid trouble. */
sc->flags = flags;
+#ifdef VBOX
sc->newselector = 0;
sc->fVBoxFlags = CPUMSELREG_FLAGS_VALID;
#endif
@@ -995,6 +1004,23 @@ static inline void cpu_x86_load_seg_cache(CPUX86State *env,
}
}
+#ifdef VBOX
+/* Raw input, adjust the flags adding the stupid intel flag when applicable. */
+static inline void cpu_x86_load_seg_cache(CPUX86State *env,
+ int seg_reg, unsigned int selector,
+ target_ulong base,
+ unsigned int limit,
+ unsigned int flags)
+{
+ flags &= DESC_RAW_FLAG_BITS;
+ if (flags & DESC_P_MASK)
+ flags |= DESC_A_MASK; /* Make sure the A bit is set to avoid trouble. */
+ else if (selector < 4U)
+ flags |= DESC_INTEL_UNUSABLE;
+ cpu_x86_load_seg_cache_with_clean_flags(env, seg_reg, selector, base, limit, flags);
+}
+#endif
+
static inline void cpu_x86_load_seg_cache_sipi(CPUX86State *env,
int sipi_vector)
{