summaryrefslogtreecommitdiff
path: root/altera-socfpga/example/constrain_clocks.sdc
blob: 840b227b56fce6b187e128f21ad9b3bffb66b305 (plain)
1
2
3
create_clock -name "clk_50mhz" -period 20.000ns clk_clk
derive_pll_clocks -create_base_clocks
derive_clock_uncertainty