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* SoCFPGA: Add generated DTSEdward Cragg2015-09-241-0/+1104
| | | | | | This is generated using the Altera SoC EDS, see README for details. Change-Id: Ie829c0b9382138f89b7ec591aeafd0a2c3e20fcf
* SoCFPGA: Add Quartus generated hardware handoff filesEdward Cragg2015-09-2415-0/+14320
| | | | | | | | These files are automatically generated by the Quartus software suite and added here unmodified. On system build they are combined with U-Boot source to build the SPL preloader for SoCFPGA SoCs Change-Id: I36304957adae1ded94171af41f272743163e8869
* SoCFPGA: Add Quartus generated BSP filesEdward Cragg2015-09-2410-0/+2377
| | | | | | | | These files are automatically generated by the Altera SoC EDS embedded design suite and added here unmodified. On system build they are combined with U-Boot source to build the SPL preloader for SoCFPGA SoCs Change-Id: Ie0b081b7e91789c77c870b2e7b87f868a1b38f3b
* Move already merged 'SoCFPGA: Add example Quartus files'Edward Cragg2015-09-242-0/+619
This was accidentally merged somehow, moving it to a folder of its own rather than using an orphan branch. Change-Id: I76e285d1c76825d9ba6c904067d9d6405b210b5a