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authorEdward Cragg <edward.cragg@codethink.co.uk>2015-05-21 17:59:37 +0100
committerEdward Cragg <edward.cragg@codethink.co.uk>2015-09-24 09:28:10 +0100
commitaa7ffdb23ae929a63c829abda623dd1710dd656c (patch)
tree28c44009be11cf321202b45de9b6ee7d059764b8 /altera-socfpga
parentc4ba753ce0832526ff3eff7ed6b989724bda4205 (diff)
downloadbsp-support-aa7ffdb23ae929a63c829abda623dd1710dd656c.tar.gz
SoCFPGA: Add generated DTS
This is generated using the Altera SoC EDS, see README for details. Change-Id: Ie829c0b9382138f89b7ec591aeafd0a2c3e20fcf
Diffstat (limited to 'altera-socfpga')
-rw-r--r--altera-socfpga/dts-generated/socfpga-devkit.dts1104
1 files changed, 1104 insertions, 0 deletions
diff --git a/altera-socfpga/dts-generated/socfpga-devkit.dts b/altera-socfpga/dts-generated/socfpga-devkit.dts
new file mode 100644
index 0000000..5e21308
--- /dev/null
+++ b/altera-socfpga/dts-generated/socfpga-devkit.dts
@@ -0,0 +1,1104 @@
+/*
+ * This devicetree is generated by sopc2dts version 15.0 [329cedd0fcd89faa59419891cd6fd5a18506b059] on Tue May 26 14:28:29 BST 2015
+ * Sopc2dts is written by Walter Goossens <waltergoossens@home.nl>
+ * in cooperation with the nios2 community <nios2-dev@lists.rocketboards.org>
+ */
+/dts-v1/;
+
+/ {
+ model = "Altera SOCFPGA Cyclone V"; /* appended from boardinfo */
+ compatible = "altr,socfpga-cyclone5", "altr,socfpga"; /* appended from boardinfo */
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ aliases {
+ ethernet0 = "/sopc@0/ethernet@0xff702000";
+ }; //end aliases
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ hps_0_arm_a9_0: cpu@0x0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9-15.0", "arm,cortex-a9";
+ reg = <0x00000000>;
+ next-level-cache = <&hps_0_L2>; /* appended from boardinfo */
+ }; //end cpu@0x0 (hps_0_arm_a9_0)
+
+ hps_0_arm_a9_1: cpu@0x1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9-15.0", "arm,cortex-a9";
+ reg = <0x00000001>;
+ next-level-cache = <&hps_0_L2>; /* appended from boardinfo */
+ }; //end cpu@0x1 (hps_0_arm_a9_1)
+ }; //end cpus
+
+ memory {
+ device_type = "memory";
+ reg = <0xffff0000 0x00010000>,
+ <0x00000000 0x80000000>;
+ }; //end memory
+
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ clk_0: clk_0 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <50000000>; /* 50.00 MHz */
+ clock-output-names = "clk_0-clk";
+ }; //end clk_0 (clk_0)
+
+ hps_0_eosc1: hps_0_eosc1 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <25000000>; /* 25.00 MHz */
+ clock-output-names = "hps_0_eosc1-clk";
+ }; //end hps_0_eosc1 (hps_0_eosc1)
+
+ hps_0_eosc2: hps_0_eosc2 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <25000000>; /* 25.00 MHz */
+ clock-output-names = "hps_0_eosc2-clk";
+ }; //end hps_0_eosc2 (hps_0_eosc2)
+
+ hps_0_f2s_periph_ref_clk: hps_0_f2s_periph_ref_clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>; /* 0.00 Hz */
+ clock-output-names = "hps_0_f2s_periph_ref_clk-clk";
+ }; //end hps_0_f2s_periph_ref_clk (hps_0_f2s_periph_ref_clk)
+
+ hps_0_f2s_sdram_ref_clk: hps_0_f2s_sdram_ref_clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>; /* 0.00 Hz */
+ clock-output-names = "hps_0_f2s_sdram_ref_clk-clk";
+ }; //end hps_0_f2s_sdram_ref_clk (hps_0_f2s_sdram_ref_clk)
+ }; //end clocks
+
+ sopc0: sopc@0 {
+ device_type = "soc";
+ ranges;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "ALTR,avalon", "simple-bus";
+ bus-frequency = <0>;
+
+ hps_0_arm_gic_0: intc@0xfffed000 {
+ compatible = "arm,cortex-a9-gic-15.0", "arm,cortex-a9-gic";
+ reg = <0xfffed000 0x00001000>,
+ <0xfffec100 0x00000100>;
+ reg-names = "axi_slave0", "axi_slave1";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ }; //end intc@0xfffed000 (hps_0_arm_gic_0)
+
+ hps_0_L2: L2-cache@0xfffef000 {
+ compatible = "arm,pl310-cache-15.0", "arm,pl310-cache";
+ reg = <0xfffef000 0x00001000>;
+ interrupt-parent = <&hps_0_arm_gic_0>;
+ interrupts = <0 38 4>;
+ cache-level = <2>; /* embeddedsw.dts.params.cache-level type NUMBER */
+ cache-unified; /* appended from boardinfo */
+ arm,tag-latency = <1 1 1>; /* appended from boardinfo */
+ arm,data-latency = <2 1 1>; /* appended from boardinfo */
+ }; //end L2-cache@0xfffef000 (hps_0_L2)
+
+ hps_0_dma: dma@0xffe01000 {
+ compatible = "arm,pl330-15.0", "arm,pl330", "arm,primecell";
+ reg = <0xffe01000 0x00001000>;
+ interrupt-parent = <&hps_0_arm_gic_0>;
+ interrupts = <0 104 4>;
+ clocks = <&l4_main_clk>;
+ #dma-cells = <1>; /* embeddedsw.dts.params.#dma-cells type NUMBER */
+ #dma-channels = <8>; /* embeddedsw.dts.params.#dma-channels type NUMBER */
+ #dma-requests = <32>; /* embeddedsw.dts.params.#dma-requests type NUMBER */
+ clock-names = "apb_pclk"; /* embeddedsw.dts.params.clock-names type STRING */
+ copy-align = <3>; /* embeddedsw.dts.params.copy-align type NUMBER */
+ nr-irqs = <9>; /* embeddedsw.dts.params.nr-irqs type NUMBER */
+ nr-valid-peri = <9>; /* embeddedsw.dts.params.nr-valid-peri type NUMBER */
+ }; //end dma@0xffe01000 (hps_0_dma)
+
+ hps_0_sysmgr: sysmgr@0xffd08000 {
+ compatible = "altr,sys-mgr-15.0", "altr,sys-mgr", "syscon";
+ reg = <0xffd08000 0x00000400>;
+ cpu1-start-addr = <4291854532>; /* embeddedsw.dts.params.cpu1-start-addr type NUMBER */
+ }; //end sysmgr@0xffd08000 (hps_0_sysmgr)
+
+ hps_0_clkmgr: clkmgr@0xffd04000 {
+ compatible = "altr,clk-mgr-15.0", "altr,clk-mgr";
+ reg = <0xffd04000 0x00001000>;
+ clocks = <&hps_0_eosc1 &hps_0_eosc2 &hps_0_f2s_periph_ref_clk &hps_0_f2s_sdram_ref_clk>;
+ clock-names = "eosc1", "eosc2", "f2s_periph_ref_clk", "f2s_sdram_ref_clk";
+
+ clock_tree {
+ #size-cells = <0>;
+ #address-cells = <1>;
+
+ sdram_pll: sdram_pll {
+ compatible = "altr,socfpga-pll-clock";
+ reg = <0x000000c0>;
+ clocks = <&hps_0_eosc1 &hps_0_eosc2 &hps_0_f2s_sdram_ref_clk>;
+ clock-names = "hps_0_eosc1", "hps_0_eosc2", "hps_0_f2s_sdram_ref_clk";
+ #clock-cells = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ddr_dqs_clk: ddr_dqs_clk {
+ compatible = "altr,socfpga-perip-clk";
+ reg = <0x000000c8>;
+ clocks = <&sdram_pll>;
+ #clock-cells = <0>;
+ }; //end ddr_dqs_clk (ddr_dqs_clk)
+
+ ddr_2x_dqs_clk: ddr_2x_dqs_clk {
+ compatible = "altr,socfpga-perip-clk";
+ reg = <0x000000cc>;
+ clocks = <&sdram_pll>;
+ #clock-cells = <0>;
+ }; //end ddr_2x_dqs_clk (ddr_2x_dqs_clk)
+
+ ddr_dq_clk: ddr_dq_clk {
+ compatible = "altr,socfpga-perip-clk";
+ reg = <0x000000d0>;
+ clocks = <&sdram_pll>;
+ #clock-cells = <0>;
+ }; //end ddr_dq_clk (ddr_dq_clk)
+
+ s2f_usr2_clk: s2f_usr2_clk {
+ compatible = "altr,socfpga-perip-clk";
+ reg = <0x000000d4>;
+ clocks = <&sdram_pll>;
+ #clock-cells = <0>;
+ }; //end s2f_usr2_clk (s2f_usr2_clk)
+ }; //end sdram_pll (sdram_pll)
+
+ periph_pll: periph_pll {
+ compatible = "altr,socfpga-pll-clock";
+ reg = <0x00000080>;
+ clocks = <&hps_0_eosc1 &hps_0_eosc2 &hps_0_f2s_periph_ref_clk>;
+ clock-names = "hps_0_eosc1", "hps_0_eosc2", "hps_0_f2s_periph_ref_clk";
+ #clock-cells = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ per_nand_mmc_clk: per_nand_mmc_clk {
+ compatible = "altr,socfpga-perip-clk";
+ reg = <0x00000094>;
+ clocks = <&periph_pll>;
+ #clock-cells = <0>;
+ }; //end per_nand_mmc_clk (per_nand_mmc_clk)
+
+ per_base_clk: per_base_clk {
+ compatible = "altr,socfpga-perip-clk";
+ reg = <0x00000098>;
+ clocks = <&periph_pll>;
+ #clock-cells = <0>;
+ }; //end per_base_clk (per_base_clk)
+
+ per_qspi_clk: per_qspi_clk {
+ compatible = "altr,socfpga-perip-clk";
+ reg = <0x00000090>;
+ clocks = <&periph_pll>;
+ #clock-cells = <0>;
+ }; //end per_qspi_clk (per_qspi_clk)
+
+ s2f_usr1_clk: s2f_usr1_clk {
+ compatible = "altr,socfpga-perip-clk";
+ reg = <0x0000009c>;
+ clocks = <&periph_pll>;
+ #clock-cells = <0>;
+ }; //end s2f_usr1_clk (s2f_usr1_clk)
+
+ emac0_clk: emac0_clk {
+ compatible = "altr,socfpga-perip-clk";
+ reg = <0x00000088>;
+ clocks = <&periph_pll>;
+ #clock-cells = <0>;
+ }; //end emac0_clk (emac0_clk)
+
+ emac1_clk: emac1_clk {
+ compatible = "altr,socfpga-perip-clk";
+ reg = <0x0000008c>;
+ clocks = <&periph_pll>;
+ #clock-cells = <0>;
+ }; //end emac1_clk (emac1_clk)
+ }; //end periph_pll (periph_pll)
+
+ main_pll: main_pll {
+ compatible = "altr,socfpga-pll-clock";
+ reg = <0x00000040>;
+ clocks = <&hps_0_eosc1>;
+ #clock-cells = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cfg_s2f_usr0_clk: cfg_s2f_usr0_clk {
+ compatible = "altr,socfpga-perip-clk";
+ reg = <0x0000005c>;
+ clocks = <&main_pll>;
+ #clock-cells = <0>;
+ }; //end cfg_s2f_usr0_clk (cfg_s2f_usr0_clk)
+
+ main_qspi_clk: main_qspi_clk {
+ compatible = "altr,socfpga-perip-clk";
+ reg = <0x00000054>;
+ clocks = <&main_pll>;
+ #clock-cells = <0>;
+ }; //end main_qspi_clk (main_qspi_clk)
+
+ dbg_base_clk: dbg_base_clk {
+ compatible = "altr,socfpga-perip-clk";
+ reg = <0x00000050>;
+ clocks = <&main_pll &hps_0_eosc1>;
+ clock-names = "main_pll", "hps_0_eosc1";
+ #clock-cells = <0>;
+ div-reg = <0x000000e8 0x00000000 0x00000009>;
+ }; //end dbg_base_clk (dbg_base_clk)
+
+ mpuclk: mpuclk {
+ compatible = "altr,socfpga-perip-clk";
+ reg = <0x00000048>;
+ clocks = <&main_pll>;
+ #clock-cells = <0>;
+ div-reg = <0x000000e0 0x00000000 0x00000009>;
+ }; //end mpuclk (mpuclk)
+
+ mainclk: mainclk {
+ compatible = "altr,socfpga-perip-clk";
+ reg = <0x0000004c>;
+ clocks = <&main_pll>;
+ #clock-cells = <0>;
+ div-reg = <0x000000e4 0x00000000 0x00000009>;
+ }; //end mainclk (mainclk)
+
+ main_nand_sdmmc_clk: main_nand_sdmmc_clk {
+ compatible = "altr,socfpga-perip-clk";
+ reg = <0x00000058>;
+ clocks = <&main_pll>;
+ #clock-cells = <0>;
+ }; //end main_nand_sdmmc_clk (main_nand_sdmmc_clk)
+ }; //end main_pll (main_pll)
+
+ mpu_l2_ram_clk: mpu_l2_ram_clk {
+ compatible = "altr,socfpga-gate-clk";
+ clocks = <&mpuclk>;
+ #clock-cells = <0>;
+ fixed-divider = <2>;
+ }; //end mpu_l2_ram_clk (mpu_l2_ram_clk)
+
+ l4_main_clk: l4_main_clk {
+ compatible = "altr,socfpga-gate-clk";
+ clocks = <&mainclk>;
+ #clock-cells = <0>;
+ clk-gate = <0x00000060 0x00000000>;
+ }; //end l4_main_clk (l4_main_clk)
+
+ l3_mp_clk: l3_mp_clk {
+ compatible = "altr,socfpga-gate-clk";
+ clocks = <&mainclk>;
+ #clock-cells = <0>;
+ clk-gate = <0x00000060 0x00000001>;
+ div-reg = <0x00000064 0x00000000 0x00000002>;
+ }; //end l3_mp_clk (l3_mp_clk)
+
+ l3_sp_clk: l3_sp_clk {
+ compatible = "altr,socfpga-gate-clk";
+ clocks = <&l3_mp_clk>;
+ #clock-cells = <0>;
+ div-reg = <0x00000064 0x00000002 0x00000002>;
+ }; //end l3_sp_clk (l3_sp_clk)
+
+ l4_mp_clk: l4_mp_clk {
+ compatible = "altr,socfpga-gate-clk";
+ clocks = <&mainclk &per_base_clk>;
+ clock-names = "mainclk", "per_base_clk";
+ #clock-cells = <0>;
+ clk-gate = <0x00000060 0x00000002>;
+ div-reg = <0x00000064 0x00000004 0x00000003>;
+ }; //end l4_mp_clk (l4_mp_clk)
+
+ l4_sp_clk: l4_sp_clk {
+ compatible = "altr,socfpga-gate-clk";
+ clocks = <&mainclk &per_base_clk>;
+ clock-names = "mainclk", "per_base_clk";
+ #clock-cells = <0>;
+ clk-gate = <0x00000060 0x00000003>;
+ div-reg = <0x00000064 0x00000007 0x00000003>;
+ }; //end l4_sp_clk (l4_sp_clk)
+
+ dbg_at_clk: dbg_at_clk {
+ compatible = "altr,socfpga-gate-clk";
+ clocks = <&dbg_base_clk>;
+ #clock-cells = <0>;
+ clk-gate = <0x00000060 0x00000004>;
+ div-reg = <0x00000068 0x00000000 0x00000002>;
+ }; //end dbg_at_clk (dbg_at_clk)
+
+ dbg_clk: dbg_clk {
+ compatible = "altr,socfpga-gate-clk";
+ clocks = <&dbg_at_clk>;
+ #clock-cells = <0>;
+ clk-gate = <0x00000060 0x00000005>;
+ div-reg = <0x00000068 0x00000002 0x00000002>;
+ }; //end dbg_clk (dbg_clk)
+
+ dbg_trace_clk: dbg_trace_clk {
+ compatible = "altr,socfpga-gate-clk";
+ clocks = <&dbg_base_clk>;
+ #clock-cells = <0>;
+ clk-gate = <0x00000060 0x00000006>;
+ div-reg = <0x0000006c 0x00000000 0x00000003>;
+ }; //end dbg_trace_clk (dbg_trace_clk)
+
+ dbg_timer_clk: dbg_timer_clk {
+ compatible = "altr,socfpga-gate-clk";
+ clocks = <&dbg_base_clk>;
+ #clock-cells = <0>;
+ clk-gate = <0x00000060 0x00000007>;
+ }; //end dbg_timer_clk (dbg_timer_clk)
+
+ cfg_clk: cfg_clk {
+ compatible = "altr,socfpga-gate-clk";
+ clocks = <&cfg_s2f_usr0_clk>;
+ #clock-cells = <0>;
+ clk-gate = <0x00000060 0x00000008>;
+ }; //end cfg_clk (cfg_clk)
+
+ h2f_user0_clock: h2f_user0_clock {
+ compatible = "altr,socfpga-gate-clk";
+ clocks = <&cfg_s2f_usr0_clk>;
+ #clock-cells = <0>;
+ clk-gate = <0x00000060 0x00000009>;
+ }; //end h2f_user0_clock (h2f_user0_clock)
+
+ emac_0_clk: emac_0_clk {
+ compatible = "altr,socfpga-gate-clk";
+ clocks = <&emac0_clk>;
+ #clock-cells = <0>;
+ clk-gate = <0x000000a0 0x00000000>;
+ }; //end emac_0_clk (emac_0_clk)
+
+ emac_1_clk: emac_1_clk {
+ compatible = "altr,socfpga-gate-clk";
+ clocks = <&emac1_clk>;
+ #clock-cells = <0>;
+ clk-gate = <0x000000a0 0x00000001>;
+ }; //end emac_1_clk (emac_1_clk)
+
+ usb_mp_clk: usb_mp_clk {
+ compatible = "altr,socfpga-gate-clk";
+ clocks = <&per_base_clk>;
+ #clock-cells = <0>;
+ clk-gate = <0x000000a0 0x00000002>;
+ div-reg = <0x000000a4 0x00000000 0x00000003>;
+ }; //end usb_mp_clk (usb_mp_clk)
+
+ spi_m_clk: spi_m_clk {
+ compatible = "altr,socfpga-gate-clk";
+ clocks = <&per_base_clk>;
+ #clock-cells = <0>;
+ clk-gate = <0x000000a0 0x00000003>;
+ div-reg = <0x000000a4 0x00000003 0x00000003>;
+ }; //end spi_m_clk (spi_m_clk)
+
+ can0_clk: can0_clk {
+ compatible = "altr,socfpga-gate-clk";
+ clocks = <&per_base_clk>;
+ #clock-cells = <0>;
+ clk-gate = <0x000000a0 0x00000004>;
+ div-reg = <0x000000a4 0x00000006 0x00000003>;
+ }; //end can0_clk (can0_clk)
+
+ can1_clk: can1_clk {
+ compatible = "altr,socfpga-gate-clk";
+ clocks = <&per_base_clk>;
+ #clock-cells = <0>;
+ clk-gate = <0x000000a0 0x00000005>;
+ div-reg = <0x000000a4 0x00000009 0x00000003>;
+ }; //end can1_clk (can1_clk)
+
+ gpio_db_clk: gpio_db_clk {
+ compatible = "altr,socfpga-gate-clk";
+ clocks = <&per_base_clk>;
+ #clock-cells = <0>;
+ clk-gate = <0x000000a0 0x00000006>;
+ div-reg = <0x000000a8 0x00000000 0x00000018>;
+ }; //end gpio_db_clk (gpio_db_clk)
+
+ h2f_user1_clock: h2f_user1_clock {
+ compatible = "altr,socfpga-gate-clk";
+ clocks = <&s2f_usr1_clk>;
+ #clock-cells = <0>;
+ clk-gate = <0x000000a0 0x00000007>;
+ }; //end h2f_user1_clock (h2f_user1_clock)
+
+ sdmmc_clk: sdmmc_clk {
+ compatible = "altr,socfpga-gate-clk";
+ clocks = <&hps_0_f2s_periph_ref_clk &main_nand_sdmmc_clk &per_nand_mmc_clk>;
+ clock-names = "hps_0_f2s_periph_ref_clk", "main_nand_sdmmc_clk", "per_nand_mmc_clk";
+ #clock-cells = <0>;
+ clk-gate = <0x000000a0 0x00000008>;
+ }; //end sdmmc_clk (sdmmc_clk)
+
+ nand_x_clk: nand_x_clk {
+ compatible = "altr,socfpga-gate-clk";
+ clocks = <&hps_0_f2s_periph_ref_clk &main_nand_sdmmc_clk &per_nand_mmc_clk>;
+ clock-names = "hps_0_f2s_periph_ref_clk", "main_nand_sdmmc_clk", "per_nand_mmc_clk";
+ #clock-cells = <0>;
+ clk-gate = <0x000000a0 0x00000009>;
+ }; //end nand_x_clk (nand_x_clk)
+
+ nand_clk: nand_clk {
+ compatible = "altr,socfpga-gate-clk";
+ clocks = <&hps_0_f2s_periph_ref_clk &main_nand_sdmmc_clk &per_nand_mmc_clk>;
+ clock-names = "hps_0_f2s_periph_ref_clk", "main_nand_sdmmc_clk", "per_nand_mmc_clk";
+ #clock-cells = <0>;
+ clk-gate = <0x000000a0 0x0000000a>;
+ fixed-divider = <4>;
+ }; //end nand_clk (nand_clk)
+
+ qspi_clk: qspi_clk {
+ compatible = "altr,socfpga-gate-clk";
+ clocks = <&hps_0_f2s_periph_ref_clk &main_qspi_clk &per_qspi_clk>;
+ clock-names = "hps_0_f2s_periph_ref_clk", "main_qspi_clk", "per_qspi_clk";
+ #clock-cells = <0>;
+ clk-gate = <0x000000a0 0x0000000b>;
+ }; //end qspi_clk (qspi_clk)
+
+ ddr_dqs_clk_gate: ddr_dqs_clk_gate {
+ compatible = "altr,socfpga-gate-clk";
+ clocks = <&ddr_dqs_clk>;
+ #clock-cells = <0>;
+ clk-gate = <0x000000d8 0x00000000>;
+ }; //end ddr_dqs_clk_gate (ddr_dqs_clk_gate)
+
+ ddr_2x_dqs_clk_gate: ddr_2x_dqs_clk_gate {
+ compatible = "altr,socfpga-gate-clk";
+ clocks = <&ddr_2x_dqs_clk>;
+ #clock-cells = <0>;
+ clk-gate = <0x000000d8 0x00000001>;
+ }; //end ddr_2x_dqs_clk_gate (ddr_2x_dqs_clk_gate)
+
+ ddr_dq_clk_gate: ddr_dq_clk_gate {
+ compatible = "altr,socfpga-gate-clk";
+ clocks = <&ddr_dq_clk>;
+ #clock-cells = <0>;
+ clk-gate = <0x000000d8 0x00000002>;
+ }; //end ddr_dq_clk_gate (ddr_dq_clk_gate)
+
+ h2f_user2_clock: h2f_user2_clock {
+ compatible = "altr,socfpga-gate-clk";
+ clocks = <&s2f_usr2_clk>;
+ #clock-cells = <0>;
+ clk-gate = <0x000000d8 0x00000003>;
+ }; //end h2f_user2_clock (h2f_user2_clock)
+
+ l3_main_clk: l3_main_clk {
+ compatible = "altr,socfpga-gate-clk";
+ clocks = <&mainclk>;
+ #clock-cells = <0>;
+ }; //end l3_main_clk (l3_main_clk)
+
+ mpu_periph_clk: mpu_periph_clk {
+ compatible = "altr,socfpga-perip-clk";
+ clocks = <&mpuclk>;
+ #clock-cells = <0>;
+ fixed-divider = <4>;
+ }; //end mpu_periph_clk (mpu_periph_clk)
+ }; //end clock_tree
+ }; //end clkmgr@0xffd04000 (hps_0_clkmgr)
+
+ hps_0_rstmgr: rstmgr@0xffd05000 {
+ compatible = "altr,rst-mgr-15.0", "altr,rst-mgr";
+ reg = <0xffd05000 0x00000100>;
+ #reset-cells = <1>; /* appended from boardinfo */
+ }; //end rstmgr@0xffd05000 (hps_0_rstmgr)
+
+ hps_0_fpgamgr: fpgamgr@0xff706000 {
+ compatible = "altr,fpga-mgr-15.0", "altr,fpga-mgr";
+ reg = <0xff706000 0x00001000>,
+ <0xffb90000 0x00000100>;
+ reg-names = "axi_slave0", "axi_slave1";
+ interrupt-parent = <&hps_0_arm_gic_0>;
+ interrupts = <0 175 4>;
+ transport = "mmio"; /* embeddedsw.dts.params.transport type STRING */
+ }; //end fpgamgr@0xff706000 (hps_0_fpgamgr)
+
+ hps_0_uart0: serial@0xffc02000 {
+ compatible = "snps,dw-apb-uart-15.0", "snps,dw-apb-uart";
+ reg = <0xffc02000 0x00000100>;
+ interrupt-parent = <&hps_0_arm_gic_0>;
+ interrupts = <0 162 4>;
+ clocks = <&l4_sp_clk>;
+ reg-io-width = <4>; /* embeddedsw.dts.params.reg-io-width type NUMBER */
+ reg-shift = <2>; /* embeddedsw.dts.params.reg-shift type NUMBER */
+ status = "okay"; /* embeddedsw.dts.params.status type STRING */
+ }; //end serial@0xffc02000 (hps_0_uart0)
+
+ hps_0_uart1: serial@0xffc03000 {
+ compatible = "snps,dw-apb-uart-15.0", "snps,dw-apb-uart";
+ reg = <0xffc03000 0x00000100>;
+ interrupt-parent = <&hps_0_arm_gic_0>;
+ interrupts = <0 163 4>;
+ clocks = <&l4_sp_clk>;
+ reg-io-width = <4>; /* embeddedsw.dts.params.reg-io-width type NUMBER */
+ reg-shift = <2>; /* embeddedsw.dts.params.reg-shift type NUMBER */
+ status = "disabled"; /* embeddedsw.dts.params.status type STRING */
+ }; //end serial@0xffc03000 (hps_0_uart1)
+
+ hps_0_timer0: timer@0xffc08000 {
+ compatible = "snps,dw-apb-timer-sp-15.0", "snps,dw-apb-timer-sp";
+ reg = <0xffc08000 0x00000100>;
+ interrupt-parent = <&hps_0_arm_gic_0>;
+ interrupts = <0 167 4>;
+ clocks = <&l4_sp_clk>;
+ clock-names = "timer"; /* embeddedsw.dts.params.clock-names type STRING */
+ }; //end timer@0xffc08000 (hps_0_timer0)
+
+ hps_0_timer1: timer@0xffc09000 {
+ compatible = "snps,dw-apb-timer-sp-15.0", "snps,dw-apb-timer-sp";
+ reg = <0xffc09000 0x00000100>;
+ interrupt-parent = <&hps_0_arm_gic_0>;
+ interrupts = <0 168 4>;
+ clocks = <&l4_sp_clk>;
+ clock-names = "timer"; /* embeddedsw.dts.params.clock-names type STRING */
+ }; //end timer@0xffc09000 (hps_0_timer1)
+
+ hps_0_timer2: timer@0xffd00000 {
+ compatible = "snps,dw-apb-timer-osc-15.0", "snps,dw-apb-timer-osc";
+ reg = <0xffd00000 0x00000100>;
+ interrupt-parent = <&hps_0_arm_gic_0>;
+ interrupts = <0 169 4>;
+ clocks = <&hps_0_eosc1>;
+ clock-names = "timer"; /* embeddedsw.dts.params.clock-names type STRING */
+ }; //end timer@0xffd00000 (hps_0_timer2)
+
+ hps_0_timer3: timer@0xffd01000 {
+ compatible = "snps,dw-apb-timer-osc-15.0", "snps,dw-apb-timer-osc";
+ reg = <0xffd01000 0x00000100>;
+ interrupt-parent = <&hps_0_arm_gic_0>;
+ interrupts = <0 170 4>;
+ clocks = <&hps_0_eosc1>;
+ clock-names = "timer"; /* embeddedsw.dts.params.clock-names type STRING */
+ }; //end timer@0xffd01000 (hps_0_timer3)
+
+ hps_0_wd_timer0: timer@0xffd02000 {
+ compatible = "snps,dw-wdt-15.0", "snps,dw-wdt";
+ reg = <0xffd02000 0x00000100>;
+ interrupt-parent = <&hps_0_arm_gic_0>;
+ interrupts = <0 171 4>;
+ clocks = <&hps_0_eosc1>;
+ clock-names = "timer"; /* embeddedsw.dts.params.clock-names type STRING */
+ }; //end timer@0xffd02000 (hps_0_wd_timer0)
+
+ hps_0_wd_timer1: timer@0xffd03000 {
+ compatible = "snps,dw-wdt-15.0", "snps,dw-wdt";
+ reg = <0xffd03000 0x00000100>;
+ interrupt-parent = <&hps_0_arm_gic_0>;
+ interrupts = <0 172 4>;
+ clocks = <&per_base_clk>;
+ clock-names = "timer"; /* embeddedsw.dts.params.clock-names type STRING */
+ status = "disabled"; /* appended from boardinfo */
+ }; //end timer@0xffd03000 (hps_0_wd_timer1)
+
+ hps_0_gpio0: gpio@0xff708000 {
+ compatible = "snps,dw-apb-gpio", "snps,dw-gpio-15.0", "snps,dw-gpio";
+ reg = <0xff708000 0x00000100>;
+ interrupt-parent = <&hps_0_arm_gic_0>;
+ interrupts = <0 164 4>;
+ clocks = <&l4_mp_clk>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ hps_0_gpio0_porta: gpio-controller@0 {
+ compatible = "snps,dw-apb-gpio-port";
+ gpio-controller;
+ #gpio-cells = <2>;
+ snps,nr-gpios = <29>; /* appended from boardinfo */
+ reg = <0>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <0 164 4>;
+ interrupt-parent = <&hps_0_arm_gic_0>;
+ }; //end gpio-controller@0 (hps_0_gpio0_porta)
+ }; //end gpio@0xff708000 (hps_0_gpio0)
+
+ hps_0_gpio1: gpio@0xff709000 {
+ compatible = "snps,dw-apb-gpio", "snps,dw-gpio-15.0", "snps,dw-gpio";
+ reg = <0xff709000 0x00000100>;
+ interrupt-parent = <&hps_0_arm_gic_0>;
+ interrupts = <0 165 4>;
+ clocks = <&l4_mp_clk>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ hps_0_gpio1_porta: gpio-controller@0 {
+ compatible = "snps,dw-apb-gpio-port";
+ gpio-controller;
+ #gpio-cells = <2>;
+ snps,nr-gpios = <29>; /* appended from boardinfo */
+ reg = <0>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <0 165 4>;
+ interrupt-parent = <&hps_0_arm_gic_0>;
+ }; //end gpio-controller@0 (hps_0_gpio1_porta)
+ }; //end gpio@0xff709000 (hps_0_gpio1)
+
+ hps_0_gpio2: gpio@0xff70a000 {
+ compatible = "snps,dw-apb-gpio", "snps,dw-gpio-15.0", "snps,dw-gpio";
+ reg = <0xff70a000 0x00000100>;
+ interrupt-parent = <&hps_0_arm_gic_0>;
+ interrupts = <0 166 4>;
+ clocks = <&l4_mp_clk>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ hps_0_gpio2_porta: gpio-controller@0 {
+ compatible = "snps,dw-apb-gpio-port";
+ gpio-controller;
+ #gpio-cells = <2>;
+ snps,nr-gpios = <27>;
+ reg = <0>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <0 166 4>;
+ interrupt-parent = <&hps_0_arm_gic_0>;
+ }; //end gpio-controller@0 (hps_0_gpio2_porta)
+ }; //end gpio@0xff70a000 (hps_0_gpio2)
+
+ hps_0_i2c0: i2c@0xffc04000 {
+ compatible = "snps,designware-i2c-15.0", "snps,designware-i2c";
+ reg = <0xffc04000 0x00000100>;
+ interrupt-parent = <&hps_0_arm_gic_0>;
+ interrupts = <0 158 4>;
+ clocks = <&l4_sp_clk>;
+ emptyfifo_hold_master = <1>; /* embeddedsw.dts.params.emptyfifo_hold_master type NUMBER */
+ status = "okay"; /* embeddedsw.dts.params.status type STRING */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ speed-mode = <0>; /* appended from boardinfo */
+ i2c-sda-falling-time-ns = <5000>; /* appended from boardinfo */
+ i2c-scl-falling-time-ns = <5000>; /* appended from boardinfo */
+
+ lcd: newhaven,nhd-0216k3z-nsw-bbw@0x28 {
+ compatible = "newhaven,nhd-0216k3z-nsw-bbw";
+ reg = <0x00000028>;
+ height = <2>; /* appended from boardinfo */
+ width = <16>; /* appended from boardinfo */
+ brightness = <8>; /* appended from boardinfo */
+ }; //end newhaven,nhd-0216k3z-nsw-bbw@0x28 (lcd)
+
+ eeprom: atmel,24c32@0x51 {
+ compatible = "atmel,24c32";
+ reg = <0x00000051>;
+ pagesize = <32>; /* appended from boardinfo */
+ }; //end atmel,24c32@0x51 (eeprom)
+
+ rtc: dallas,ds1339@0x68 {
+ compatible = "dallas,ds1339";
+ reg = <0x00000068>;
+ }; //end dallas,ds1339@0x68 (rtc)
+ }; //end i2c@0xffc04000 (hps_0_i2c0)
+
+ hps_0_i2c1: i2c@0xffc05000 {
+ compatible = "snps,designware-i2c-15.0", "snps,designware-i2c";
+ reg = <0xffc05000 0x00000100>;
+ interrupt-parent = <&hps_0_arm_gic_0>;
+ interrupts = <0 159 4>;
+ clocks = <&l4_sp_clk>;
+ emptyfifo_hold_master = <1>; /* embeddedsw.dts.params.emptyfifo_hold_master type NUMBER */
+ status = "disabled"; /* embeddedsw.dts.params.status type STRING */
+ }; //end i2c@0xffc05000 (hps_0_i2c1)
+
+ hps_0_i2c2: i2c@0xffc06000 {
+ compatible = "snps,designware-i2c-15.0", "snps,designware-i2c";
+ reg = <0xffc06000 0x00000100>;
+ interrupt-parent = <&hps_0_arm_gic_0>;
+ interrupts = <0 160 4>;
+ clocks = <&l4_sp_clk>;
+ emptyfifo_hold_master = <1>; /* embeddedsw.dts.params.emptyfifo_hold_master type NUMBER */
+ status = "disabled"; /* embeddedsw.dts.params.status type STRING */
+ }; //end i2c@0xffc06000 (hps_0_i2c2)
+
+ hps_0_i2c3: i2c@0xffc07000 {
+ compatible = "snps,designware-i2c-15.0", "snps,designware-i2c";
+ reg = <0xffc07000 0x00000100>;
+ interrupt-parent = <&hps_0_arm_gic_0>;
+ interrupts = <0 161 4>;
+ emptyfifo_hold_master = <1>; /* embeddedsw.dts.params.emptyfifo_hold_master type NUMBER */
+ status = "disabled"; /* embeddedsw.dts.params.status type STRING */
+ }; //end i2c@0xffc07000 (hps_0_i2c3)
+
+ hps_0_nand0: flash@0xff900000 {
+ compatible = "denali,nand-15.0", "denali,denali-nand-dt";
+ reg = <0xff900000 0x00010000>,
+ <0xffb80000 0x00010000>;
+ reg-names = "nand_data", "denali_reg"; /* embeddedsw.dts.params.reg-names type STRING */
+ interrupt-parent = <&hps_0_arm_gic_0>;
+ interrupts = <0 144 4>;
+ clocks = <&nand_clk>;
+ #address-cells = <1>; /* embeddedsw.dts.params.#address-cells type NUMBER */
+ #size-cells = <1>; /* embeddedsw.dts.params.#size-cells type NUMBER */
+ status = "disabled"; /* embeddedsw.dts.params.status type STRING */
+ bank-width = <2>;
+ device-width = <1>;
+ }; //end flash@0xff900000 (hps_0_nand0)
+
+ hps_0_spim0: spi@0xfff00000 {
+ compatible = "snps,dw-spi-mmio-15.0", "snps,dw-spi-mmio";
+ reg = <0xfff00000 0x00000100>;
+ interrupt-parent = <&hps_0_arm_gic_0>;
+ interrupts = <0 154 4>;
+ clocks = <&spi_m_clk>;
+ #address-cells = <1>; /* embeddedsw.dts.params.#address-cells type NUMBER */
+ #size-cells = <0>; /* embeddedsw.dts.params.#size-cells type NUMBER */
+ bus-num = <0>; /* embeddedsw.dts.params.bus-num type NUMBER */
+ num-chipselect = <4>; /* embeddedsw.dts.params.num-chipselect type NUMBER */
+ status = "disabled"; /* embeddedsw.dts.params.status type STRING */
+
+ spidev0: spidev@0 {
+ compatible = "spidev"; /* appended from boardinfo */
+ reg = <0>; /* appended from boardinfo */
+ spi-max-frequency = <100000000>; /* appended from boardinfo */
+ enable-dma = <1>; /* appended from boardinfo */
+ }; //end spidev@0 (spidev0)
+ }; //end spi@0xfff00000 (hps_0_spim0)
+
+ hps_0_spim1: spi@0xfff01000 {
+ compatible = "snps,dw-spi-mmio-15.0", "snps,dw-spi-mmio";
+ reg = <0xfff01000 0x00000100>;
+ interrupt-parent = <&hps_0_arm_gic_0>;
+ interrupts = <0 155 4>;
+ clocks = <&spi_m_clk>;
+ #address-cells = <1>; /* embeddedsw.dts.params.#address-cells type NUMBER */
+ #size-cells = <0>; /* embeddedsw.dts.params.#size-cells type NUMBER */
+ bus-num = <0>; /* embeddedsw.dts.params.bus-num type NUMBER */
+ num-chipselect = <4>; /* embeddedsw.dts.params.num-chipselect type NUMBER */
+ status = "disabled"; /* embeddedsw.dts.params.status type STRING */
+
+ spidev1: spidev@0 {
+ compatible = "spidev"; /* appended from boardinfo */
+ reg = <0>; /* appended from boardinfo */
+ spi-max-frequency = <100000000>; /* appended from boardinfo */
+ enable-dma = <1>; /* appended from boardinfo */
+ }; //end spidev@0 (spidev1)
+ }; //end spi@0xfff01000 (hps_0_spim1)
+
+ hps_0_qspi: flash@0xff705000 {
+ compatible = "cadence,qspi-15.0", "cadence,qspi";
+ reg = <0xff705000 0x00000100>,
+ <0xffa00000 0x00000100>;
+ reg-names = "axi_slave0", "axi_slave1";
+ interrupt-parent = <&hps_0_arm_gic_0>;
+ interrupts = <0 151 4>;
+ clocks = <&qspi_clk>;
+ bus-num = <2>; /* embeddedsw.dts.params.bus-num type NUMBER */
+ fifo-depth = <128>; /* embeddedsw.dts.params.fifo-depth type NUMBER */
+ num-chipselect = <4>; /* embeddedsw.dts.params.num-chipselect type NUMBER */
+ status = "disabled"; /* embeddedsw.dts.params.status type STRING */
+ bank-width = <2>;
+ device-width = <1>;
+ #address-cells = <1>; /* appended from boardinfo */
+ #size-cells = <0>; /* appended from boardinfo */
+ master-ref-clk = <400000000>; /* appended from boardinfo */
+ ext-decoder = <0>; /* appended from boardinfo */
+
+ flash0: n25q00@0 {
+ compatible = "n25q00"; /* appended from boardinfo */
+ #address-cells = <1>; /* appended from boardinfo */
+ #size-cells = <1>; /* appended from boardinfo */
+ reg = <0>; /* appended from boardinfo */
+ spi-max-frequency = <100000000>; /* appended from boardinfo */
+ page-size = <256>; /* appended from boardinfo */
+ block-size = <16>; /* appended from boardinfo */
+ m25p,fast-read; /* appended from boardinfo */
+ read-delay = <4>; /* appended from boardinfo */
+ tshsl-ns = <50>; /* appended from boardinfo */
+ tsd2d-ns = <50>; /* appended from boardinfo */
+ tchsh-ns = <4>; /* appended from boardinfo */
+ tslch-ns = <4>; /* appended from boardinfo */
+
+ part0: partition@0 {
+ label = "Flash 0 Raw Data"; /* appended from boardinfo */
+ reg = <0x00000000 0x00800000>; /* appended from boardinfo */
+ }; //end partition@0 (part0)
+
+ part1: partition@800000 {
+ label = "Flash 1 jffs2 Filesystem"; /* appended from boardinfo */
+ reg = <0x00800000 0x07800000>; /* appended from boardinfo */
+ }; //end partition@800000 (part1)
+ }; //end n25q00@0 (flash0)
+ }; //end flash@0xff705000 (hps_0_qspi)
+
+ hps_0_sdmmc: flash@0xff704000 {
+ compatible = "altr,socfpga-dw-mshc"; /* appended from boardinfo */
+ reg = <0xff704000 0x00001000>;
+ interrupt-parent = <&hps_0_arm_gic_0>;
+ interrupts = <0 139 4>;
+ clocks = <&l4_mp_clk &sdmmc_clk>;
+ clock-names = "biu", "ciu";
+ fifo-depth = <1024>; /* embeddedsw.dts.params.fifo-depth type NUMBER */
+ num-slots = <1>; /* embeddedsw.dts.params.num-slots type NUMBER */
+ status = "okay"; /* embeddedsw.dts.params.status type STRING */
+ bank-width = <2>;
+ device-width = <1>;
+ #address-cells = <1>; /* appended from boardinfo */
+ #size-cells = <0>; /* appended from boardinfo */
+ supports-highspeed; /* appended from boardinfo */
+ broken-cd; /* appended from boardinfo */
+ altr,dw-mshc-ciu-div = <3>; /* appended from boardinfo */
+ altr,dw-mshc-sdr-timing = <0 3>; /* appended from boardinfo */
+
+ slot_0: slot@0 {
+ reg = <0>; /* appended from boardinfo */
+ bus-width = <4>; /* appended from boardinfo */
+ }; //end slot@0 (slot_0)
+ }; //end flash@0xff704000 (hps_0_sdmmc)
+
+ hps_0_usb0: usb@0xffb00000 {
+ compatible = "snps,dwc-otg-15.0", "snps,dwc-otg", "snps,dwc2";
+ reg = <0xffb00000 0x00040000>;
+ interrupt-parent = <&hps_0_arm_gic_0>;
+ interrupts = <0 125 4>;
+ clocks = <&usb_mp_clk>;
+ clock-names = "otg"; /* embeddedsw.dts.params.clock-names type STRING */
+ dev-nperio-tx-fifo-size = <4096>; /* embeddedsw.dts.params.dev-nperio-tx-fifo-size type NUMBER */
+ dev-perio-tx-fifo-size = "<512 512 512 512 512 512 512 512 512 512 512 512 512 512 512>"; /* embeddedsw.dts.params.dev-perio-tx-fifo-size type STRING */
+ dev-rx-fifo-size = <512>; /* embeddedsw.dts.params.dev-rx-fifo-size type NUMBER */
+ dev-tx-fifo-size = "<512 512 512 512 512 512 512 512 512 512 512 512 512 512 512>"; /* embeddedsw.dts.params.dev-tx-fifo-size type STRING */
+ dma-mask = <268435455>; /* embeddedsw.dts.params.dma-mask type NUMBER */
+ enable-dynamic-fifo = <1>; /* embeddedsw.dts.params.enable-dynamic-fifo type NUMBER */
+ host-nperio-tx-fifo-size = <2560>; /* embeddedsw.dts.params.host-nperio-tx-fifo-size type NUMBER */
+ host-perio-tx-fifo-size = <2560>; /* embeddedsw.dts.params.host-perio-tx-fifo-size type NUMBER */
+ host-rx-fifo-size = <2560>; /* embeddedsw.dts.params.host-rx-fifo-size type NUMBER */
+ phy-names = "usb2-phy"; /* embeddedsw.dts.params.phy-names type STRING */
+ status = "disabled"; /* embeddedsw.dts.params.status type STRING */
+ ulpi-ddr = <0>; /* embeddedsw.dts.params.ulpi-ddr type NUMBER */
+ voltage-switch = <0>; /* embeddedsw.dts.params.voltage-switch type NUMBER */
+ }; //end usb@0xffb00000 (hps_0_usb0)
+
+ hps_0_usb1: usb@0xffb40000 {
+ compatible = "snps,dwc-otg-15.0", "snps,dwc-otg", "snps,dwc2";
+ reg = <0xffb40000 0x00040000>;
+ interrupt-parent = <&hps_0_arm_gic_0>;
+ interrupts = <0 128 4>;
+ clocks = <&usb_mp_clk>;
+ clock-names = "otg"; /* embeddedsw.dts.params.clock-names type STRING */
+ dev-nperio-tx-fifo-size = <4096>; /* embeddedsw.dts.params.dev-nperio-tx-fifo-size type NUMBER */
+ dev-perio-tx-fifo-size = "<512 512 512 512 512 512 512 512 512 512 512 512 512 512 512>"; /* embeddedsw.dts.params.dev-perio-tx-fifo-size type STRING */
+ dev-rx-fifo-size = <512>; /* embeddedsw.dts.params.dev-rx-fifo-size type NUMBER */
+ dev-tx-fifo-size = "<512 512 512 512 512 512 512 512 512 512 512 512 512 512 512>"; /* embeddedsw.dts.params.dev-tx-fifo-size type STRING */
+ dma-mask = <268435455>; /* embeddedsw.dts.params.dma-mask type NUMBER */
+ enable-dynamic-fifo = <1>; /* embeddedsw.dts.params.enable-dynamic-fifo type NUMBER */
+ host-nperio-tx-fifo-size = <2560>; /* embeddedsw.dts.params.host-nperio-tx-fifo-size type NUMBER */
+ host-perio-tx-fifo-size = <2560>; /* embeddedsw.dts.params.host-perio-tx-fifo-size type NUMBER */
+ host-rx-fifo-size = <2560>; /* embeddedsw.dts.params.host-rx-fifo-size type NUMBER */
+ phy-names = "usb2-phy"; /* embeddedsw.dts.params.phy-names type STRING */
+ status = "disabled"; /* embeddedsw.dts.params.status type STRING */
+ ulpi-ddr = <0>; /* embeddedsw.dts.params.ulpi-ddr type NUMBER */
+ voltage-switch = <0>; /* embeddedsw.dts.params.voltage-switch type NUMBER */
+ phys = <&usbphy0>; /* appended from boardinfo */
+ }; //end usb@0xffb40000 (hps_0_usb1)
+
+ hps_0_gmac0: ethernet@0xff700000 {
+ compatible = "synopsys,dwmac-15.0", "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
+ reg = <0xff700000 0x00002000>;
+ interrupt-parent = <&hps_0_arm_gic_0>;
+ interrupts = <0 115 4>;
+ clocks = <&emac0_clk>;
+ clock-names = "stmmaceth"; /* embeddedsw.dts.params.clock-names type STRING */
+ interrupt-names = "macirq"; /* embeddedsw.dts.params.interrupt-names type STRING */
+ mac-address = "[00 00 00 00 00 00]"; /* embeddedsw.dts.params.mac-address type STRING */
+ snps,multicast-filter-bins = <256>; /* embeddedsw.dts.params.snps,multicast-filter-bins type NUMBER */
+ snps,perfect-filter-entries = <128>; /* embeddedsw.dts.params.snps,perfect-filter-entries type NUMBER */
+ status = "disabled"; /* embeddedsw.dts.params.status type STRING */
+ address-bits = <48>;
+ max-frame-size = <1518>;
+ local-mac-address = [00 00 00 00 00 00];
+ reset-names = "stmmaceth"; /* appended from boardinfo */
+ resets = <&hps_0_rstmgr 32>; /* appended from boardinfo */
+ }; //end ethernet@0xff700000 (hps_0_gmac0)
+
+ hps_0_gmac1: ethernet@0xff702000 {
+ compatible = "synopsys,dwmac-15.0", "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
+ reg = <0xff702000 0x00002000>;
+ interrupt-parent = <&hps_0_arm_gic_0>;
+ interrupts = <0 120 4>;
+ clocks = <&emac1_clk>;
+ clock-names = "stmmaceth"; /* embeddedsw.dts.params.clock-names type STRING */
+ interrupt-names = "macirq"; /* embeddedsw.dts.params.interrupt-names type STRING */
+ mac-address = "[00 00 00 00 00 00]"; /* embeddedsw.dts.params.mac-address type STRING */
+ snps,multicast-filter-bins = <256>; /* embeddedsw.dts.params.snps,multicast-filter-bins type NUMBER */
+ snps,perfect-filter-entries = <128>; /* embeddedsw.dts.params.snps,perfect-filter-entries type NUMBER */
+ status = "okay"; /* embeddedsw.dts.params.status type STRING */
+ address-bits = <48>;
+ max-frame-size = <3800>; /* appended from boardinfo */
+ local-mac-address = [00 00 00 00 00 00];
+ phy-mode = "rgmii"; /* appended from boardinfo */
+ snps,phy-addr = <0xffffffff>; /* appended from boardinfo */
+ phy-addr = <0xffffffff>; /* appended from boardinfo */
+ txc-skew-ps = <3000>; /* appended from boardinfo */
+ rxc-skew-ps = <3000>; /* appended from boardinfo */
+ txen-skew-ps = <0>; /* appended from boardinfo */
+ rxdv-skew-ps = <0>; /* appended from boardinfo */
+ rxd0-skew-ps = <0>; /* appended from boardinfo */
+ rxd1-skew-ps = <0>; /* appended from boardinfo */
+ rxd2-skew-ps = <0>; /* appended from boardinfo */
+ rxd3-skew-ps = <0>; /* appended from boardinfo */
+ txd0-skew-ps = <0>; /* appended from boardinfo */
+ txd1-skew-ps = <0>; /* appended from boardinfo */
+ txd2-skew-ps = <0>; /* appended from boardinfo */
+ txd3-skew-ps = <0>; /* appended from boardinfo */
+ altr,sysmgr-syscon = <&hps_0_sysmgr 0x00000060 2>; /* appended from boardinfo */
+ reset-names = "stmmaceth"; /* appended from boardinfo */
+ resets = <&hps_0_rstmgr 33>; /* appended from boardinfo */
+ }; //end ethernet@0xff702000 (hps_0_gmac1)
+
+ hps_0_dcan0: can@0xffc00000 {
+ compatible = "bosch,dcan-15.0", "bosch,d_can";
+ reg = <0xffc00000 0x00001000>;
+ interrupt-parent = <&hps_0_arm_gic_0>;
+ interrupts = <0 131 4 0 132 4>;
+ interrupt-names = "interrupt_sender0", "interrupt_sender1";
+ clocks = <&can0_clk>;
+ status = "disabled"; /* embeddedsw.dts.params.status type STRING */
+ }; //end can@0xffc00000 (hps_0_dcan0)
+
+ hps_0_dcan1: can@0xffc01000 {
+ compatible = "bosch,dcan-15.0", "bosch,d_can";
+ reg = <0xffc01000 0x00001000>;
+ interrupt-parent = <&hps_0_arm_gic_0>;
+ interrupts = <0 135 4 0 136 4>;
+ interrupt-names = "interrupt_sender0", "interrupt_sender1";
+ clocks = <&can1_clk>;
+ status = "disabled"; /* embeddedsw.dts.params.status type STRING */
+ }; //end can@0xffc01000 (hps_0_dcan1)
+
+ hps_0_l3regs: rl3regs@0xff800000 {
+ compatible = "altr,l3regs-15.0", "altr,l3regs", "syscon";
+ reg = <0xff800000 0x00001000>;
+ }; //end rl3regs@0xff800000 (hps_0_l3regs)
+
+ hps_0_sdrctl: sdr-ctl@0xffc25000 {
+ compatible = "altr,sdr-ctl-15.0", "altr,sdr-ctl", "syscon";
+ reg = <0xffc25000 0x00001000>;
+ }; //end sdr-ctl@0xffc25000 (hps_0_sdrctl)
+
+ hps_0_timer: timer@0xfffec600 {
+ compatible = "arm,cortex-a9-twd-timer-15.0", "arm,cortex-a9-twd-timer";
+ reg = <0xfffec600 0x00000100>;
+ interrupt-parent = <&hps_0_arm_gic_0>;
+ interrupts = <1 13 3844>;
+ clocks = <&mpu_periph_clk>;
+ }; //end timer@0xfffec600 (hps_0_timer)
+
+ soc_leds: leds {
+ compatible = "gpio-leds"; /* appended from boardinfo */
+
+ led_hps0: hps0 {
+ label = "hps_led0"; /* appended from boardinfo */
+ gpios = <&hps_0_gpio1_porta 15 1>; /* appended from boardinfo */
+ }; //end hps0 (led_hps0)
+
+ led_hps1: hps1 {
+ label = "hps_led1"; /* appended from boardinfo */
+ gpios = <&hps_0_gpio1_porta 14 1>; /* appended from boardinfo */
+ }; //end hps1 (led_hps1)
+
+ led_hps2: hps2 {
+ label = "hps_led2"; /* appended from boardinfo */
+ gpios = <&hps_0_gpio1_porta 13 1>; /* appended from boardinfo */
+ }; //end hps2 (led_hps2)
+
+ led_hps3: hps3 {
+ label = "hps_led3"; /* appended from boardinfo */
+ gpios = <&hps_0_gpio1_porta 12 1>; /* appended from boardinfo */
+ }; //end hps3 (led_hps3)
+
+ led_fpga0: fpga0 {
+ label = "fpga_led0"; /* appended from boardinfo */
+ gpios = <&led_pio 0 1>; /* appended from boardinfo */
+ }; //end fpga0 (led_fpga0)
+
+ led_fpga1: fpga1 {
+ label = "fpga_led1"; /* appended from boardinfo */
+ gpios = <&led_pio 1 1>; /* appended from boardinfo */
+ }; //end fpga1 (led_fpga1)
+
+ led_fpga2: fpga2 {
+ label = "fpga_led2"; /* appended from boardinfo */
+ gpios = <&led_pio 2 1>; /* appended from boardinfo */
+ }; //end fpga2 (led_fpga2)
+
+ led_fpga3: fpga3 {
+ label = "fpga_led3"; /* appended from boardinfo */
+ gpios = <&led_pio 3 1>; /* appended from boardinfo */
+ }; //end fpga3 (led_fpga3)
+ }; //end leds (soc_leds)
+
+ pmu: pmu0 {
+ #address-cells = <1>; /* appended from boardinfo */
+ #size-cells = <1>; /* appended from boardinfo */
+ compatible = "arm,cortex-a9-pmu"; /* appended from boardinfo */
+ interrupt-parent = <&hps_0_arm_gic_0>; /* appended from boardinfo */
+ interrupts = <0 176 4 0 177 4>; /* appended from boardinfo */
+ ranges; /* appended from boardinfo */
+
+ cti0: cti0@ff118000 {
+ compatible = "arm,coresight-cti"; /* appended from boardinfo */
+ reg = <0xff118000 0x00001000>; /* appended from boardinfo */
+ }; //end cti0@ff118000 (cti0)
+
+ cti1: cti0@ff119000 {
+ compatible = "arm,coresight-cti"; /* appended from boardinfo */
+ reg = <0xff119000 0x00001000>; /* appended from boardinfo */
+ }; //end cti0@ff119000 (cti1)
+ }; //end pmu0 (pmu)
+
+ fpgabridge0: fpgabridge@0 {
+ compatible = "altr,socfpga-hps2fpga-bridge"; /* appended from boardinfo */
+ label = "hps2fpga"; /* appended from boardinfo */
+ reset-names = "hps2fpga"; /* appended from boardinfo */
+ clocks = <&l4_main_clk>; /* appended from boardinfo */
+ resets = <&hps_0_rstmgr 96>; /* appended from boardinfo */
+ }; //end fpgabridge@0 (fpgabridge0)
+
+ fpgabridge1: fpgabridge@1 {
+ compatible = "altr,socfpga-lwhps2fpga-bridge"; /* appended from boardinfo */
+ label = "lwhps2fpga"; /* appended from boardinfo */
+ reset-names = "lwhps2fpga"; /* appended from boardinfo */
+ clocks = <&l4_main_clk>; /* appended from boardinfo */
+ resets = <&hps_0_rstmgr 97>; /* appended from boardinfo */
+ }; //end fpgabridge@1 (fpgabridge1)
+
+ fpgabridge2: fpgabridge@2 {
+ compatible = "altr,socfpga-fpga2hps-bridge"; /* appended from boardinfo */
+ label = "fpga2hps"; /* appended from boardinfo */
+ reset-names = "fpga2hps"; /* appended from boardinfo */
+ clocks = <&l4_main_clk>; /* appended from boardinfo */
+ resets = <&hps_0_rstmgr 98>; /* appended from boardinfo */
+ }; //end fpgabridge@2 (fpgabridge2)
+
+ usbphy0: usbphy@0 {
+ #phy-cells = <0>; /* appended from boardinfo */
+ compatible = "usb-nop-xceiv"; /* appended from boardinfo */
+ status = "okay"; /* appended from boardinfo */
+ }; //end usbphy@0 (usbphy0)
+ }; //end sopc@0 (sopc0)
+
+ chosen {
+ bootargs = "console=ttyS0,115200";
+ }; //end chosen
+}; //end /