diff options
Diffstat (limited to 'altera-socfpga/hardware-handoff/spl_bsp/settings.bsp')
| -rw-r--r-- | altera-socfpga/hardware-handoff/spl_bsp/settings.bsp | 555 |
1 files changed, 555 insertions, 0 deletions
diff --git a/altera-socfpga/hardware-handoff/spl_bsp/settings.bsp b/altera-socfpga/hardware-handoff/spl_bsp/settings.bsp new file mode 100644 index 0000000..411e42b --- /dev/null +++ b/altera-socfpga/hardware-handoff/spl_bsp/settings.bsp @@ -0,0 +1,555 @@ +<?xml version="1.0" encoding="UTF-8"?> +<sch:Settings xmlns:sch="http://www.altera.com/embeddedsw/bsp/schema"> + <BspType>spl</BspType> + <BspVersion>default</BspVersion> + <BspGeneratedTimeStamp>May 26, 2015 2:15:07 PM</BspGeneratedTimeStamp> + <BspGeneratedUnixTimeStamp>1432646107141</BspGeneratedUnixTimeStamp> + <BspGeneratedLocation>./</BspGeneratedLocation> + <BspSettingsFile>/home/ed/socfpga-devkit-demo/software/spl_bsp/settings.bsp</BspSettingsFile> + <HpsSettingsPath>../../hps_isw_handoff/hps_hps_0</HpsSettingsPath> + <JdiFile>default</JdiFile> + <Cpu xsi:nil="true" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"/> + <SchemaVersion>1.9</SchemaVersion> + <Setting> + <SettingName>spl.PRELOADER_TGZ</SettingName> + <Identifier>none</Identifier> + <Type>UnquotedString</Type> + <Value>$(SOCEDS_DEST_ROOT)/host_tools/altera/preloader/uboot-socfpga.tar.gz</Value> + <DefaultValue>$(SOCEDS_DEST_ROOT)/host_tools/altera/preloader/uboot-socfpga.tar.gz</DefaultValue> + <DestinationFile>public_mk_define</DestinationFile> + <Description>Path to gzip compressed tar archive file which contains Preloader source files.</Description> + <Restrictions>none</Restrictions> + <Enabled>false</Enabled> + <Group>common</Group> + </Setting> + <Setting> + <SettingName>spl.CROSS_COMPILE</SettingName> + <Identifier>none</Identifier> + <Type>UnquotedString</Type> + <Value>arm-altera-eabi-</Value> + <DefaultValue>arm-altera-eabi-</DefaultValue> + <DestinationFile>public_mk_define</DestinationFile> + <Description>Target triplet of the cross toolchain to use.</Description> + <Restrictions>none</Restrictions> + <Enabled>false</Enabled> + <Group>common</Group> + </Setting> + <Setting> + <SettingName>spl.reset_assert.L4WD1</SettingName> + <Identifier>none</Identifier> + <Type>Boolean</Type> + <Value>0</Value> + <DefaultValue>0</DefaultValue> + <DestinationFile>public_mk_define</DestinationFile> + <Description>When enabled, the device will remain in reset state, and registers for this device should not be read.</Description> + <Restrictions>none</Restrictions> + <Enabled>false</Enabled> + <Group/> + </Setting> + <Setting> + <SettingName>spl.reset_assert.OSC1TIMER1</SettingName> + <Identifier>none</Identifier> + <Type>Boolean</Type> + <Value>0</Value> + <DefaultValue>0</DefaultValue> + <DestinationFile>public_mk_define</DestinationFile> + <Description>When enabled, the device will remain in reset state, and registers for this device should not be read.</Description> + <Restrictions>none</Restrictions> + <Enabled>false</Enabled> + <Group/> + </Setting> + <Setting> + <SettingName>spl.reset_assert.SPTIMER0</SettingName> + <Identifier>none</Identifier> + <Type>Boolean</Type> + <Value>0</Value> + <DefaultValue>0</DefaultValue> + <DestinationFile>public_mk_define</DestinationFile> + <Description>When enabled, the device will remain in reset state, and registers for this device should not be read.</Description> + <Restrictions>none</Restrictions> + <Enabled>false</Enabled> + <Group/> + </Setting> + <Setting> + <SettingName>spl.reset_assert.SPTIMER1</SettingName> + <Identifier>none</Identifier> + <Type>Boolean</Type> + <Value>0</Value> + <DefaultValue>0</DefaultValue> + <DestinationFile>public_mk_define</DestinationFile> + <Description>When enabled, the device will remain in reset state, and registers for this device should not be read.</Description> + <Restrictions>none</Restrictions> + <Enabled>false</Enabled> + <Group/> + </Setting> + <Setting> + <SettingName>spl.reset_assert.GPIO0</SettingName> + <Identifier>none</Identifier> + <Type>Boolean</Type> + <Value>0</Value> + <DefaultValue>0</DefaultValue> + <DestinationFile>public_mk_define</DestinationFile> + <Description>When enabled, the device will remain in reset state, and registers for this device should not be read.</Description> + <Restrictions>none</Restrictions> + <Enabled>false</Enabled> + <Group/> + </Setting> + <Setting> + <SettingName>spl.reset_assert.GPIO1</SettingName> + <Identifier>none</Identifier> + <Type>Boolean</Type> + <Value>0</Value> + <DefaultValue>0</DefaultValue> + <DestinationFile>public_mk_define</DestinationFile> + <Description>When enabled, the device will remain in reset state, and registers for this device should not be read.</Description> + <Restrictions>none</Restrictions> + <Enabled>false</Enabled> + <Group/> + </Setting> + <Setting> + <SettingName>spl.reset_assert.GPIO2</SettingName> + <Identifier>none</Identifier> + <Type>Boolean</Type> + <Value>0</Value> + <DefaultValue>0</DefaultValue> + <DestinationFile>public_mk_define</DestinationFile> + <Description>When enabled, the device will remain in reset state, and registers for this device should not be read.</Description> + <Restrictions>none</Restrictions> + <Enabled>false</Enabled> + <Group/> + </Setting> + <Setting> + <SettingName>spl.reset_assert.DMA</SettingName> + <Identifier>none</Identifier> + <Type>Boolean</Type> + <Value>0</Value> + <DefaultValue>0</DefaultValue> + <DestinationFile>public_mk_define</DestinationFile> + <Description>When enabled, the device will remain in reset state, and registers for this device should not be read.</Description> + <Restrictions>none</Restrictions> + <Enabled>false</Enabled> + <Group/> + </Setting> + <Setting> + <SettingName>spl.reset_assert.SDR</SettingName> + <Identifier>none</Identifier> + <Type>Boolean</Type> + <Value>0</Value> + <DefaultValue>0</DefaultValue> + <DestinationFile>public_mk_define</DestinationFile> + <Description>When enabled, the device will remain in reset state, and registers for this device should not be read.</Description> + <Restrictions>none</Restrictions> + <Enabled>false</Enabled> + <Group/> + </Setting> + <Setting> + <SettingName>spl.warm_reset_handshake.FPGA</SettingName> + <Identifier>none</Identifier> + <Type>Boolean</Type> + <Value>1</Value> + <DefaultValue>1</DefaultValue> + <DestinationFile>public_mk_define</DestinationFile> + <Description>When enabled, Reset Manager will perform handshake with FPGA before asserting warm reset.</Description> + <Restrictions>none</Restrictions> + <Enabled>false</Enabled> + <Group/> + </Setting> + <Setting> + <SettingName>spl.warm_reset_handshake.ETR</SettingName> + <Identifier>none</Identifier> + <Type>Boolean</Type> + <Value>1</Value> + <DefaultValue>1</DefaultValue> + <DestinationFile>public_mk_define</DestinationFile> + <Description>When enabled, Reset Manager makes a request to the ETR to stall its AXI master and waits for it to finish any outstanding AXI transactions before a warm reset of the L3 Interconnect or a debug reset of the ETR. This stalling is required because the debug logic (including the ETR) is reset on a debug reset and the ETR AXI master is connected to the L3 Interconnect which is reset on a warm reset and these resets can happen independently.</Description> + <Restrictions>none</Restrictions> + <Enabled>false</Enabled> + <Group/> + </Setting> + <Setting> + <SettingName>spl.warm_reset_handshake.SDRAM</SettingName> + <Identifier>none</Identifier> + <Type>Boolean</Type> + <Value>0</Value> + <DefaultValue>0</DefaultValue> + <DestinationFile>public_mk_define</DestinationFile> + <Description>When enabled, Reset Manager makes a request to the SDRAM controller subsystem to put the SDRAM device into self-refresh mode before asserting warm reset signals. It will ensure the contents of SDRAM devices survive a hardware sequenced warm reset. However, if SDRAM is already in warm reset, handshake with SDRAM is not performed.</Description> + <Restrictions>none</Restrictions> + <Enabled>false</Enabled> + <Group/> + </Setting> + <Setting> + <SettingName>spl.boot.BOOT_FROM_QSPI</SettingName> + <Identifier>none</Identifier> + <Type>Boolean</Type> + <Value>0</Value> + <DefaultValue>0</DefaultValue> + <DestinationFile>public_mk_define</DestinationFile> + <Description>Load subsequent boot image from QSPI.</Description> + <Restrictions>none</Restrictions> + <Enabled>false</Enabled> + <Group>common</Group> + </Setting> + <Setting> + <SettingName>spl.boot.BOOT_FROM_SDMMC</SettingName> + <Identifier>none</Identifier> + <Type>Boolean</Type> + <Value>1</Value> + <DefaultValue>1</DefaultValue> + <DestinationFile>public_mk_define</DestinationFile> + <Description>Load subsequent boot image from SDMMC.</Description> + <Restrictions>none</Restrictions> + <Enabled>false</Enabled> + <Group>common</Group> + </Setting> + <Setting> + <SettingName>spl.boot.BOOT_FROM_NAND</SettingName> + <Identifier>none</Identifier> + <Type>Boolean</Type> + <Value>0</Value> + <DefaultValue>0</DefaultValue> + <DestinationFile>public_mk_define</DestinationFile> + <Description>Load subsequent boot image from NAND.</Description> + <Restrictions>none</Restrictions> + <Enabled>false</Enabled> + <Group>common</Group> + </Setting> + <Setting> + <SettingName>spl.boot.BOOT_FROM_RAM</SettingName> + <Identifier>none</Identifier> + <Type>Boolean</Type> + <Value>0</Value> + <DefaultValue>0</DefaultValue> + <DestinationFile>public_mk_define</DestinationFile> + <Description>Load subsequent boot image from RAM.</Description> + <Restrictions>none</Restrictions> + <Enabled>false</Enabled> + <Group>common</Group> + </Setting> + <Setting> + <SettingName>spl.boot.QSPI_NEXT_BOOT_IMAGE</SettingName> + <Identifier>none</Identifier> + <Type>HexNumber</Type> + <Value>0x60000</Value> + <DefaultValue>0x60000</DefaultValue> + <DestinationFile>public_mk_define</DestinationFile> + <Description>Location of subsequent boot image in QSPI.</Description> + <Restrictions>none</Restrictions> + <Enabled>false</Enabled> + <Group>common</Group> + </Setting> + <Setting> + <SettingName>spl.boot.SDMMC_NEXT_BOOT_IMAGE</SettingName> + <Identifier>none</Identifier> + <Type>HexNumber</Type> + <Value>0x40000</Value> + <DefaultValue>0x40000</DefaultValue> + <DestinationFile>public_mk_define</DestinationFile> + <Description>Location of subsequent boot image in SDMMC.</Description> + <Restrictions>none</Restrictions> + <Enabled>false</Enabled> + <Group>common</Group> + </Setting> + <Setting> + <SettingName>spl.boot.NAND_NEXT_BOOT_IMAGE</SettingName> + <Identifier>none</Identifier> + <Type>HexNumber</Type> + <Value>0xc0000</Value> + <DefaultValue>0xC0000</DefaultValue> + <DestinationFile>public_mk_define</DestinationFile> + <Description>Location of subsequent boot image in NAND.</Description> + <Restrictions>none</Restrictions> + <Enabled>false</Enabled> + <Group>common</Group> + </Setting> + <Setting> + <SettingName>spl.boot.FAT_SUPPORT</SettingName> + <Identifier>none</Identifier> + <Type>Boolean</Type> + <Value>0</Value> + <DefaultValue>0</DefaultValue> + <DestinationFile>public_mk_define</DestinationFile> + <Description>Enable FAT partition support when booting from SDMMC.</Description> + <Restrictions>none</Restrictions> + <Enabled>false</Enabled> + <Group>common</Group> + </Setting> + <Setting> + <SettingName>spl.boot.FAT_BOOT_PARTITION</SettingName> + <Identifier>none</Identifier> + <Type>DecimalNumber</Type> + <Value>1</Value> + <DefaultValue>1</DefaultValue> + <DestinationFile>public_mk_define</DestinationFile> + <Description>When FAT partition support is enabled, this specifies the FAT partition where the boot image is located.</Description> + <Restrictions>none</Restrictions> + <Enabled>false</Enabled> + <Group>common</Group> + </Setting> + <Setting> + <SettingName>spl.boot.FAT_LOAD_PAYLOAD_NAME</SettingName> + <Identifier>none</Identifier> + <Type>UnquotedString</Type> + <Value>u-boot.img</Value> + <DefaultValue>u-boot.img</DefaultValue> + <DestinationFile>public_mk_define</DestinationFile> + <Description>When FAT partition supported is enabled, this specifies the boot image filename within a FAT partition to be used as fatload payload.</Description> + <Restrictions>none</Restrictions> + <Enabled>false</Enabled> + <Group>common</Group> + </Setting> + <Setting> + <SettingName>spl.boot.WATCHDOG_ENABLE</SettingName> + <Identifier>none</Identifier> + <Type>Boolean</Type> + <Value>1</Value> + <DefaultValue>1</DefaultValue> + <DestinationFile>public_mk_define</DestinationFile> + <Description>Enable watchdog during Preloader execution phase. Watchdog state remains after Preloader exits.</Description> + <Restrictions>none</Restrictions> + <Enabled>false</Enabled> + <Group/> + </Setting> + <Setting> + <SettingName>spl.debug.DEBUG_MEMORY_WRITE</SettingName> + <Identifier>none</Identifier> + <Type>Boolean</Type> + <Value>0</Value> + <DefaultValue>0</DefaultValue> + <DestinationFile>public_mk_define</DestinationFile> + <Description>Enable debug memory write support for debugging, useful when UART is not available.</Description> + <Restrictions>none</Restrictions> + <Enabled>false</Enabled> + <Group/> + </Setting> + <Setting> + <SettingName>spl.debug.DEBUG_MEMORY_ADDR</SettingName> + <Identifier>none</Identifier> + <Type>HexNumber</Type> + <Value>0xfffffd00</Value> + <DefaultValue>0xFFFFFD00</DefaultValue> + <DestinationFile>public_mk_define</DestinationFile> + <Description>The base address used for storing Preloader debug information.</Description> + <Restrictions>none</Restrictions> + <Enabled>false</Enabled> + <Group/> + </Setting> + <Setting> + <SettingName>spl.debug.DEBUG_MEMORY_SIZE</SettingName> + <Identifier>none</Identifier> + <Type>HexNumber</Type> + <Value>0x200</Value> + <DefaultValue>0x200</DefaultValue> + <DestinationFile>public_mk_define</DestinationFile> + <Description>The amount of memory used for storing Preloader debug information.</Description> + <Restrictions>none</Restrictions> + <Enabled>false</Enabled> + <Group/> + </Setting> + <Setting> + <SettingName>spl.debug.SEMIHOSTING</SettingName> + <Identifier>none</Identifier> + <Type>Boolean</Type> + <Value>0</Value> + <DefaultValue>0</DefaultValue> + <DestinationFile>public_mk_define</DestinationFile> + <Description>Semihosting support in Preloader, to be used together with debugger tool. Useful when UART is not available.</Description> + <Restrictions>none</Restrictions> + <Enabled>false</Enabled> + <Group/> + </Setting> + <Setting> + <SettingName>spl.boot.CHECKSUM_NEXT_IMAGE</SettingName> + <Identifier>none</Identifier> + <Type>Boolean</Type> + <Value>1</Value> + <DefaultValue>1</DefaultValue> + <DestinationFile>public_mk_define</DestinationFile> + <Description>Option to check checksum of subsequent boot image.</Description> + <Restrictions>none</Restrictions> + <Enabled>false</Enabled> + <Group/> + </Setting> + <Setting> + <SettingName>spl.performance.SERIAL_SUPPORT</SettingName> + <Identifier>none</Identifier> + <Type>Boolean</Type> + <Value>1</Value> + <DefaultValue>1</DefaultValue> + <DestinationFile>public_mk_define</DestinationFile> + <Description>Enable UART printout support.</Description> + <Restrictions>none</Restrictions> + <Enabled>false</Enabled> + <Group/> + </Setting> + <Setting> + <SettingName>spl.debug.HARDWARE_DIAGNOSTIC</SettingName> + <Identifier>none</Identifier> + <Type>Boolean</Type> + <Value>0</Value> + <DefaultValue>0</DefaultValue> + <DestinationFile>public_mk_define</DestinationFile> + <Description>Enable hardware diagnostic support. To enable this, at least 1GB of memory is needed, otherwise hardware diagnostic will fail to run properly.</Description> + <Restrictions>none</Restrictions> + <Enabled>false</Enabled> + <Group/> + </Setting> + <Setting> + <SettingName>spl.boot.EXE_ON_FPGA</SettingName> + <Identifier>none</Identifier> + <Type>Boolean</Type> + <Value>0</Value> + <DefaultValue>0</DefaultValue> + <DestinationFile>public_mk_define</DestinationFile> + <Description>Execute Preloader on FPGA. Select this when BootROM is configured as FPGA boot.</Description> + <Restrictions>none</Restrictions> + <Enabled>false</Enabled> + <Group/> + </Setting> + <Setting> + <SettingName>spl.boot.FPGA_MAX_SIZE</SettingName> + <Identifier>none</Identifier> + <Type>HexNumber</Type> + <Value>0x10000</Value> + <DefaultValue>10000</DefaultValue> + <DestinationFile>public_mk_define</DestinationFile> + <Description>The maximum code (.text and .rodata) size that can fit within FPGA. If the actual code size is bigger than the specified size, it will trigger a build error.</Description> + <Restrictions>none</Restrictions> + <Enabled>false</Enabled> + <Group/> + </Setting> + <Setting> + <SettingName>spl.boot.FPGA_DATA_BASE</SettingName> + <Identifier>none</Identifier> + <Type>HexNumber</Type> + <Value>0xffff0000</Value> + <DefaultValue>0xFFFF0000</DefaultValue> + <DestinationFile>public_mk_define</DestinationFile> + <Description>The base address for data region (.data, .bss, malloc and stack) when execute on FPGA is enabled</Description> + <Restrictions>none</Restrictions> + <Enabled>false</Enabled> + <Group/> + </Setting> + <Setting> + <SettingName>spl.boot.FPGA_DATA_MAX_SIZE</SettingName> + <Identifier>none</Identifier> + <Type>HexNumber</Type> + <Value>0x10000</Value> + <DefaultValue>10000</DefaultValue> + <DestinationFile>public_mk_define</DestinationFile> + <Description>The maximum data (.data, .bss, malloc and stack) size that can fit within FPGA. If the actual data size is bigger than the specified size, it will trigger a build error.</Description> + <Restrictions>none</Restrictions> + <Enabled>false</Enabled> + <Group/> + </Setting> + <Setting> + <SettingName>spl.boot.STATE_REG_ENABLE</SettingName> + <Identifier>none</Identifier> + <Type>Boolean</Type> + <Value>1</Value> + <DefaultValue>1</DefaultValue> + <DestinationFile>public_mk_define</DestinationFile> + <Description>Enable write STATE_VALID value to STATE_REG register when Preloader exists. This tells BootROM that the Preloader has run successfully.</Description> + <Restrictions>none</Restrictions> + <Enabled>false</Enabled> + <Group/> + </Setting> + <Setting> + <SettingName>spl.boot.BOOTROM_HANDSHAKE_CFGIO</SettingName> + <Identifier>none</Identifier> + <Type>Boolean</Type> + <Value>1</Value> + <DefaultValue>1</DefaultValue> + <DestinationFile>public_mk_define</DestinationFile> + <Description>Enable handshake with BootROM when configuring the IOCSR and pin mux. When enabled and warm reset happens when the Preloader is still configuring IOCSR and pin mux, BootROM will reconfigure the IOCSR and pin mux again.</Description> + <Restrictions>none</Restrictions> + <Enabled>false</Enabled> + <Group/> + </Setting> + <Setting> + <SettingName>spl.boot.WARMRST_SKIP_CFGIO</SettingName> + <Identifier>none</Identifier> + <Type>Boolean</Type> + <Value>1</Value> + <DefaultValue>1</DefaultValue> + <DestinationFile>public_mk_define</DestinationFile> + <Description>When enabled, Preloader will skip configuring the IOCSR and pin mux when warm reset happens. Only applicable if BootROM has skipped configuring IOCSR and pin mux.</Description> + <Restrictions>none</Restrictions> + <Enabled>false</Enabled> + <Group/> + </Setting> + <Setting> + <SettingName>spl.debug.SKIP_SDRAM</SettingName> + <Identifier>none</Identifier> + <Type>Boolean</Type> + <Value>0</Value> + <DefaultValue>0</DefaultValue> + <DestinationFile>public_mk_define</DestinationFile> + <Description>When enabled, Preloader will skip SDRAM initialization and calibration.</Description> + <Restrictions>none</Restrictions> + <Enabled>false</Enabled> + <Group/> + </Setting> + <Setting> + <SettingName>spl.boot.SDRAM_SCRUBBING</SettingName> + <Identifier>none</Identifier> + <Type>Boolean</Type> + <Value>0</Value> + <DefaultValue>0</DefaultValue> + <DestinationFile>public_mk_define</DestinationFile> + <Description>Scrub SDRAM to initialize the ECC bits</Description> + <Restrictions>none</Restrictions> + <Enabled>false</Enabled> + <Group/> + </Setting> + <Setting> + <SettingName>spl.boot.SDRAM_SCRUB_BOOT_REGION_START</SettingName> + <Identifier>none</Identifier> + <Type>HexNumber</Type> + <Value>0x1000000</Value> + <DefaultValue>0x1000000</DefaultValue> + <DestinationFile>public_mk_define</DestinationFile> + <Description>The start address of the memory region within the SDRAM to be scrubbed.</Description> + <Restrictions>none</Restrictions> + <Enabled>false</Enabled> + <Group/> + </Setting> + <Setting> + <SettingName>spl.boot.SDRAM_SCRUB_BOOT_REGION_END</SettingName> + <Identifier>none</Identifier> + <Type>HexNumber</Type> + <Value>0x2000000</Value> + <DefaultValue>0x2000000</DefaultValue> + <DestinationFile>public_mk_define</DestinationFile> + <Description>The end address of the memory region within SDRAM to be scrubbed.</Description> + <Restrictions>none</Restrictions> + <Enabled>false</Enabled> + <Group/> + </Setting> + <Setting> + <SettingName>spl.boot.SDRAM_SCRUB_REMAIN_REGION</SettingName> + <Identifier>none</Identifier> + <Type>Boolean</Type> + <Value>1</Value> + <DefaultValue>1</DefaultValue> + <DestinationFile>public_mk_define</DestinationFile> + <Description>Scrub the remaining SDRAM memory regions. This will be done during the flash access (to load next boot image). The memory regions are auto calculated. For SOCFPAGA, it would be 2 regions as below: +> CONFIG_SYS_SDRAM_BASE to CONFIG_SPL_SDRAM_SCRUB_BOOT_REGION_START +> CONFIG_SPL_SDRAM_SCRUB_BOOT_REGION_END to calculated SDRAM size</Description> + <Restrictions>none</Restrictions> + <Enabled>false</Enabled> + <Group/> + </Setting> + <Setting> + <SettingName>spl.boot.RAMBOOT_PLLRESET</SettingName> + <Identifier>none</Identifier> + <Type>Boolean</Type> + <Value>1</Value> + <DefaultValue>1</DefaultValue> + <DestinationFile>public_mk_define</DestinationFile> + <Description>Execute RAM boot code after warm reset. This option must be enabled for warm reset to work when CSEL=0, where the RAM boot code will reset PLL settings and put Clock Manager into a state required by BootROM.</Description> + <Restrictions>none</Restrictions> + <Enabled>false</Enabled> + <Group/> + </Setting> +</sch:Settings>
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