diff options
Diffstat (limited to 'altera-socfpga/hardware-handoff/hps_hps_0/emif.xml')
| -rw-r--r-- | altera-socfpga/hardware-handoff/hps_hps_0/emif.xml | 183 |
1 files changed, 183 insertions, 0 deletions
diff --git a/altera-socfpga/hardware-handoff/hps_hps_0/emif.xml b/altera-socfpga/hardware-handoff/hps_hps_0/emif.xml new file mode 100644 index 0000000..01bc046 --- /dev/null +++ b/altera-socfpga/hardware-handoff/hps_hps_0/emif.xml @@ -0,0 +1,183 @@ +<emif> + <sequencer> + <define name="AC_ROM_MR1_MIRR" value="0000000100100"/> + <define name="AC_ROM_MR1_OCD_ENABLE" value=""/> + <define name="AC_ROM_MR2_MIRR" value="0000000010000"/> + <define name="AC_ROM_MR3_MIRR" value="0000000000000"/> + <define name="AC_ROM_MR0_CALIB" value=""/> + <define name="AC_ROM_MR0_DLL_RESET_MIRR" value="0010011001000"/> + <define name="AC_ROM_MR0_DLL_RESET" value="0010100110000"/> + <define name="AC_ROM_MR0_MIRR" value="0010001001001"/> + <define name="AC_ROM_MR0" value="0010000110001"/> + <define name="AC_ROM_MR1" value="0000001000100"/> + <define name="AC_ROM_MR2" value="0000000001000"/> + <define name="AC_ROM_MR3" value="0000000000000"/> + <define name="AC_ROM_USER_ADD_0" value="0_0000_0000_0000"/> + <define name="AC_ROM_USER_ADD_1" value="0_0000_0000_1000"/> + <define name="AFI_CLK_FREQ" value="401"/> + <define name="AFI_RATE_RATIO" value="1"/> + <define name="AP_MODE" value="0"/> + <define name="ARRIAVGZ" value="0"/> + <define name="ARRIAV" value="0"/> + <define name="AVL_CLK_FREQ" value="67"/> + <define name="BFM_MODE" value="0"/> + <define name="BURST2" value="0"/> + <define name="CALIBRATE_BIT_SLIPS" value="0"/> + <define name="CALIB_LFIFO_OFFSET" value="8"/> + <define name="CALIB_VFIFO_OFFSET" value="6"/> + <define name="CYCLONEV" value="1"/> + <define name="DDR2" value="0"/> + <define name="DDR3" value="1"/> + <define name="DDRX" value="1"/> + <define name="DM_PINS_ENABLED" value="1"/> + <define name="ENABLE_ASSERT" value="0"/> + <define name="ENABLE_BRINGUP_DEBUGGING" value="0"/> + <define name="ENABLE_DELAY_CHAIN_WRITE" value="0"/> + <define name="ENABLE_DQS_IN_CENTERING" value="1"/> + <define name="ENABLE_DQS_OUT_CENTERING" value="0"/> + <define name="ENABLE_EXPORT_SEQ_DEBUG_BRIDGE" value="0"/> + <define name="ENABLE_INST_ROM_WRITE" value="1"/> + <define name="ENABLE_MARGIN_REPORT_GEN" value="0"/> + <define name="ENABLE_NON_DESTRUCTIVE_CALIB" value="0"/> + <define name="ENABLE_NON_DES_CAL_TEST" value="0"/> + <define name="ENABLE_NON_DES_CAL" value="0"/> + <define name="ENABLE_SUPER_QUICK_CALIBRATION" value="0"/> + <define name="ENABLE_TCL_DEBUG" value="0"/> + <define name="FAKE_CAL_FAIL" value="0"/> + <define name="FULL_RATE" value="1"/> + <define name="GUARANTEED_READ_BRINGUP_TEST" value="0"/> + <define name="HALF_RATE" value="0"/> + <define name="HARD_PHY" value="1"/> + <define name="HARD_VFIFO" value="1"/> + <define name="HCX_COMPAT_MODE" value="0"/> + <define name="HHP_HPS_SIMULATION" value="0"/> + <define name="HHP_HPS_VERIFICATION" value="0"/> + <define name="HHP_HPS" value="1"/> + <define name="HPS_HW" value="1"/> + <define name="HR_DDIO_OUT_HAS_THREE_REGS" value="0"/> + <define name="IO_DELAY_PER_DCHAIN_TAP" value="25"/> + <define name="IO_DELAY_PER_DQS_EN_DCHAIN_TAP" value="25"/> + <define name="IO_DELAY_PER_OPA_TAP" value="312"/> + <define name="IO_DLL_CHAIN_LENGTH" value="8"/> + <define name="IO_DM_OUT_RESERVE" value="0"/> + <define name="IO_DQDQS_OUT_PHASE_MAX" value="0"/> + <define name="IO_DQS_EN_DELAY_MAX" value="31"/> + <define name="IO_DQS_EN_DELAY_OFFSET" value="0"/> + <define name="IO_DQS_EN_PHASE_MAX" value="7"/> + <define name="IO_DQS_IN_DELAY_MAX" value="31"/> + <define name="IO_DQS_IN_RESERVE" value="4"/> + <define name="IO_DQS_OUT_RESERVE" value="4"/> + <define name="IO_DQ_OUT_RESERVE" value="0"/> + <define name="IO_IO_IN_DELAY_MAX" value="31"/> + <define name="IO_IO_OUT1_DELAY_MAX" value="31"/> + <define name="IO_IO_OUT2_DELAY_MAX" value="0"/> + <define name="IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS" value="0"/> + <define name="LPDDR1" value="0"/> + <define name="LPDDR2" value="0"/> + <define name="LRDIMM" value="0"/> + <define name="MARGIN_VARIATION_TEST" value="0"/> + <define name="MAX_LATENCY_COUNT_WIDTH" value="5"/> + <define name="MEM_ADDR_WIDTH" value="13"/> + <define name="MRS_MIRROR_PING_PONG_ATSO" value="0"/> + <define name="MULTIPLE_AFI_WLAT" value="0"/> + <define name="NON_DES_CAL" value="0"/> + <define name="NUM_SHADOW_REGS" value="1"/> + <define name="QDRII" value="0"/> + <define name="QUARTER_RATE" value="0"/> + <define name="RDIMM" value="0"/> + <define name="READ_AFTER_WRITE_CALIBRATION" value="1"/> + <define name="READ_VALID_FIFO_SIZE" value="16"/> + <define name="REG_FILE_INIT_SEQ_SIGNATURE" value="0x55550496"/> + <define name="RLDRAM3" value="0"/> + <define name="RLDRAMII" value="0"/> + <define name="RLDRAMX" value="0"/> + <define name="RUNTIME_CAL_REPORT" value="0"/> + <define name="RW_MGR_MEM_ADDRESS_MIRRORING" value="0"/> + <define name="RW_MGR_MEM_ADDRESS_WIDTH" value="15"/> + <define name="RW_MGR_MEM_BANK_WIDTH" value="3"/> + <define name="RW_MGR_MEM_CHIP_SELECT_WIDTH" value="1"/> + <define name="RW_MGR_MEM_CLK_EN_WIDTH" value="1"/> + <define name="RW_MGR_MEM_CONTROL_WIDTH" value="1"/> + <define name="RW_MGR_MEM_DATA_MASK_WIDTH" value="5"/> + <define name="RW_MGR_MEM_DATA_WIDTH" value="40"/> + <define name="RW_MGR_MEM_DQ_PER_READ_DQS" value="8"/> + <define name="RW_MGR_MEM_DQ_PER_WRITE_DQS" value="8"/> + <define name="RW_MGR_MEM_IF_READ_DQS_WIDTH" value="5"/> + <define name="RW_MGR_MEM_IF_WRITE_DQS_WIDTH" value="5"/> + <define name="RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM" value="1"/> + <define name="RW_MGR_MEM_NUMBER_OF_RANKS" value="1"/> + <define name="RW_MGR_MEM_ODT_WIDTH" value="1"/> + <define name="RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS" value="1"/> + <define name="RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS" value="1"/> + <define name="RW_MGR_MR0_BL" value="1"/> + <define name="RW_MGR_MR0_CAS_LATENCY" value="3"/> + <define name="RW_MGR_TRUE_MEM_DATA_MASK_WIDTH" value="5"/> + <define name="RW_MGR_WRITE_TO_DEBUG_READ" value="1.0"/> + <define name="SKEW_CALIBRATION" value="0"/> + <define name="STATIC_FULL_CALIBRATION" value="1"/> + <define name="STATIC_SIM_FILESET" value="0"/> + <define name="STATIC_SKIP_MEM_INIT" value="0"/> + <define name="STRATIXV" value="0"/> + <define name="TINIT_CNTR1_VAL" value="32"/> + <define name="TINIT_CNTR2_VAL" value="32"/> + <define name="TINIT_CNTR0_VAL" value="99"/> + <define name="TRACKING_ERROR_TEST" value="0"/> + <define name="TRACKING_WATCH_TEST" value="0"/> + <define name="TRESET_CNTR1_VAL" value="99"/> + <define name="TRESET_CNTR2_VAL" value="10"/> + <define name="TRESET_CNTR0_VAL" value="99"/> + <define name="USE_DQS_TRACKING" value="1"/> + <define name="USE_SHADOW_REGS" value="0"/> + <define name="USE_USER_RDIMM_VALUE" value="0"/> + </sequencer> + <pll> + <define name="PLL_MEM_CLK_MULT" value="31"/> + <define name="PLL_MEM_CLK_DIV" value="0"/> + <define name="PLL_MEM_CLK_PHASE_DEG" value="0"/> + <define name="PLL_WRITE_CLK_MULT" value="31"/> + <define name="PLL_WRITE_CLK_DIV" value="0"/> + <define name="PLL_WRITE_CLK_PHASE_DEG" value="4"/> + </pll> + <controller> + <define name="AC_PARITY" value="false"/> + <define name="ADDR_ORDER" value="0"/> + <define name="CFG_READ_ODT_CHIP" value="0"/> + <define name="CFG_TCCD" value="1"/> + <define name="CFG_WRITE_ODT_CHIP" value="1"/> + <define name="DEVICE_DEPTH" value="1"/> + <define name="MEM_ASR" value="Manual"/> + <define name="MEM_ATCL_INT" value="0"/> + <define name="MEM_BT" value="Sequential"/> + <define name="MEM_BURST_LENGTH" value="8"/> + <define name="MEM_CK_WIDTH" value="1"/> + <define name="MEM_DQ_WIDTH" value="40"/> + <define name="MEM_DRV_STR" value="RZQ/6"/> + <define name="MEM_IF_BANKADDR_WIDTH" value="3"/> + <define name="MEM_IF_COL_ADDR_WIDTH" value="10"/> + <define name="MEM_IF_DM_PINS_EN" value="true"/> + <define name="MEM_IF_DQSN_EN" value="true"/> + <define name="MEM_IF_DQS_WIDTH" value="5"/> + <define name="MEM_IF_ROW_ADDR_WIDTH" value="15"/> + <define name="MEM_MIRROR_ADDRESSING" value="0"/> + <define name="MEM_PD" value="DLL off"/> + <define name="MEM_RTT_NOM" value="RZQ/6"/> + <define name="MEM_RTT_WR" value="Dynamic ODT off"/> + <define name="MEM_SRT" value="Normal"/> + <define name="MEM_TCL" value="7"/> + <define name="MEM_TFAW" value="12"/> + <define name="MEM_TMRD_CK" value="4"/> + <define name="MEM_TRAS" value="14"/> + <define name="MEM_TRC" value="20"/> + <define name="MEM_TRCD" value="6"/> + <define name="MEM_TREFI" value="3120"/> + <define name="MEM_TRFC" value="104"/> + <define name="MEM_TRP" value="6"/> + <define name="MEM_TRRD" value="4"/> + <define name="MEM_TRTP" value="4"/> + <define name="MEM_TWR" value="6"/> + <define name="MEM_TWTR" value="4"/> + <define name="MEM_WTCL_INT" value="6"/> + <define name="PLL_MEM_CLK_FREQ" value="400.0"/> + <define name="USE_HPS_DQS_TRACKING" value="false"/> + </controller> +</emif> |