SoCFPGA: Add Quartus generated BSP files

These files are automatically generated by the Altera SoC EDS embedded
design suite and added here unmodified. On system build they are combined
with U-Boot source to build the SPL preloader for SoCFPGA SoCs

Change-Id: Ie0b081b7e91789c77c870b2e7b87f868a1b38f3b

8 files changed, 1499 insertions, 0 deletions

diff --git a/altera-socfpga/hardware-handoff/spl_bsp/generated/build.h b/altera-socfpga/hardware-handoff/spl_bsp/generated/build.h
new file mode 100644
index 0000000..3ed7e6c
--- /dev/null
+++ b/altera-socfpga/hardware-handoff/spl_bsp/generated/build.h
@@ -0,0 +1,172 @@
+/* GENERATED FILE - DO NOT EDIT */
+/*
+ * Copyright Altera Corporation (C) 2012-2014. All rights reserved
+ *
+ * SPDX-License-Identifier:    BSD-3-Clause
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *    * Redistributions of source code must retain the above copyright
+ *      notice, this list of conditions and the following disclaimer.
+ *    * Redistributions in binary form must reproduce the above copyright
+ *      notice, this list of conditions and the following disclaimer in the
+ *      documentation and/or other materials provided with the distribution.
+ *    * Neither the name of Altera Corporation nor the
+ *      names of its contributors may be used to endorse or promote products
+ *      derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef	_PRELOADER_BUILD_H_
+#define	_PRELOADER_BUILD_H_
+
+/*
+ * Boot option. 1 mean that particular boot mode is selected.
+ * Only 1 boot option to be enabled at any time
+ */
+#define CONFIG_PRELOADER_BOOT_FROM_QSPI		(0)
+#define CONFIG_PRELOADER_BOOT_FROM_SDMMC	(1)
+#define CONFIG_PRELOADER_BOOT_FROM_NAND		(0)
+#define CONFIG_PRELOADER_BOOT_FROM_RAM		(0)
+
+/*
+ * Handoff files must provide image location of subsequent
+ * bootloader inside the boot devices / flashes
+ */
+#if (CONFIG_PRELOADER_BOOT_FROM_QSPI == 1)
+#define CONFIG_PRELOADER_QSPI_NEXT_BOOT_IMAGE	(0x60000)
+#endif
+#if (CONFIG_PRELOADER_BOOT_FROM_SDMMC == 1)
+#define CONFIG_PRELOADER_SDMMC_NEXT_BOOT_IMAGE	(0x40000)
+#endif
+#if (CONFIG_PRELOADER_BOOT_FROM_NAND == 1)
+#define CONFIG_PRELOADER_NAND_NEXT_BOOT_IMAGE	(0xc0000)
+#endif
+
+/* Enable FAT partition support when booting from SDMMC. */
+#define CONFIG_PRELOADER_FAT_SUPPORT		(0)
+
+/*
+ * When FAT partition support is enabled, this specifies the
+ * FAT partition where the boot image is located.
+ */
+#define CONFIG_PRELOADER_FAT_BOOT_PARTITION	(1)
+
+/*
+ * When FAT partition supported is enabled, this specifies the
+ * boot image filename within a FAT partition to be used as
+ * fatload payload.
+ */
+#define CONFIG_PRELOADER_FAT_LOAD_PAYLOAD_NAME 	"u-boot.img"
+
+/*
+ * Handoff files must provide user option whether to
+ * enable watchdog during preloader execution phase
+ */
+#define CONFIG_PRELOADER_WATCHDOG_ENABLE	(1)
+
+/*
+ * Handoff files must provide user option whether to enable
+ * debug memory write support
+ */
+#define CONFIG_PRELOADER_DEBUG_MEMORY_WRITE	(0)
+/* the base address of debug memory */
+#if (CONFIG_PRELOADER_DEBUG_MEMORY_WRITE == 1)
+#define CONFIG_PRELOADER_DEBUG_MEMORY_ADDR	(0xfffffd00)
+#define CONFIG_PRELOADER_DEBUG_MEMORY_SIZE	(0x200)
+#endif
+
+/* Semihosting support in Preloader */
+#define CONFIG_PRELOADER_SEMIHOSTING		(0)
+
+/* Option to check checksum of subsequent boot software image */
+#define CONFIG_PRELOADER_CHECKSUM_NEXT_IMAGE	(1)
+
+/*
+ * Handoff files must provide user option whether to enable
+ * debug serial printout support
+ */
+#define CONFIG_PRELOADER_SERIAL_SUPPORT		(1)
+
+/*
+ * Handoff files must provide user option whether to enable
+ * hardware diagnostic support
+ */
+#define CONFIG_PRELOADER_HARDWARE_DIAGNOSTIC	(0)
+
+/*
+ * Preloader execute on FPGA. This is normally selected
+ * for BootROM FPGA boot where Preloader located on FPGA
+ */
+#define CONFIG_PRELOADER_EXE_ON_FPGA		(0)
+#if (CONFIG_PRELOADER_EXE_ON_FPGA == 1)
+#define CONFIG_FPGA_MAX_SIZE			(0x10000)
+#define CONFIG_FPGA_DATA_BASE			0xffff0000
+#define CONFIG_FPGA_DATA_MAX_SIZE		(0x10000)
+#endif
+
+/*
+ * Add new option to force ramboot pll reset
+ */
+#define CONFIG_PRELOADER_RAMBOOT_PLLRESET	(1)
+
+/*
+ * Enabled write STATE_VALID value to STATE_REG register to
+ * tell BootROM that Preloader run successfully.
+ */
+#define CONFIG_PRELOADER_STATE_REG_ENABLE	(1)
+
+/*
+ * Enabled the handshake with BootROM when confiuring the IOCSR and pin mux.
+ * If enabled and warm reset happen in middle of Preloader configuring IOCSR
+ * and pin mux, BootROM will reconfigure the IOCSR and pin mux again.
+ */
+#define CONFIG_PRELOADER_BOOTROM_HANDSHAKE_CFGIO	(1)
+
+/*
+ * If enabled, when warm reset happen and BootROM skipped configuring IOCSR
+ * and pin mux, Preloader will skip configuring the IOCSR and pin mux too.
+ */
+#define CONFIG_PRELOADER_WARMRST_SKIP_CFGIO	(1)
+
+/*
+ * If enabled, Preloader will skip SDRAM initialization and calibration.
+ */
+#define CONFIG_PRELOADER_SKIP_SDRAM		(0)
+
+/*
+ * To configure whether to scrub the SDRAM to initialize the ECC bits
+ */
+#define CONFIG_PRELOADER_SDRAM_SCRUBBING    (0)
+
+/* To configure whether to scrub the SDRAM to initialize the ECC bits */
+#if (CONFIG_PRELOADER_SDRAM_SCRUBBING == 1)
+/*
+ * The region of next stage boot image will be copied to
+ */
+#define CONFIG_PRELOADER_SDRAM_SCRUB_BOOT_REGION_START    (0x1000000)
+#define CONFIG_PRELOADER_SDRAM_SCRUB_BOOT_REGION_END    (0x2000000)
+/*
+ * Decide remaining region will be scrubbed. This will be done during the flash
+ * access (to load next boot image). The region is auto calculated based on the
+ * remain region. For SOCFPAGA, it would be 2 regions as below
+ * > CONFIG_SYS_SDRAM_BASE to CONFIG_SPL_SDRAM_SCRUB_BOOT_REGION_START
+ * > CONFIG_SPL_SDRAM_SCRUB_BOOT_REGION_END to calculated SDRAM size
+ */
+#define CONFIG_PRELOADER_SDRAM_SCRUB_REMAIN_REGION    (1)
+
+#endif /* CONFIG_PRELOADER_SDRAM_SCRUBBING */
+
+#endif /* _PRELOADER_BUILD_H_ */
+
+
diff --git a/altera-socfpga/hardware-handoff/spl_bsp/generated/iocsr_config_cyclone5.c b/altera-socfpga/hardware-handoff/spl_bsp/generated/iocsr_config_cyclone5.c
new file mode 100644
index 0000000..2359b7c
--- /dev/null
+++ b/altera-socfpga/hardware-handoff/spl_bsp/generated/iocsr_config_cyclone5.c
@@ -0,0 +1,675 @@
+/* GENERATED FILE - DO NOT EDIT */
+/* 
+ * Copyright Altera Corporation (C) 2012-2014. All rights reserved
+ * 
+ * SPDX-License-Identifier:    BSD-3-Clause
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *    * Redistributions of source code must retain the above copyright
+ *      notice, this list of conditions and the following disclaimer.
+ *    * Redistributions in binary form must reproduce the above copyright
+ *      notice, this list of conditions and the following disclaimer in the
+ *      documentation and/or other materials provided with the distribution.
+ *    * Neither the name of Altera Corporation nor the
+ *      names of its contributors may be used to endorse or promote products
+ *      derived from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <iocsr_config_cyclone5.h>
+
+const unsigned long iocsr_scan_chain0_table[((CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH / 32) + 1)] = {
+	0x00100000,
+	0x40000000,
+	0x0FF00000,
+	0xC0000000,
+	0x0000003F,
+	0x00008000,
+	0x00080000,
+	0x01209000,
+	0x00000000,
+	0x00000080,
+	0x00020000,
+	0x00004000,
+	0x00040000,
+	0x10000000,
+	0x00000000,
+	0x00000040,
+	0x00010000,
+	0x00002000,
+	0x00020000,
+	0x08000000,
+	0x00000000,
+	0x00000020,
+	0x00008000,
+	0x00001000,
+};
+
+const unsigned long iocsr_scan_chain1_table[((CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH / 32) + 1)] = {
+	0x00009048,
+	0x02412000,
+	0x048000C0,
+	0x00000009,
+	0x00002412,
+	0x00008000,
+	0x00080000,
+	0x01209000,
+	0x82400000,
+	0x00000004,
+	0x00001209,
+	0x00004000,
+	0x00002412,
+	0x10000000,
+	0x41200000,
+	0x80000002,
+	0x00000904,
+	0x00002000,
+	0x00020000,
+	0x00482400,
+	0x01FE0000,
+	0xF8000000,
+	0x00000007,
+	0x00001000,
+	0x00010000,
+	0x04000000,
+	0x00000000,
+	0x00000010,
+	0x00004000,
+	0x00000800,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000008,
+	0x00002000,
+	0x00000400,
+	0x00000000,
+	0x00090480,
+	0x00000003,
+	0x00000000,
+	0x00000000,
+	0x90000200,
+	0x00600120,
+	0x00000000,
+	0x12090000,
+	0x24000600,
+	0x00000048,
+	0x48000100,
+	0x00300090,
+	0xC0024120,
+	0x09048000,
+	0x12000300,
+	0x000C0024,
+	0x00000080,
+};
+
+const unsigned long iocsr_scan_chain2_table[((CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH / 32) + 1)] = {
+	0x80009048,
+	0x00000000,
+	0x0FF00000,
+	0x00000000,
+	0x0C002412,
+	0x00008000,
+	0x00080000,
+	0x20000000,
+	0x82400000,
+	0x00040004,
+	0x00020000,
+	0x00004000,
+	0x00040000,
+	0x10000000,
+	0x00000000,
+	0x00000040,
+	0x00010000,
+	0x00002000,
+	0x00020000,
+	0x08000000,
+	0x00000000,
+	0x00000020,
+	0x00008000,
+	0x00001000,
+	0x00010000,
+	0x04000000,
+	0x00000000,
+	0x00000010,
+	0x00004000,
+	0x00000800,
+};
+
+const unsigned long iocsr_scan_chain3_table[((CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH / 32) + 1)] = {
+	0x0C420D80,
+	0x082000FF,
+	0x0A804001,
+	0x07900000,
+	0x08020000,
+	0x00100000,
+	0x0A800000,
+	0x07900000,
+	0x08020000,
+	0x00100000,
+	0xC8800000,
+	0x00003001,
+	0x00C00722,
+	0x00000000,
+	0x00000021,
+	0x82000004,
+	0x05400000,
+	0x03C80000,
+	0x04010000,
+	0x00080000,
+	0x05400000,
+	0x03C80000,
+	0x05400000,
+	0x03C80000,
+	0xE4400000,
+	0x00001800,
+	0x00600391,
+	0x800E4400,
+	0x00000001,
+	0x40000002,
+	0x02A00000,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x72200000,
+	0x80000C00,
+	0x003001C8,
+	0xC0072200,
+	0x1C880000,
+	0x20000300,
+	0x00040000,
+	0x50670000,
+	0x00000010,
+	0x24590000,
+	0x00001000,
+	0xA0000034,
+	0x0D000001,
+	0x40680C30,
+	0x8E034010,
+	0x02081A03,
+	0x80C300D0,
+	0x34010406,
+	0x01A00410,
+	0x300D0000,
+	0x1040680C,
+	0x00410340,
+	0xD000001A,
+	0x0680C300,
+	0x10040000,
+	0x00200000,
+	0x10040000,
+	0x00200000,
+	0x15000000,
+	0x0F200000,
+	0x15000000,
+	0x0F200000,
+	0x01FE0000,
+	0x00000000,
+	0x01800E44,
+	0x00391000,
+	0x007F8006,
+	0x00000000,
+	0x0A800001,
+	0x07900000,
+	0x0A800000,
+	0x07900000,
+	0x0A800000,
+	0x07900000,
+	0x08020000,
+	0x00100000,
+	0xC8800000,
+	0x00003001,
+	0x00C00722,
+	0x00000FF0,
+	0x72200000,
+	0x80000C00,
+	0x05400000,
+	0x02480000,
+	0x04000000,
+	0x00080000,
+	0x05400000,
+	0x03C80000,
+	0x05400000,
+	0x03C80000,
+	0x6A1C0000,
+	0x00001800,
+	0x00600391,
+	0x800E4400,
+	0x1A870001,
+	0x40000600,
+	0x02A00040,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x72200000,
+	0x80000C00,
+	0x003001C8,
+	0xC0072200,
+	0x1C880000,
+	0x20000300,
+	0x00040000,
+	0x50670000,
+	0x00000010,
+	0x24590000,
+	0x00001000,
+	0xA0000034,
+	0x0D000001,
+	0x40680C30,
+	0x41034010,
+	0x02081A00,
+	0x80C300D0,
+	0x34051406,
+	0x01A00040,
+	0x080D0002,
+	0x10406802,
+	0x00410340,
+	0xD002081A,
+	0x06802080,
+	0x10040000,
+	0x00200000,
+	0x10040000,
+	0x00200000,
+	0x15000000,
+	0x0F200000,
+	0x15000000,
+	0x0F200000,
+	0x01FE0000,
+	0x00000000,
+	0x01800E44,
+	0x00391000,
+	0x007F8006,
+	0x00000000,
+	0x99300001,
+	0x34343400,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A890,
+	0xAA0D4000,
+	0x01C3A800,
+	0x00040100,
+	0x00000800,
+	0x00000000,
+	0x00001208,
+	0x00482000,
+	0x01000000,
+	0x00000000,
+	0x00410482,
+	0x0006A000,
+	0x0001B400,
+	0x00020000,
+	0x00000400,
+	0x0002A000,
+	0x0001E400,
+	0x5506A000,
+	0x00E1D400,
+	0x00000000,
+	0xC880090C,
+	0x00003001,
+	0x90400000,
+	0x00000000,
+	0x2020C243,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA24,
+	0x2A835000,
+	0x0070EA00,
+	0x00010040,
+	0x00000200,
+	0x00000000,
+	0x00000482,
+	0x00120800,
+	0x00002000,
+	0x80000000,
+	0x00104120,
+	0x00000200,
+	0xAC0D5F80,
+	0xFFFFFFFF,
+	0x14F3690D,
+	0x1A041414,
+	0x00D00000,
+	0x08864000,
+	0x49247A02,
+	0xEBCF23DB,
+	0xF41E791E,
+	0x0356E388,
+	0x821A0000,
+	0x0000D000,
+	0x01040680,
+	0xDB71C47A,
+	0x1EEBCF23,
+	0x88F41E79,
+	0x000346A2,
+	0x00080200,
+	0x00001000,
+	0x00080200,
+	0x00001000,
+	0x000A8000,
+	0x00075000,
+	0x541A8000,
+	0x03875001,
+	0x10000000,
+	0x00000000,
+	0x0080C000,
+	0x41000000,
+	0x00003FC2,
+	0x00820000,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0x00040100,
+	0x00000800,
+	0x00000000,
+	0x00001208,
+	0x00482000,
+	0x00008000,
+	0x00000000,
+	0x00410482,
+	0x0006A000,
+	0x0001B400,
+	0x00020000,
+	0x00000400,
+	0x00020080,
+	0x00000400,
+	0x5506A000,
+	0x00E1D400,
+	0x00000000,
+	0x0000090C,
+	0x00000010,
+	0x90400000,
+	0x00000000,
+	0x2020C243,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x00015000,
+	0x0000F200,
+	0x00000000,
+	0x00000482,
+	0x00120800,
+	0x00600391,
+	0x80000000,
+	0x00104120,
+	0x00000200,
+	0xAC0D5F80,
+	0xFFFFFFFF,
+	0x14F3690D,
+	0x1A041414,
+	0x00D00000,
+	0x18864000,
+	0x49247A06,
+	0xABCF23DB,
+	0xF7DE791E,
+	0x0356E388,
+	0x821A028A,
+	0x0000D000,
+	0x00000680,
+	0xDB71C47A,
+	0x1EAACB23,
+	0x88F7DE79,
+	0x000356E3,
+	0x00080200,
+	0x00001000,
+	0x00080200,
+	0x00001000,
+	0x000A8000,
+	0x00075000,
+	0x541A8000,
+	0x03875001,
+	0x10000000,
+	0x00000000,
+	0x0080C000,
+	0x41000000,
+	0x04000002,
+	0x00820000,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0x00040100,
+	0x00000800,
+	0x00000000,
+	0x00001208,
+	0x00482000,
+	0x00008000,
+	0x00000000,
+	0x00410482,
+	0x0006A000,
+	0x0001B400,
+	0x00020000,
+	0x00000400,
+	0x0002A000,
+	0x0001E400,
+	0x5506A000,
+	0x00E1D400,
+	0x00000000,
+	0xC880090C,
+	0x00003001,
+	0x90400000,
+	0x00000000,
+	0x2020C243,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x00010040,
+	0x00000200,
+	0x00000000,
+	0x00000482,
+	0x00120800,
+	0x00002000,
+	0x80000000,
+	0x00104120,
+	0x00000200,
+	0xAC0D5F80,
+	0xFFFFFFFF,
+	0x14F3690D,
+	0x1A041414,
+	0x00D00000,
+	0x04864000,
+	0x69A47A01,
+	0x9A28A3D7,
+	0xF431451E,
+	0x0356E388,
+	0x821A0000,
+	0x0000D000,
+	0x00000680,
+	0xD749247A,
+	0x1EEBCF23,
+	0x88F43145,
+	0x000356E3,
+	0x00080200,
+	0x00001000,
+	0x00080200,
+	0x00001000,
+	0x000A8000,
+	0x00075000,
+	0x541A8000,
+	0x03875001,
+	0x10000000,
+	0x00000000,
+	0x0080C000,
+	0x41000000,
+	0x04000002,
+	0x00820000,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A890,
+	0xAA0D4000,
+	0x01C3A800,
+	0x00040100,
+	0x00000800,
+	0x00000000,
+	0x00001208,
+	0x00482000,
+	0x00008000,
+	0x00000000,
+	0x00410482,
+	0x0006A000,
+	0x0001B400,
+	0x00020000,
+	0x00000400,
+	0x00020080,
+	0x00000400,
+	0x5506A000,
+	0x00E1D400,
+	0x00000000,
+	0x0000090C,
+	0x00000010,
+	0x90400000,
+	0x00000000,
+	0x2020C243,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x00010040,
+	0x00000200,
+	0x00000000,
+	0x00000482,
+	0x00120800,
+	0x00400000,
+	0x80000000,
+	0x00104120,
+	0x00000200,
+	0xAC0D5F80,
+	0xFFFFFFFF,
+	0x14F1690D,
+	0x1A041414,
+	0x00D00000,
+	0x08864000,
+	0x71C47A02,
+	0xAACB23DB,
+	0xF7DE791E,
+	0x0346A288,
+	0x821A0000,
+	0x0000D000,
+	0x00000680,
+	0xDB49247A,
+	0x1EEBCF23,
+	0x88F41E79,
+	0x000356E3,
+	0x00080200,
+	0x00001000,
+	0x00080200,
+	0x00001000,
+	0x000A8000,
+	0x00075000,
+	0x541A8000,
+	0x03875001,
+	0x10000000,
+	0x00000000,
+	0x0080C000,
+	0x41000000,
+	0x04000002,
+	0x00820000,
+	0x00489800,
+	0x001A1A1A,
+	0x005506A0,
+	0x0000E1D4,
+	0x005506A0,
+	0x0000E1D4,
+	0x005506A0,
+	0x8000E1D4,
+	0x00000200,
+	0x00000004,
+	0x04000000,
+	0x00000009,
+	0x00002410,
+	0x00000040,
+	0x41000000,
+	0x00002082,
+	0x00000350,
+	0x000000DA,
+	0x00000100,
+	0x40000002,
+	0x00000100,
+	0x00000002,
+	0x002A8350,
+	0x000070EA,
+	0x86000000,
+	0x08000004,
+	0x00000000,
+	0x00482000,
+	0x21800000,
+	0x00101061,
+	0x001541A8,
+	0x00003875,
+	0x121541A8,
+	0x00003875,
+	0x001541A8,
+	0x20003875,
+	0x00000080,
+	0x00000001,
+	0x41000000,
+	0x00000002,
+	0x00FF0904,
+	0x00000000,
+	0x90400000,
+	0x00000820,
+	0xC0000001,
+	0xFFD606AF,
+	0x86FFFFFF,
+	0x0A0A78B4,
+	0x000D020A,
+	0x00006800,
+	0x01044320,
+	0xEDB8E23D,
+	0x8F75E791,
+	0xC47A0F3C,
+	0x0001AB71,
+	0x00410D00,
+	0x40000068,
+	0x3D000003,
+	0x91EBA492,
+	0x2C8F6565,
+	0x71C47AEB,
+	0x000001AB,
+	0x00000401,
+	0x00000008,
+	0x00000401,
+	0x00000008,
+	0x00000540,
+	0x000003A8,
+	0x00AA0D40,
+	0x8001C3A8,
+	0x0000007F,
+	0x00000000,
+	0x00004060,
+	0xE1208000,
+	0x0000001F,
+	0x00004100,
+};
+
diff --git a/altera-socfpga/hardware-handoff/spl_bsp/generated/iocsr_config_cyclone5.h b/altera-socfpga/hardware-handoff/spl_bsp/generated/iocsr_config_cyclone5.h
new file mode 100644
index 0000000..8f908f5
--- /dev/null
+++ b/altera-socfpga/hardware-handoff/spl_bsp/generated/iocsr_config_cyclone5.h
@@ -0,0 +1,38 @@
+/* GENERATED FILE - DO NOT EDIT */
+/* 
+ * Copyright Altera Corporation (C) 2012-2014. All rights reserved
+ * 
+ * SPDX-License-Identifier:    BSD-3-Clause
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *    * Redistributions of source code must retain the above copyright
+ *      notice, this list of conditions and the following disclaimer.
+ *    * Redistributions in binary form must reproduce the above copyright
+ *      notice, this list of conditions and the following disclaimer in the
+ *      documentation and/or other materials provided with the distribution.
+ *    * Neither the name of Altera Corporation nor the
+ *      names of its contributors may be used to endorse or promote products
+ *      derived from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _PRELOADER_IOCSR_CONFIG_H_
+#define _PRELOADER_IOCSR_CONFIG_H_
+
+#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH	(764)
+#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH	(1719)
+#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH	(955)
+#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH	(16766)
+
+#endif /*_PRELOADER_IOCSR_CONFIG_H_*/
diff --git a/altera-socfpga/hardware-handoff/spl_bsp/generated/pinmux_config.h b/altera-socfpga/hardware-handoff/spl_bsp/generated/pinmux_config.h
new file mode 100644
index 0000000..64c85d9
--- /dev/null
+++ b/altera-socfpga/hardware-handoff/spl_bsp/generated/pinmux_config.h
@@ -0,0 +1,75 @@
+/* GENERATED FILE - DO NOT EDIT */
+/* 
+ * Copyright Altera Corporation (C) 2012-2014. All rights reserved
+ * 
+ * SPDX-License-Identifier:    BSD-3-Clause
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *    * Redistributions of source code must retain the above copyright
+ *      notice, this list of conditions and the following disclaimer.
+ *    * Redistributions in binary form must reproduce the above copyright
+ *      notice, this list of conditions and the following disclaimer in the
+ *      documentation and/or other materials provided with the distribution.
+ *    * Neither the name of Altera Corporation nor the
+ *      names of its contributors may be used to endorse or promote products
+ *      derived from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _PRELOADER_PINMUX_CONFIG_H_
+#define _PRELOADER_PINMUX_CONFIG_H_
+
+#define CONFIG_HPS_EMAC0 (0)
+#define CONFIG_HPS_EMAC1 (1)
+#define CONFIG_HPS_USB0 (0)
+#define CONFIG_HPS_USB1 (0)
+#define CONFIG_HPS_NAND (0)
+#define CONFIG_HPS_SDMMC (1)
+#define CONFIG_HPS_QSPI (0)
+#define CONFIG_HPS_UART0 (1)
+#define CONFIG_HPS_UART1 (0)
+#define CONFIG_HPS_TRACE (0)
+#define CONFIG_HPS_I2C0 (1)
+#define CONFIG_HPS_I2C1 (0)
+#define CONFIG_HPS_I2C2 (0)
+#define CONFIG_HPS_I2C3 (0)
+#define CONFIG_HPS_SPIM0 (0)
+#define CONFIG_HPS_SPIM1 (0)
+#define CONFIG_HPS_SPIS0 (0)
+#define CONFIG_HPS_SPIS1 (0)
+#define CONFIG_HPS_CAN0 (0)
+#define CONFIG_HPS_CAN1 (0)
+
+#define CONFIG_HPS_SDMMC_BUSWIDTH (4)
+
+#define CONFIG_HPS_QSPI_CS3 (0)
+#define CONFIG_HPS_QSPI_CS2 (0)
+#define CONFIG_HPS_QSPI_CS1 (0)
+#define CONFIG_HPS_QSPI_CS0 (0)
+
+#define CONFIG_HPS_UART0_TX (1)
+#define CONFIG_HPS_UART0_CTS (0)
+#define CONFIG_HPS_UART0_RTS (0)
+#define CONFIG_HPS_UART0_RX (1)
+
+#define CONFIG_HPS_UART1_TX (0)
+#define CONFIG_HPS_UART1_CTS (0)
+#define CONFIG_HPS_UART1_RTS (0)
+#define CONFIG_HPS_UART1_RX (0)
+
+
+/* Pin MUX data */
+#define CONFIG_HPS_PINMUX_NUM	(207)
+
+#endif /* _PRELOADER_PINMUX_CONFIG_H_ */
diff --git a/altera-socfpga/hardware-handoff/spl_bsp/generated/pinmux_config_cyclone5.c b/altera-socfpga/hardware-handoff/spl_bsp/generated/pinmux_config_cyclone5.c
new file mode 100644
index 0000000..ca8d00c
--- /dev/null
+++ b/altera-socfpga/hardware-handoff/spl_bsp/generated/pinmux_config_cyclone5.c
@@ -0,0 +1,241 @@
+/* GENERATED FILE - DO NOT EDIT */
+/* 
+ * Copyright Altera Corporation (C) 2012-2014. All rights reserved
+ * 
+ * SPDX-License-Identifier:    BSD-3-Clause
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *    * Redistributions of source code must retain the above copyright
+ *      notice, this list of conditions and the following disclaimer.
+ *    * Redistributions in binary form must reproduce the above copyright
+ *      notice, this list of conditions and the following disclaimer in the
+ *      documentation and/or other materials provided with the distribution.
+ *    * Neither the name of Altera Corporation nor the
+ *      names of its contributors may be used to endorse or promote products
+ *      derived from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <pinmux_config.h>
+
+/* pin MUX configuration data */
+unsigned long sys_mgr_init_table[CONFIG_HPS_PINMUX_NUM] = {
+	0, /* EMACIO0 */
+	0, /* EMACIO1 */
+	0, /* EMACIO2 */
+	0, /* EMACIO3 */
+	0, /* EMACIO4 */
+	0, /* EMACIO5 */
+	0, /* EMACIO6 */
+	0, /* EMACIO7 */
+	0, /* EMACIO8 */
+	0, /* EMACIO9 */
+	0, /* EMACIO10 */
+	0, /* EMACIO11 */
+	0, /* EMACIO12 */
+	0, /* EMACIO13 */
+	0, /* EMACIO14 */
+	0, /* EMACIO15 */
+	0, /* EMACIO16 */
+	0, /* EMACIO17 */
+	0, /* EMACIO18 */
+	0, /* EMACIO19 */
+	3, /* FLASHIO0 */
+	0, /* FLASHIO1 */
+	3, /* FLASHIO2 */
+	3, /* FLASHIO3 */
+	0, /* FLASHIO4 */
+	0, /* FLASHIO5 */
+	0, /* FLASHIO6 */
+	0, /* FLASHIO7 */
+	0, /* FLASHIO8 */
+	3, /* FLASHIO9 */
+	3, /* FLASHIO10 */
+	3, /* FLASHIO11 */
+	0, /* GENERALIO0 */
+	0, /* GENERALIO1 */
+	0, /* GENERALIO2 */
+	0, /* GENERALIO3 */
+	0, /* GENERALIO4 */
+	0, /* GENERALIO5 */
+	0, /* GENERALIO6 */
+	0, /* GENERALIO7 */
+	0, /* GENERALIO8 */
+	0, /* GENERALIO9 */
+	0, /* GENERALIO10 */
+	0, /* GENERALIO11 */
+	0, /* GENERALIO12 */
+	0, /* GENERALIO13 */
+	0, /* GENERALIO14 */
+	3, /* GENERALIO15 */
+	3, /* GENERALIO16 */
+	2, /* GENERALIO17 */
+	2, /* GENERALIO18 */
+	0, /* GENERALIO19 */
+	0, /* GENERALIO20 */
+	0, /* GENERALIO21 */
+	0, /* GENERALIO22 */
+	0, /* GENERALIO23 */
+	0, /* GENERALIO24 */
+	0, /* GENERALIO25 */
+	0, /* GENERALIO26 */
+	0, /* GENERALIO27 */
+	0, /* GENERALIO28 */
+	0, /* GENERALIO29 */
+	0, /* GENERALIO30 */
+	0, /* GENERALIO31 */
+	2, /* MIXED1IO0 */
+	2, /* MIXED1IO1 */
+	2, /* MIXED1IO2 */
+	2, /* MIXED1IO3 */
+	2, /* MIXED1IO4 */
+	2, /* MIXED1IO5 */
+	2, /* MIXED1IO6 */
+	2, /* MIXED1IO7 */
+	2, /* MIXED1IO8 */
+	2, /* MIXED1IO9 */
+	2, /* MIXED1IO10 */
+	2, /* MIXED1IO11 */
+	2, /* MIXED1IO12 */
+	2, /* MIXED1IO13 */
+	0, /* MIXED1IO14 */
+	0, /* MIXED1IO15 */
+	0, /* MIXED1IO16 */
+	0, /* MIXED1IO17 */
+	0, /* MIXED1IO18 */
+	0, /* MIXED1IO19 */
+	0, /* MIXED1IO20 */
+	0, /* MIXED1IO21 */
+	0, /* MIXED2IO0 */
+	0, /* MIXED2IO1 */
+	0, /* MIXED2IO2 */
+	0, /* MIXED2IO3 */
+	0, /* MIXED2IO4 */
+	0, /* MIXED2IO5 */
+	0, /* MIXED2IO6 */
+	0, /* MIXED2IO7 */
+	0, /* GPLINMUX48 */
+	0, /* GPLINMUX49 */
+	0, /* GPLINMUX50 */
+	0, /* GPLINMUX51 */
+	0, /* GPLINMUX52 */
+	0, /* GPLINMUX53 */
+	0, /* GPLINMUX54 */
+	0, /* GPLINMUX55 */
+	0, /* GPLINMUX56 */
+	0, /* GPLINMUX57 */
+	0, /* GPLINMUX58 */
+	0, /* GPLINMUX59 */
+	0, /* GPLINMUX60 */
+	0, /* GPLINMUX61 */
+	0, /* GPLINMUX62 */
+	0, /* GPLINMUX63 */
+	0, /* GPLINMUX64 */
+	0, /* GPLINMUX65 */
+	0, /* GPLINMUX66 */
+	0, /* GPLINMUX67 */
+	0, /* GPLINMUX68 */
+	0, /* GPLINMUX69 */
+	0, /* GPLINMUX70 */
+	1, /* GPLMUX0 */
+	1, /* GPLMUX1 */
+	1, /* GPLMUX2 */
+	1, /* GPLMUX3 */
+	1, /* GPLMUX4 */
+	1, /* GPLMUX5 */
+	1, /* GPLMUX6 */
+	1, /* GPLMUX7 */
+	1, /* GPLMUX8 */
+	1, /* GPLMUX9 */
+	1, /* GPLMUX10 */
+	1, /* GPLMUX11 */
+	1, /* GPLMUX12 */
+	1, /* GPLMUX13 */
+	1, /* GPLMUX14 */
+	1, /* GPLMUX15 */
+	1, /* GPLMUX16 */
+	1, /* GPLMUX17 */
+	1, /* GPLMUX18 */
+	1, /* GPLMUX19 */
+	1, /* GPLMUX20 */
+	1, /* GPLMUX21 */
+	1, /* GPLMUX22 */
+	1, /* GPLMUX23 */
+	1, /* GPLMUX24 */
+	1, /* GPLMUX25 */
+	1, /* GPLMUX26 */
+	1, /* GPLMUX27 */
+	1, /* GPLMUX28 */
+	1, /* GPLMUX29 */
+	1, /* GPLMUX30 */
+	1, /* GPLMUX31 */
+	1, /* GPLMUX32 */
+	1, /* GPLMUX33 */
+	1, /* GPLMUX34 */
+	1, /* GPLMUX35 */
+	1, /* GPLMUX36 */
+	1, /* GPLMUX37 */
+	1, /* GPLMUX38 */
+	1, /* GPLMUX39 */
+	1, /* GPLMUX40 */
+	1, /* GPLMUX41 */
+	1, /* GPLMUX42 */
+	1, /* GPLMUX43 */
+	1, /* GPLMUX44 */
+	1, /* GPLMUX45 */
+	1, /* GPLMUX46 */
+	1, /* GPLMUX47 */
+	1, /* GPLMUX48 */
+	1, /* GPLMUX49 */
+	1, /* GPLMUX50 */
+	1, /* GPLMUX51 */
+	1, /* GPLMUX52 */
+	1, /* GPLMUX53 */
+	1, /* GPLMUX54 */
+	1, /* GPLMUX55 */
+	1, /* GPLMUX56 */
+	1, /* GPLMUX57 */
+	1, /* GPLMUX58 */
+	1, /* GPLMUX59 */
+	1, /* GPLMUX60 */
+	1, /* GPLMUX61 */
+	1, /* GPLMUX62 */
+	1, /* GPLMUX63 */
+	1, /* GPLMUX64 */
+	1, /* GPLMUX65 */
+	1, /* GPLMUX66 */
+	1, /* GPLMUX67 */
+	1, /* GPLMUX68 */
+	1, /* GPLMUX69 */
+	1, /* GPLMUX70 */
+	0, /* NANDUSEFPGA */
+	0, /* UART0USEFPGA */
+	0, /* RGMII1USEFPGA */
+	0, /* SPIS0USEFPGA */
+	0, /* CAN0USEFPGA */
+	0, /* I2C0USEFPGA */
+	0, /* SDMMCUSEFPGA */
+	0, /* QSPIUSEFPGA */
+	0, /* SPIS1USEFPGA */
+	0, /* RGMII0USEFPGA */
+	0, /* UART1USEFPGA */
+	0, /* CAN1USEFPGA */
+	0, /* USB1USEFPGA */
+	0, /* I2C3USEFPGA */
+	0, /* I2C2USEFPGA */
+	0, /* I2C1USEFPGA */
+	0, /* SPIM1USEFPGA */
+	0, /* USB0USEFPGA */
+	0 /* SPIM0USEFPGA */
+};
\ No newline at end of file
diff --git a/altera-socfpga/hardware-handoff/spl_bsp/generated/pll_config.h b/altera-socfpga/hardware-handoff/spl_bsp/generated/pll_config.h
new file mode 100644
index 0000000..986c703
--- /dev/null
+++ b/altera-socfpga/hardware-handoff/spl_bsp/generated/pll_config.h
@@ -0,0 +1,108 @@
+/* GENERATED FILE - DO NOT EDIT */
+/*
+ * Copyright Altera Corporation (C) 2012-2014. All rights reserved
+ * 
+ * SPDX-License-Identifier:    BSD-3-Clause
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *    * Redistributions of source code must retain the above copyright
+ *      notice, this list of conditions and the following disclaimer.
+ *    * Redistributions in binary form must reproduce the above copyright
+ *      notice, this list of conditions and the following disclaimer in the
+ *      documentation and/or other materials provided with the distribution.
+ *    * Neither the name of Altera Corporation nor the
+ *      names of its contributors may be used to endorse or promote products
+ *      derived from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _PRELOADER_PLL_CONFIG_H_
+#define _PRELOADER_PLL_CONFIG_H_
+
+#define CONFIG_HPS_DBCTRL_STAYOSC1 (1)
+
+#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM (0)
+#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER (63)
+#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT (0)
+#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT (0)
+#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT (0)
+#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT (511)
+#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT (511)
+#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT (15)
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK (1)
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK (1)
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK (0)
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK (0)
+#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK (0)
+#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK (1)
+#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK (0)
+#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP (1)
+#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP (1)
+
+#define CONFIG_HPS_PERPLLGRP_VCO_DENOM (0)
+#define CONFIG_HPS_PERPLLGRP_VCO_NUMER (39)
+#define CONFIG_HPS_PERPLLGRP_VCO_PSRC (0)
+#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT (511)
+#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT (3)
+#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT (511)
+#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT (4)
+#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT (9)
+#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT (511)
+#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK (4)
+#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK (4)
+#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK (4)
+#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK (4)
+#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK (3124)
+#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC (2)
+#define CONFIG_HPS_PERPLLGRP_SRC_NAND (2)
+#define CONFIG_HPS_PERPLLGRP_SRC_QSPI (1)
+
+#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM (0)
+#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER (31)
+#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC (0)
+#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT (1)
+#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE (0)
+#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT (0)
+#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE (0)
+#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT (1)
+#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE (4)
+#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT (5)
+#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE (0)
+
+#define CONFIG_HPS_CLK_OSC1_HZ (25000000)
+#define CONFIG_HPS_CLK_OSC2_HZ (25000000)
+#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ (0)
+#define CONFIG_HPS_CLK_F2S_PER_REF_HZ (0)
+#define CONFIG_HPS_CLK_MAINVCO_HZ (1600000000)
+#define CONFIG_HPS_CLK_PERVCO_HZ (1000000000)
+#define CONFIG_HPS_CLK_SDRVCO_HZ (800000000)
+#define CONFIG_HPS_CLK_EMAC0_HZ (1953125)
+#define CONFIG_HPS_CLK_EMAC1_HZ (250000000)
+#define CONFIG_HPS_CLK_USBCLK_HZ (6250000)
+#define CONFIG_HPS_CLK_NAND_HZ (50000000)
+#define CONFIG_HPS_CLK_SDMMC_HZ (200000000)
+#define CONFIG_HPS_CLK_QSPI_HZ (3125000)
+#define CONFIG_HPS_CLK_SPIM_HZ (6250000)
+#define CONFIG_HPS_CLK_CAN0_HZ (6250000)
+#define CONFIG_HPS_CLK_CAN1_HZ (6250000)
+#define CONFIG_HPS_CLK_GPIODB_HZ (32000)
+#define CONFIG_HPS_CLK_L4_MP_HZ (100000000)
+#define CONFIG_HPS_CLK_L4_SP_HZ (100000000)
+
+#define CONFIG_HPS_ALTERAGRP_MPUCLK (1)
+#define CONFIG_HPS_ALTERAGRP_MAINCLK (3)
+#define CONFIG_HPS_ALTERAGRP_DBGATCLK (3)
+
+#endif /* _PRELOADER_PLL_CONFIG_H_ */
+
diff --git a/altera-socfpga/hardware-handoff/spl_bsp/generated/reset_config.h b/altera-socfpga/hardware-handoff/spl_bsp/generated/reset_config.h
new file mode 100644
index 0000000..c7105d3
--- /dev/null
+++ b/altera-socfpga/hardware-handoff/spl_bsp/generated/reset_config.h
@@ -0,0 +1,82 @@
+/* GENERATED FILE - DO NOT EDIT */
+/*
+ * Copyright Altera Corporation (C) 2012-2014. All rights reserved
+ *
+ * SPDX-License-Identifier:    BSD-3-Clause
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *    * Redistributions of source code must retain the above copyright
+ *      notice, this list of conditions and the following disclaimer.
+ *    * Redistributions in binary form must reproduce the above copyright
+ *      notice, this list of conditions and the following disclaimer in the
+ *      documentation and/or other materials provided with the distribution.
+ *    * Neither the name of Altera Corporation nor the
+ *      names of its contributors may be used to endorse or promote products
+ *      derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _PRELOADER_RESET_CONFIG_H_
+#define _PRELOADER_RESET_CONFIG_H_
+
+/* 1 mean that particular IP need to be kept under reset state */
+#define CONFIG_HPS_RESET_ASSERT_EMAC0		(1)
+#define CONFIG_HPS_RESET_ASSERT_EMAC1		(0)
+#define CONFIG_HPS_RESET_ASSERT_USB0		(1)
+#define CONFIG_HPS_RESET_ASSERT_USB1		(1)
+#define CONFIG_HPS_RESET_ASSERT_NAND		(1)
+#define CONFIG_HPS_RESET_ASSERT_SDMMC		(0)
+#define CONFIG_HPS_RESET_ASSERT_QSPI		(1)
+#define CONFIG_HPS_RESET_ASSERT_UART0		(0)
+#define CONFIG_HPS_RESET_ASSERT_UART1		(1)
+#define CONFIG_HPS_RESET_ASSERT_I2C0		(0)
+#define CONFIG_HPS_RESET_ASSERT_I2C1		(1)
+#define CONFIG_HPS_RESET_ASSERT_I2C2		(1)
+#define CONFIG_HPS_RESET_ASSERT_I2C3		(1)
+#define CONFIG_HPS_RESET_ASSERT_SPIM0		(1)
+#define CONFIG_HPS_RESET_ASSERT_SPIM1		(1)
+#define CONFIG_HPS_RESET_ASSERT_SPIS0		(1)
+#define CONFIG_HPS_RESET_ASSERT_SPIS1		(1)
+#define CONFIG_HPS_RESET_ASSERT_CAN0		(1)
+#define CONFIG_HPS_RESET_ASSERT_CAN1		(1)
+#define CONFIG_HPS_RESET_ASSERT_L4WD1		(0)
+#define CONFIG_HPS_RESET_ASSERT_OSC1TIMER1	(0)
+#define CONFIG_HPS_RESET_ASSERT_SPTIMER0	(0)
+#define CONFIG_HPS_RESET_ASSERT_SPTIMER1	(0)
+#define CONFIG_HPS_RESET_ASSERT_GPIO0		(0)
+#define CONFIG_HPS_RESET_ASSERT_GPIO1		(0)
+#define CONFIG_HPS_RESET_ASSERT_GPIO2		(0)
+#define CONFIG_HPS_RESET_ASSERT_DMA		(0)
+#define CONFIG_HPS_RESET_ASSERT_SDR		(0)
+
+#define CONFIG_HPS_RESET_ASSERT_FPGA_DMA0	(1)
+#define CONFIG_HPS_RESET_ASSERT_FPGA_DMA1	(1)
+#define CONFIG_HPS_RESET_ASSERT_FPGA_DMA2	(1)
+#define CONFIG_HPS_RESET_ASSERT_FPGA_DMA3	(1)
+#define CONFIG_HPS_RESET_ASSERT_FPGA_DMA4	(1)
+#define CONFIG_HPS_RESET_ASSERT_FPGA_DMA5	(1)
+#define CONFIG_HPS_RESET_ASSERT_FPGA_DMA6	(1)
+#define CONFIG_HPS_RESET_ASSERT_FPGA_DMA7	(1)
+
+#define CONFIG_HPS_RESET_ASSERT_HPS2FPGA	(0)
+#define CONFIG_HPS_RESET_ASSERT_LWHPS2FPGA	(0)
+#define CONFIG_HPS_RESET_ASSERT_FPGA2HPS	(0)
+
+#define CONFIG_HPS_RESET_WARMRST_HANDSHAKE_FPGA		(1)
+#define CONFIG_HPS_RESET_WARMRST_HANDSHAKE_ETR		(1)
+#define CONFIG_HPS_RESET_WARMRST_HANDSHAKE_SDRAM	(0)
+
+#endif /* _PRELOADER_RESET_CONFIG_H_ */
+
+
diff --git a/altera-socfpga/hardware-handoff/spl_bsp/generated/sdram/sdram_config.h b/altera-socfpga/hardware-handoff/spl_bsp/generated/sdram/sdram_config.h
new file mode 100644
index 0000000..05d3ce2
--- /dev/null
+++ b/altera-socfpga/hardware-handoff/spl_bsp/generated/sdram/sdram_config.h
@@ -0,0 +1,108 @@
+/* GENERATED FILE - DO NOT EDIT */
+/*
+ * Copyright Altera Corporation (C) 2012-2014. All rights reserved
+ *
+ * SPDX-License-Identifier:    BSD-3-Clause
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *    * Redistributions of source code must retain the above copyright
+ *      notice, this list of conditions and the following disclaimer.
+ *    * Redistributions in binary form must reproduce the above copyright
+ *      notice, this list of conditions and the following disclaimer in the
+ *      documentation and/or other materials provided with the distribution.
+ *    * Neither the name of Altera Corporation nor the
+ *      names of its contributors may be used to endorse or promote products
+ *      derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __SDRAM_CONFIG_H
+#define __SDRAM_CONFIG_H
+
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE			(2)
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL			(8)
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER		(0)
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN			(1)
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN		(1)
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN		(1)
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT		(10)
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN			(0)
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS			(0)
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL			(6)
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL			(0)
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL			(7)
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD			(4)
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW			(12)
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC			(104)
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI		(3120)
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD		(6)
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP		(6)
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR		(6)
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR		(4)
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP			(4)
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS			(14)
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC			(20)
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD			(4)
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD			(4)
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT		(512)
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT		(3)
+#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES	(0)
+#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES	(8)
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS		(10)
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS		(15)
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS		(3)
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS			(1)
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH		(40)
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH		(8)
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN			(0)
+#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK		(3)
+#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL			(2)
+#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA		(0)
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH		(2)
+#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN		(0)
+#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE			(0)
+#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC			(0)
+#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY		(0x3FFD1088)
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0	(0x21084210)
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32	(0x1EF84)
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0	(0x2020)
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14	(0x0)
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46	(0xF800)
+#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0		(0x200)
+
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH		(0x44555)
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP		(0x2C011000)
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP		(0xB00088)
+#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP		(0x760210)
+#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP		(0x980543)
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR		(0x5A56A)
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0	(0x20820820)
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32	(0x8208208)
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0	(0)
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4	(0x41041041)
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36	(0x410410)
+#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 \
+(0x01010101)
+#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 \
+(0x01010101)
+#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 \
+(0x0101)
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ			(0)
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE			(1)
+#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_READ_PORT_USED	(0x1)
+#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_WRITE_PORT_USED	(0x1)
+#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_COMMAND_PORT_USED	(0x3)
+#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST			(0x311)
+
+#endif	/*#ifndef__SDRAM_CONFIG_H*/