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| author | Edward Cragg <edward.cragg@codethink.co.uk> | 2015-05-21 16:59:38 +0100 |
|---|---|---|
| committer | Edward Cragg <edward.cragg@codethink.co.uk> | 2015-09-24 09:28:10 +0100 |
| commit | 1a1dcc2a333ff1eb7eb50a8cf6b790ffa4d6e3d7 (patch) | |
| tree | 9392268a64e4aa2587fb6c7ac2a0b57bd161aa85 /altera-socfpga/hardware-handoff/hps_hps_0/emif.xml | |
| parent | 5ab3170a1da33e63a878865148879fb30f58d372 (diff) | |
| download | bsp-support-1a1dcc2a333ff1eb7eb50a8cf6b790ffa4d6e3d7.tar.gz | |
SoCFPGA: Add Quartus generated BSP files
These files are automatically generated by the Altera SoC EDS embedded
design suite and added here unmodified. On system build they are combined
with U-Boot source to build the SPL preloader for SoCFPGA SoCs
Change-Id: Ie0b081b7e91789c77c870b2e7b87f868a1b38f3b
Diffstat (limited to 'altera-socfpga/hardware-handoff/hps_hps_0/emif.xml')
0 files changed, 0 insertions, 0 deletions