Add Intel ADX, RDSEED, and SMAP instructions.

11 files changed, 158 insertions, 12 deletions

diff --git a/modules/arch/x86/gen_x86_insn.py b/modules/arch/x86/gen_x86_insn.py
index c4aedf04..88972b01 100755
--- a/modules/arch/x86/gen_x86_insn.py
+++ b/modules/arch/x86/gen_x86_insn.py
@@ -39,7 +39,8 @@ ordered_cpu_features = [
     "SSE3", "SVM", "PadLock", "SSSE3", "SSE41", "SSE42", "SSE4a", "SSE5",
     "AVX", "FMA", "AES", "CLMUL", "MOVBE", "XOP", "FMA4", "F16C",
     "FSGSBASE", "RDRAND", "XSAVEOPT", "EPTVPID", "SMX", "AVX2", "BMI1",
-    "BMI2", "INVPCID", "LZCNT", "TBM", "TSX", "SHA"]
+    "BMI2", "INVPCID", "LZCNT", "TBM", "TSX", "SHA", "SMAP", "RDSEED", "ADX",
+    "PRFCHW"]
 unordered_cpu_features = ["Priv", "Prot", "Undoc", "Obs"]
 
 # Predefined VEX prefix field values
@@ -7371,25 +7372,23 @@ for comb, combval in zip(["lql","hql","lqh","hqh"], [0x00,0x01,0x10,0x11]):
 
 # RDRAND
 add_group("rdrand",
-    cpu=["RDRAND"],
+    modifiers=['SpAdd'],
     opersize=16,
     opcode=[0x0F, 0xC7],
-    spare=6,
     operands=[Operand(type="Reg", size=16, dest="EA")])
 add_group("rdrand",
     #suffix="l",
-    cpu=["RDRAND"],
+    modifiers=['SpAdd'],
     opersize=32,
     opcode=[0x0F, 0xC7],
-    spare=6,
     operands=[Operand(type="Reg", size=32, dest="EA")])
 add_group("rdrand",
-    cpu=["RDRAND"],
+    modifiers=['SpAdd'],
     opersize=64,
     opcode=[0x0F, 0xC7],
-    spare=6,
     operands=[Operand(type="Reg", size=64, dest="EA")])
-add_insn("rdrand", "rdrand")
+add_insn("rdrand", "rdrand", modifiers=[6], cpu=["RDRAND"])
+add_insn("rdseed", "rdrand", modifiers=[7], cpu=["RDSEED"])
 
 # FSGSBASE instructions
 add_group("fs_gs_base",
@@ -7932,7 +7931,7 @@ add_insn("movbe", "movbe")
 add_insn("tzcnt", "cnt", modifiers=[0xBC], cpu=["BMI1"])
 # LZCNT is present as AMD ext
 
-for sfx, sz in zip("wlq", [32, 64]):
+for sfx, sz in zip("lq", [32, 64]):
     add_group("vex_gpr_ndd_rm_0F38_regext",
         suffix=sfx,
         modifiers=["PreAdd", "Op2Add", "SpAdd" ],
@@ -7951,7 +7950,7 @@ add_insn("blsmsk", "vex_gpr_ndd_rm_0F38_regext", modifiers=[0x00, 0xF3, 2],
 add_insn("blsi",   "vex_gpr_ndd_rm_0F38_regext", modifiers=[0x00, 0xF3, 3],
          cpu=["BMI1"])
 
-for sfx, sz in zip("wlq", [32, 64]):
+for sfx, sz in zip("lq", [32, 64]):
     add_group("vex_gpr_reg_rm_0F_imm8",
         suffix=sfx,
         modifiers=["PreAdd", "Op1Add", "Op2Add"],
@@ -8058,6 +8057,8 @@ add_insn("invpcid", "invpcid")
 
 
 #####################################################################
+# Intel SHA instructions
+#####################################################################
 add_group("intel_SHA1MSG1",
 	cpu=["SHA"],
 	opcode=[0x0F, 0x38, 0xC9],
@@ -8095,7 +8096,6 @@ add_group("intel_SHA256RNDS2",
 	operands=[Operand(type="SIMDReg", size=128, dest="Spare"),
 		Operand(type="SIMDReg", size=128, dest="EA")])
 
-
 add_insn("SHA1MSG1", "intel_SHA1MSG1")
 add_insn("SHA1MSG2", "intel_SHA1MSG2")
 add_insn("SHA1NEXTE", "intel_SHA1NEXTE")
@@ -8104,6 +8104,28 @@ add_insn("SHA256MSG1", "intel_SHA256MSG1")
 add_insn("SHA256MSG2", "intel_SHA256MSG2")
 add_insn("SHA256RNDS2", "intel_SHA256RNDS2")
 
+#####################################################################
+# Intel SMAP instructions
+#####################################################################
+add_insn("clac", "threebyte", modifiers=[0x0F, 0x01, 0xCA], cpu=["SMAP"])
+add_insn("stac", "threebyte", modifiers=[0x0F, 0x01, 0xCB], cpu=["SMAP"])
+
+#####################################################################
+# Intel ADX instructions
+#####################################################################
+for sfx, sz in zip("lq", [32, 64]):
+    add_group("vex_gpr_ndd_rm_0F38",
+        suffix=sfx,
+        modifiers=["PreAdd", "Op2Add"],
+        opersize=sz,
+        prefix=0x00,
+        opcode=[0x0F, 0x38, 0x00],
+        operands=[Operand(type="Reg", size=sz, dest="Spare"),
+                  Operand(type="RM", size=sz, relaxed=True, dest="EA")])
+
+add_insn("adcx", "vex_gpr_ndd_rm_0F38", modifiers=[0x66, 0xF6], cpu=["ADX"])
+add_insn("adox", "vex_gpr_ndd_rm_0F38", modifiers=[0xF3, 0xF6], cpu=["ADX"])
+
 
 #####################################################################
 # AMD trailing bit manipulation (TBM)
@@ -8137,7 +8159,7 @@ add_insn("tzmsk",   "xop_gpr_reg_rm_09", modifiers=[0x01, 4])
 #####################################################################
 
 add_insn("prefetch", "twobytemem", modifiers=[0x00, 0x0F, 0x0D], cpu=["3DNow"])
-add_insn("prefetchw", "twobytemem", modifiers=[0x01, 0x0F, 0x0D], cpu=["3DNow"])
+add_insn("prefetchw", "twobytemem", modifiers=[0x01, 0x0F, 0x0D], cpu=["PRFCHW"])
 add_insn("femms", "twobyte", modifiers=[0x0F, 0x0E], cpu=["3DNow"])
 
 add_group("now3d",
diff --git a/modules/arch/x86/tests/adx.asm b/modules/arch/x86/tests/adx.asm
new file mode 100644
index 00000000..3feb88e0
--- /dev/null
+++ b/modules/arch/x86/tests/adx.asm
@@ -0,0 +1,10 @@
+[bits 64]
+adcx eax, ebx
+adcx ebx, [0]
+adcx rax, rbx
+adcx rbx, [0]
+
+adox eax, ebx
+adox ebx, [0]
+adox rax, rbx
+adox rbx, [0]
diff --git a/modules/arch/x86/tests/adx.hex b/modules/arch/x86/tests/adx.hex
new file mode 100644
index 00000000..f6188af3
--- /dev/null
+++ b/modules/arch/x86/tests/adx.hex
@@ -0,0 +1,64 @@
+66 
+0f 
+38 
+f6 
+c3 
+66 
+0f 
+38 
+f6 
+1c 
+25 
+00 
+00 
+00 
+00 
+66 
+48 
+0f 
+38 
+f6 
+c3 
+66 
+48 
+0f 
+38 
+f6 
+1c 
+25 
+00 
+00 
+00 
+00 
+f3 
+0f 
+38 
+f6 
+c3 
+f3 
+0f 
+38 
+f6 
+1c 
+25 
+00 
+00 
+00 
+00 
+f3 
+48 
+0f 
+38 
+f6 
+c3 
+f3 
+48 
+0f 
+38 
+f6 
+1c 
+25 
+00 
+00 
+00 
+00 
diff --git a/modules/arch/x86/tests/rdrand.asm b/modules/arch/x86/tests/rdrand.asm
new file mode 100644
index 00000000..20ade23f
--- /dev/null
+++ b/modules/arch/x86/tests/rdrand.asm
@@ -0,0 +1,4 @@
+[bits 64]
+rdrand bx
+rdrand ebx
+rdrand rbx
diff --git a/modules/arch/x86/tests/rdrand.hex b/modules/arch/x86/tests/rdrand.hex
new file mode 100644
index 00000000..25ac57c4
--- /dev/null
+++ b/modules/arch/x86/tests/rdrand.hex
@@ -0,0 +1,11 @@
+66 
+0f 
+c7 
+f3 
+0f 
+c7 
+f3 
+48 
+0f 
+c7 
+f3 
diff --git a/modules/arch/x86/tests/rdseed.asm b/modules/arch/x86/tests/rdseed.asm
new file mode 100644
index 00000000..42fff846
--- /dev/null
+++ b/modules/arch/x86/tests/rdseed.asm
@@ -0,0 +1,4 @@
+[bits 64]
+rdseed bx
+rdseed ebx
+rdseed rbx
diff --git a/modules/arch/x86/tests/rdseed.hex b/modules/arch/x86/tests/rdseed.hex
new file mode 100644
index 00000000..03f4fbd3
--- /dev/null
+++ b/modules/arch/x86/tests/rdseed.hex
@@ -0,0 +1,11 @@
+66 
+0f 
+c7 
+fb 
+0f 
+c7 
+fb 
+48 
+0f 
+c7 
+fb 
diff --git a/modules/arch/x86/tests/smap.asm b/modules/arch/x86/tests/smap.asm
new file mode 100644
index 00000000..702bc810
--- /dev/null
+++ b/modules/arch/x86/tests/smap.asm
@@ -0,0 +1,2 @@
+clac
+stac
diff --git a/modules/arch/x86/tests/smap.hex b/modules/arch/x86/tests/smap.hex
new file mode 100644
index 00000000..a1034059
--- /dev/null
+++ b/modules/arch/x86/tests/smap.hex
@@ -0,0 +1,6 @@
+0f 
+01 
+ca 
+0f 
+01 
+cb 
diff --git a/modules/arch/x86/x86arch.h b/modules/arch/x86/x86arch.h
index 7ad10466..78c3d739 100644
--- a/modules/arch/x86/x86arch.h
+++ b/modules/arch/x86/x86arch.h
@@ -86,6 +86,10 @@
 #define CPU_TBM     52      /* AMD TBM instruction */
 #define CPU_TSX     53      /* Intel TSX instructions */
 #define CPU_SHA     54      /* Intel SHA instructions */
+#define CPU_SMAP    55      /* Intel SMAP instructions */
+#define CPU_RDSEED  56      /* Intel RDSEED instruction */
+#define CPU_ADX     57      /* Intel ADCX and ADOX instructions */
+#define CPU_PRFCHW  58      /* Intel/AMD PREFETCHW instruction */
 
 enum x86_parser_type {
     X86_PARSER_NASM = 0,
diff --git a/modules/arch/x86/x86cpu.gperf b/modules/arch/x86/x86cpu.gperf
index d6808660..4d7d5e52 100644
--- a/modules/arch/x86/x86cpu.gperf
+++ b/modules/arch/x86/x86cpu.gperf
@@ -404,6 +404,14 @@ tbm,		x86_cpu_set,	CPU_TBM
 notbm,	x86_cpu_clear,	CPU_TBM
 sha,		x86_cpu_set,	CPU_SHA
 nosha,		x86_cpu_clear,	CPU_SHA
+smap,		x86_cpu_set,	CPU_SMAP
+nosmap,		x86_cpu_clear,	CPU_SMAP
+rdseed,		x86_cpu_set,	CPU_RDSEED
+nordseed,	x86_cpu_clear,	CPU_RDSEED
+adx,		x86_cpu_set,	CPU_ADX
+noadx,		x86_cpu_clear,	CPU_ADX
+prfchw,		x86_cpu_set,	CPU_PRFCHW
+noprfchw,	x86_cpu_clear,	CPU_PRFCHW
 # Change NOP patterns
 basicnop,	x86_nop,	X86_NOP_BASIC
 intelnop,	x86_nop,	X86_NOP_INTEL