diff options
| author | Zhenyu Wang <zhenyu.z.wang@intel.com> | 2008-02-19 08:51:53 +0800 |
|---|---|---|
| committer | Zhenyu Wang <zhenyu.z.wang@intel.com> | 2008-02-19 08:56:25 +0800 |
| commit | aa1813e4807e500fb122f36af988cf60f91e05a5 (patch) | |
| tree | 088bffa91e7ac96f3e6e00b4ad56959cb049f929 | |
| parent | 1cea254b70158600d9dfff8ba66fb2ec0a6e0f67 (diff) | |
| download | xorg-driver-xf86-video-intel-aa1813e4807e500fb122f36af988cf60f91e05a5.tar.gz | |
Fix last 8XX clock's p2 value commit
My fault to change Hong's origin patch reversely.
| -rw-r--r-- | src/i830_display.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/src/i830_display.c b/src/i830_display.c index 7a2520d7..8f7c0689 100644 --- a/src/i830_display.c +++ b/src/i830_display.c @@ -1640,10 +1640,11 @@ i830_crtc_clock_get(ScrnInfoPtr pScrn, xf86CrtcPtr crtc) clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> DPLL_FPA01_P1_POST_DIV_SHIFT); + /* if LVDS is dual-channel, p2 = 7 */ if ((INREG(LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP) - clock.p2 = I8XX_P2_LVDS_SLOW; + clock.p2 = 7; else - clock.p2 = I8XX_P2_LVDS_FAST; + clock.p2 = 14; if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) i8xx_clock(66000, &clock); /* XXX: might not be 66MHz */ |