diff options
Diffstat (limited to 'runtime/syntax/vhdl.vim')
| -rw-r--r-- | runtime/syntax/vhdl.vim | 101 |
1 files changed, 64 insertions, 37 deletions
diff --git a/runtime/syntax/vhdl.vim b/runtime/syntax/vhdl.vim index 916bd9635..044ef83d1 100644 --- a/runtime/syntax/vhdl.vim +++ b/runtime/syntax/vhdl.vim @@ -1,14 +1,10 @@ " Vim syntax file -" Language: VHDL -" Maintainer: Daniel Kho <daniel.kho@tauhop.com> +" Language: VHDL [VHSIC (Very High Speed Integrated Circuit) Hardware Description Language] +" Maintainer: Daniel Kho <daniel.kho@tauhop.com> " Previous Maintainer: Czo <Olivier.Sirol@lip6.fr> -" Credits: Stephan Hegel <stephan.hegel@snc.siemens.com.cn> -" Last Changed: 2015 Dec 4 by Daniel Kho +" Credits: Stephan Hegel <stephan.hegel@snc.siemens.com.cn> +" Last Changed: 2016 Mar 05 by Daniel Kho -" VHSIC (Very High Speed Integrated Circuit) Hardware Description Language - -" For version 5.x: Clear all syntax items -" For version 6.x: Quit when a syntax file was already loaded if version < 600 syntax clear elseif exists("b:current_syntax") @@ -56,17 +52,40 @@ syn keyword vhdlStatement note warning error failure syn match vhdlStatement "\<\(if\|else\)\>" syn match vhdlError "\<else\s\+if\>" -" Predefined VHDL types -syn keyword vhdlType bit bit_vector -syn keyword vhdlType character boolean integer real time -syn keyword vhdlType boolean_vector integer_vector real_vector time_vector -syn keyword vhdlType string severity_level -" Predefined standard ieee VHDL types -syn keyword vhdlType positive natural signed unsigned -syn keyword vhdlType unresolved_signed unresolved_unsigned u_signed u_unsigned -syn keyword vhdlType line text -syn keyword vhdlType std_logic std_logic_vector -syn keyword vhdlType std_ulogic std_ulogic_vector +" Types and type qualifiers +" Predefined standard VHDL types +syn match vhdlType "bit[\']*" +syn match vhdlType "boolean[\']*" +syn match vhdlType "natural[\']*" +syn match vhdlType "positive[\']*" +syn match vhdlType "integer[\']*" +syn match vhdlType "real[\']*" +syn match vhdlType "time[\']*" + +syn match vhdlType "bit_vector[\']*" +syn match vhdlType "boolean_vector[\']*" +syn match vhdlType "integer_vector[\']*" +syn match vhdlType "real_vector[\']*" +syn match vhdlType "time_vector[\']*" + +syn match vhdlType "character[\']*" +syn match vhdlType "string[\']*" +"syn keyword vhdlType severity_level +syn match vhdlType "line[\']*" +syn match vhdlType "text[\']*" + +" Predefined standard IEEE VHDL types +syn match vhdlType "std_ulogic[\']*" +syn match vhdlType "std_logic[\']*" +syn match vhdlType "std_ulogic_vector[\']*" +syn match vhdlType "std_logic_vector[\']*" +syn match vhdlType "unresolved_signed[\']*" +syn match vhdlType "unresolved_unsigned[\']*" +syn match vhdlType "u_signed[\']*" +syn match vhdlType "u_unsigned[\']*" +syn match vhdlType "signed[\']*" +syn match vhdlType "unsigned[\']*" + " array attributes syn match vhdlAttribute "\'high" @@ -191,15 +210,23 @@ syn case ignore syn region vhdlComment start="/\*" end="\*/" contains=vhdlTodo,vhdlFixme,@Spell syn match vhdlComment "\(^\|\s\)--.*" contains=vhdlTodo,vhdlFixme,@Spell +" Standard IEEE P1076.6 preprocessor directives (metacomments). +syn match vhdlPreProc "/\*\s*rtl_synthesis\s\+\(on\|off\)\s*\*/" +syn match vhdlPreProc "\(^\|\s\)--\s*rtl_synthesis\s\+\(on\|off\)\s*" +syn match vhdlPreProc "/\*\s*rtl_syn\s\+\(on\|off\)\s*\*/" +syn match vhdlPreProc "\(^\|\s\)--\s*rtl_syn\s\+\(on\|off\)\s*" + " Industry-standard directives. These are not standard VHDL, but are commonly " used in the industry. syn match vhdlPreProc "/\*\s*synthesis\s\+translate_\(on\|off\)\s*\*/" "syn match vhdlPreProc "/\*\s*simulation\s\+translate_\(on\|off\)\s*\*/" +syn match vhdlPreProc "/\*\s*pragma\s\+translate_\(on\|off\)\s*\*/" syn match vhdlPreProc "/\*\s*pragma\s\+synthesis_\(on\|off\)\s*\*/" syn match vhdlPreProc "/\*\s*synopsys\s\+translate_\(on\|off\)\s*\*/" syn match vhdlPreProc "\(^\|\s\)--\s*synthesis\s\+translate_\(on\|off\)\s*" "syn match vhdlPreProc "\(^\|\s\)--\s*simulation\s\+translate_\(on\|off\)\s*" +syn match vhdlPreProc "\(^\|\s\)--\s*pragma\s\+translate_\(on\|off\)\s*" syn match vhdlPreProc "\(^\|\s\)--\s*pragma\s\+synthesis_\(on\|off\)\s*" syn match vhdlPreProc "\(^\|\s\)--\s*synopsys\s\+translate_\(on\|off\)\s*" @@ -216,24 +243,24 @@ if version >= 508 || !exists("did_vhdl_syntax_inits") else command -nargs=+ HiLink hi def link <args> endif - - HiLink vhdlSpecial Special - HiLink vhdlStatement Statement - HiLink vhdlCharacter Character - HiLink vhdlString String - HiLink vhdlVector Number - HiLink vhdlBoolean Number - HiLink vhdlTodo Todo - HiLink vhdlFixme Fixme - HiLink vhdlComment Comment - HiLink vhdlNumber Number - HiLink vhdlTime Number - HiLink vhdlType Type - HiLink vhdlOperator Operator - HiLink vhdlError Error - HiLink vhdlAttribute Special - HiLink vhdlPreProc PreProc - + + HiLink vhdlSpecial Special + HiLink vhdlStatement Statement + HiLink vhdlCharacter Character + HiLink vhdlString String + HiLink vhdlVector Number + HiLink vhdlBoolean Number + HiLink vhdlTodo Todo + HiLink vhdlFixme Fixme + HiLink vhdlComment Comment + HiLink vhdlNumber Number + HiLink vhdlTime Number + HiLink vhdlType Type + HiLink vhdlOperator Operator + HiLink vhdlError Error + HiLink vhdlAttribute Special + HiLink vhdlPreProc PreProc + delcommand HiLink endif |