Update runtime files

4 files changed, 37 insertions, 18 deletions

diff --git a/runtime/syntax/bsdl.vim b/runtime/syntax/bsdl.vim
new file mode 100644
index 000000000..75c69558e
--- /dev/null
+++ b/runtime/syntax/bsdl.vim
@@ -0,0 +1,17 @@
+" Vim syntax file
+" Language:	Boundary Scan Description Language (BSDL)
+" Maintainer:	Daniel Kho <daniel.kho@logik.haus>
+" Last Changed:	2020 Mar 19 by Daniel Kho
+
+" quit when a syntax file was already loaded
+if exists("b:current_syntax")
+    finish
+endif
+
+" Read in VHDL syntax files
+runtime! syntax/vhdl.vim
+unlet b:current_syntax
+
+let b:current_syntax = "bsdl"
+
+" vim: ts=8
diff --git a/runtime/syntax/html.vim b/runtime/syntax/html.vim
index 1571af370..aa9cb1205 100644
--- a/runtime/syntax/html.vim
+++ b/runtime/syntax/html.vim
@@ -3,8 +3,8 @@
 " Maintainer:           Jorge Maldonado Ventura <jorgesumle@freakspot.net>
 " Previous Maintainer:  Claudio Fleiner <claudio@fleiner.com>
 " Repository:           https://notabug.org/jorgesumle/vim-html-syntax
-" Last Change:          2019 Dec 24
-" Included patch from Jorge Maldonado Ventura to add the dialog element
+" Last Change:          2020 Mar 17
+" Included patch from Florian Breisch to add the summary element
 "
 
 " Please check :help html.vim for some comments and a description of the options
@@ -61,7 +61,8 @@ syn keyword htmlTagName contained datalist details dialog embed figcaption
 syn keyword htmlTagName contained figure footer header hgroup keygen main
 syn keyword htmlTagName contained mark menuitem meter nav output picture
 syn keyword htmlTagName contained progress rb rp rt rtc ruby section
-syn keyword htmlTagName contained slot source template time track video wbr
+syn keyword htmlTagName contained slot source summary template time track
+syn keyword htmlTagName contained video wbr
 
 " legal arg names
 syn keyword htmlArg contained action
diff --git a/runtime/syntax/jargon.vim b/runtime/syntax/jargon.vim
index 05f45a2c9..c4b017d9e 100644
--- a/runtime/syntax/jargon.vim
+++ b/runtime/syntax/jargon.vim
@@ -1,23 +1,24 @@
 " Vim syntax file
 " Language:	Jargon File
 " Maintainer:	Dan Church (https://github.com/h3xx)
-" Last Change:	2019 Sep 27
+" Last Change:	2020 Mar 16
 "
 " quit when a syntax file was already loaded
 if exists("b:current_syntax")
 	finish
 endif
 
-syn match jargonChaptTitle	/:[^:]*:/
-syn match jargonEmailAddr	/[^<@ ^I]*@[^ ^I>]*/
-syn match jargonUrl	 +\(http\|ftp\)://[^\t )"]*+
-syn region jargonMark	 start="{"  end="}"
+syn region jargonHeader start="^:" end="$" contains=jargonChaptTitle
+syn match jargonChaptTitle /:[^:]*:/ contained
+syn match jargonEmailAddr /[+._A-Za-z0-9-]\+@[+._A-Za-z0-9-]\+/
+syn match jargonUrl +\(https\?\|ftp\)://[^\t )"]*+
+syn region jargonMark start="{[^\t {}]" end="}"
 
 " Define the default highlighting.
 " Only when an item doesn't have highlighting yet
-hi def link jargonChaptTitle	Title
-hi def link jargonEmailAddr	 Comment
-hi def link jargonUrl	 Comment
-hi def link jargonMark	Label
+hi def link jargonChaptTitle Title
+hi def link jargonEmailAddr Comment
+hi def link jargonUrl Comment
+hi def link jargonMark Label
 
 let b:current_syntax = "jargon"
diff --git a/runtime/syntax/vhdl.vim b/runtime/syntax/vhdl.vim
index efcb84028..b40b09652 100644
--- a/runtime/syntax/vhdl.vim
+++ b/runtime/syntax/vhdl.vim
@@ -1,9 +1,9 @@
 " Vim syntax file
 " Language:		VHDL [VHSIC (Very High Speed Integrated Circuit) Hardware Description Language]
-" Maintainer:		Daniel Kho <daniel.kho@tauhop.com>
+" Maintainer:		Daniel Kho <daniel.kho@logik.haus>
 " Previous Maintainer:	Czo <Olivier.Sirol@lip6.fr>
 " Credits:		Stephan Hegel <stephan.hegel@snc.siemens.com.cn>
-" Last Changed:		2018 May 06 by Daniel Kho
+" Last Changed:		2020 Mar 09 by Daniel Kho
 
 " quit when a syntax file was already loaded
 if exists("b:current_syntax")
@@ -43,7 +43,7 @@ syn keyword 	vhdlStatement	sequence strong
 syn keyword 	vhdlStatement	then to transport type
 syn keyword 	vhdlStatement	unaffected units until use
 syn keyword 	vhdlStatement	variable
-" VHDL-2017 interface
+" VHDL-2019 interface
 syn keyword 	vhdlStatement	view
 syn keyword 	vhdlStatement	vmode vprop vunit
 syn keyword 	vhdlStatement	wait when while with
@@ -124,7 +124,7 @@ syn match   	vhdlAttribute	"\'succ"
 syn match   	vhdlAttribute	"\'val"
 syn match   	vhdlAttribute	"\'image"
 syn match   	vhdlAttribute	"\'value"
-" VHDL-2017 interface attribute
+" VHDL-2019 interface attribute
 syn match   	vhdlAttribute	"\'converse"
 
 syn keyword	vhdlBoolean	true false
@@ -167,7 +167,7 @@ syn match	vhdlOperator	"=\|\/=\|>\|<\|>="
 syn match	vhdlOperator	"<=\|:="
 syn match	vhdlOperator	"=>"
 
-" VHDL-2017 concurrent signal association (spaceship) operator
+" VHDL-202x concurrent signal association (spaceship) operator
 syn match	vhdlOperator	"<=>"
 
 " VHDL-2008 conversion, matching equality/non-equality operators
@@ -188,7 +188,7 @@ syn match	vhdlError	"\(<\)[&+\-\/\\]\+"
 syn match	vhdlError	"[>=&+\-\/\\]\+\(<\)"
 " Covers most operators
 " support negative sign after operators. E.g. q<=-b;
-" Supports VHDL-2017 spaceship (concurrent simple signal association).
+" Supports VHDL-202x spaceship (concurrent simple signal association).
 syn match	vhdlError	"\(<=\)[<=&+\*\\?:]\+"
 syn match	vhdlError	"[>=&+\-\*\\:]\+\(=>\)"
 syn match	vhdlError	"\(&\|+\|\-\|\*\*\|\/=\|??\|?=\|?\/=\|?<=\|?>=\|>=\|:=\|=>\)[<>=&+\*\\?:]\+"