blob: 487d3defbc60288eac3a61a475a8449247f5dab1 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
|
/*
* Copyright (C) 2012-2015 Panasonic Corporation
* Copyright (C) 2015-2016 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
/* U-Boot - Common settings for UniPhier Family */
#ifndef __CONFIG_UNIPHIER_COMMON_H__
#define __CONFIG_UNIPHIER_COMMON_H__
#define CONFIG_ARMV7_PSCI_1_0
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
/*-----------------------------------------------------------------------
* MMU and Cache Setting
*----------------------------------------------------------------------*/
/* Comment out the following to enable L1 cache */
/* #define CONFIG_SYS_ICACHE_OFF */
/* #define CONFIG_SYS_DCACHE_OFF */
#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
#define CONFIG_TIMESTAMP
/* FLASH related */
#define CONFIG_MTD_DEVICE
#define CONFIG_SMC911X_32_BIT
/* dummy: referenced by examples/standalone/smc911x_eeprom.c */
#define CONFIG_SMC911X_BASE 0
#ifdef CONFIG_MICRO_SUPPORT_CARD
#define CONFIG_SMC911X
#else
#define CONFIG_SYS_NO_FLASH
#endif
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_MAX_FLASH_SECT 256
#define CONFIG_SYS_MONITOR_BASE 0
#define CONFIG_SYS_MONITOR_LEN 0x00080000 /* 512KB */
#define CONFIG_SYS_FLASH_BASE 0
/*
* flash_toggle does not work for our support card.
* We need to use flash_status_poll.
*/
#define CONFIG_SYS_CFI_FLASH_STATUS_POLL
#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1
/* serial console configuration */
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_CMDLINE_EDITING /* add command line history */
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS 16 /* max number of command */
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
#define CONFIG_CONS_INDEX 1
/* #define CONFIG_ENV_IS_NOWHERE */
/* #define CONFIG_ENV_IS_IN_NAND */
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_ENV_OFFSET 0x80000
#define CONFIG_ENV_SIZE 0x2000
/* #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) */
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_SYS_MMC_ENV_PART 1
#ifdef CONFIG_ARMV8_MULTIENTRY
#define CPU_RELEASE_ADDR 0x80000000
#define COUNTER_FREQUENCY 50000000
#define CONFIG_GICV3
#define GICD_BASE 0x5fe00000
#if defined(CONFIG_ARCH_UNIPHIER_LD11)
#define GICR_BASE 0x5fe40000
#elif defined(CONFIG_ARCH_UNIPHIER_LD20)
#define GICR_BASE 0x5fe80000
#endif
#elif !defined(CONFIG_ARM64)
/* Time clock 1MHz */
#define CONFIG_SYS_TIMER_RATE 1000000
#endif
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_MAX_CHIPS 2
#define CONFIG_SYS_NAND_ONFI_DETECTION
#define CONFIG_NAND_DENALI_ECC_SIZE 1024
#ifdef CONFIG_ARCH_UNIPHIER_SLD3
#define CONFIG_SYS_NAND_REGS_BASE 0xf8100000
#define CONFIG_SYS_NAND_DATA_BASE 0xf8000000
#else
#define CONFIG_SYS_NAND_REGS_BASE 0x68100000
#define CONFIG_SYS_NAND_DATA_BASE 0x68000000
#endif
#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_DATA_BASE + 0x10)
#define CONFIG_SYS_NAND_USE_FLASH_BBT
#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
/* USB */
#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 4
#define CONFIG_FAT_WRITE
#define CONFIG_DOS_PARTITION
/* SD/MMC */
#define CONFIG_SUPPORT_EMMC_BOOT
#define CONFIG_GENERIC_MMC
/* memtest works on */
#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x01000000)
/*
* Network Configuration
*/
#define CONFIG_SERVERIP 192.168.11.1
#define CONFIG_IPADDR 192.168.11.10
#define CONFIG_GATEWAYIP 192.168.11.1
#define CONFIG_NETMASK 255.255.255.0
#define CONFIG_LOADADDR 0x84000000
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
#define CONFIG_CMDLINE_EDITING /* add command line history */
#define CONFIG_BOOTCOMMAND "run $bootmode"
#define CONFIG_ROOTPATH "/nfs/root/path"
#define CONFIG_NFSBOOTCOMMAND \
"setenv bootargs $bootargs root=/dev/nfs rw " \
"nfsroot=$serverip:$rootpath " \
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off;" \
"run __nfsboot"
#ifdef CONFIG_FIT
#define CONFIG_BOOTFILE "fitImage"
#define LINUXBOOT_ENV_SETTINGS \
"fit_addr=0x00100000\0" \
"fit_addr_r=0x84100000\0" \
"fit_size=0x00f00000\0" \
"norboot=setexpr fit_addr $nor_base + $fit_addr &&" \
"bootm $fit_addr\0" \
"nandboot=nand read $fit_addr_r $fit_addr $fit_size &&" \
"bootm $fit_addr_r\0" \
"tftpboot=tftpboot $fit_addr_r $bootfile &&" \
"bootm $fit_addr_r\0" \
"__nfsboot=run tftpboot\0"
#else
#ifdef CONFIG_ARM64
#define CONFIG_BOOTFILE "Image"
#define LINUXBOOT_CMD "booti"
#define KERNEL_ADDR_R "kernel_addr_r=0x80080000\0"
#define KERNEL_SIZE "kernel_size=0x00c00000\0"
#define RAMDISK_ADDR "ramdisk_addr=0x00e00000\0"
#else
#define CONFIG_BOOTFILE "zImage"
#define LINUXBOOT_CMD "bootz"
#define KERNEL_ADDR_R "kernel_addr_r=0x80208000\0"
#define KERNEL_SIZE "kernel_size=0x00800000\0"
#define RAMDISK_ADDR "ramdisk_addr=0x00a00000\0"
#endif
#define LINUXBOOT_ENV_SETTINGS \
"fdt_addr=0x00100000\0" \
"fdt_addr_r=0x84100000\0" \
"fdt_size=0x00008000\0" \
"kernel_addr=0x00200000\0" \
KERNEL_ADDR_R \
KERNEL_SIZE \
RAMDISK_ADDR \
"ramdisk_addr_r=0x84a00000\0" \
"ramdisk_size=0x00600000\0" \
"ramdisk_file=rootfs.cpio.uboot\0" \
"boot_common=setexpr bootm_low $kernel_addr_r '&' fe000000 &&" \
LINUXBOOT_CMD " $kernel_addr_r $ramdisk_addr_r $fdt_addr_r\0" \
"norboot=setexpr kernel_addr $nor_base + $kernel_addr &&" \
"setexpr kernel_size $kernel_size / 4 &&" \
"cp $kernel_addr $kernel_addr_r $kernel_size &&" \
"setexpr ramdisk_addr_r $nor_base + $ramdisk_addr &&" \
"setexpr fdt_addr_r $nor_base + $fdt_addr &&" \
"run boot_common\0" \
"nandboot=nand read $kernel_addr_r $kernel_addr $kernel_size &&" \
"nand read $ramdisk_addr_r $ramdisk_addr $ramdisk_size &&" \
"nand read $fdt_addr_r $fdt_addr $fdt_size &&" \
"run boot_common\0" \
"tftpboot=tftpboot $kernel_addr_r $bootfile &&" \
"tftpboot $ramdisk_addr_r $ramdisk_file &&" \
"tftpboot $fdt_addr_r $fdt_file &&" \
"run boot_common\0" \
"__nfsboot=tftpboot $kernel_addr_r $bootfile &&" \
"tftpboot $fdt_addr_r $fdt_file &&" \
"setenv ramdisk_addr_r - &&" \
"run boot_common\0"
#endif
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"verify=n\0" \
"nor_base=0x42000000\0" \
"sramupdate=setexpr tmp_addr $nor_base + 0x50000 &&" \
"tftpboot $tmp_addr u-boot-spl.bin &&" \
"setexpr tmp_addr $nor_base + 0x60000 &&" \
"tftpboot $tmp_addr u-boot.bin\0" \
"emmcupdate=mmcsetn &&" \
"mmc partconf $mmc_first_dev 0 1 1 &&" \
"tftpboot u-boot-spl.bin &&" \
"mmc write $loadaddr 0 80 &&" \
"tftpboot u-boot.bin &&" \
"mmc write $loadaddr 80 780\0" \
"nandupdate=nand erase 0 0x00100000 &&" \
"tftpboot u-boot-spl.bin &&" \
"nand write $loadaddr 0 0x00010000 &&" \
"tftpboot u-boot.bin &&" \
"nand write $loadaddr 0x00010000 0x000f0000\0" \
LINUXBOOT_ENV_SETTINGS
#define CONFIG_SYS_BOOTMAPSZ 0x20000000
#define CONFIG_SYS_SDRAM_BASE 0x80000000
#define CONFIG_NR_DRAM_BANKS 2
/* for LD20; the last 64 byte is used for dynamic DDR PHY training */
#define CONFIG_SYS_MEM_TOP_HIDE 64
#if defined(CONFIG_ARM64)
#define CONFIG_SPL_TEXT_BASE 0x30000000
#elif defined(CONFIG_ARCH_UNIPHIER_SLD3) || \
defined(CONFIG_ARCH_UNIPHIER_LD4) || \
defined(CONFIG_ARCH_UNIPHIER_SLD8)
#define CONFIG_SPL_TEXT_BASE 0x00040000
#else
#define CONFIG_SPL_TEXT_BASE 0x00100000
#endif
#if defined(CONFIG_ARCH_UNIPHIER_LD11)
#define CONFIG_SPL_STACK (0x30014c00)
#elif defined(CONFIG_ARCH_UNIPHIER_LD20)
#define CONFIG_SPL_STACK (0x3001c000)
#else
#define CONFIG_SPL_STACK (0x00100000)
#endif
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE)
#define CONFIG_PANIC_HANG
#define CONFIG_SPL_FRAMEWORK
#ifdef CONFIG_ARM64
#define CONFIG_SPL_BOARD_LOAD_IMAGE
#endif
#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x10000
/* subtract sizeof(struct image_header) */
#define CONFIG_SYS_UBOOT_BASE (0x60000 - 0x40)
#ifdef CONFIG_SPL
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
#define CONFIG_SPL_MAX_FOOTPRINT 0x10000
#define CONFIG_SPL_MAX_SIZE 0x10000
#if defined(CONFIG_ARCH_UNIPHIER_LD11)
#define CONFIG_SPL_BSS_START_ADDR 0x30012000
#elif defined(CONFIG_ARCH_UNIPHIER_LD20)
#define CONFIG_SPL_BSS_START_ADDR 0x30016000
#endif
#define CONFIG_SPL_BSS_MAX_SIZE 0x2000
#endif
#endif /* __CONFIG_UNIPHIER_COMMON_H__ */
|
