blob: d212a7f680fe5c89dee59a0415950c544ace592d (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
|
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2010,2011
* NVIDIA Corporation <www.nvidia.com>
* (C) Copyright 2011-2012
* Avionic Design GmbH <www.avionic-design.de>
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#include "tegra20-common.h"
/* High-level configuration options */
#define CONFIG_TEGRA_BOARD_STRING "Avionic Design Medcom-Wide"
/* Board-specific serial config */
#define CONFIG_TEGRA_ENABLE_UARTD /* UARTD: debug UART */
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
/* NAND support */
#define CONFIG_TEGRA_NAND
#define CONFIG_SYS_MAX_NAND_DEVICE 1
/* Environment in NAND, aligned to start of last sector */
#define CONFIG_ENV_OFFSET (SZ_512M - SZ_128K) /* 128K sectors */
#include "tegra-common-post.h"
#endif /* __CONFIG_H */
|
