1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
|
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2013
* NVIDIA Corporation <www.nvidia.com>
*/
/* Tegra124 high-level function multiplexing */
#include <common.h>
#include <asm/arch/clock.h>
#include <asm/arch/funcmux.h>
#include <asm/arch/pinmux.h>
int funcmux_select(enum periph_id id, int config)
{
int bad_config = config != FUNCMUX_DEFAULT;
switch (id) {
case PERIPH_ID_UART4:
switch (config) {
case FUNCMUX_UART4_GPIO: /* TXD,RXD,CTS,RTS */
pinmux_set_func(PMUX_PINGRP_PJ7, PMUX_FUNC_UARTD);
pinmux_set_func(PMUX_PINGRP_PB0, PMUX_FUNC_UARTD);
pinmux_set_func(PMUX_PINGRP_PB1, PMUX_FUNC_UARTD);
pinmux_set_func(PMUX_PINGRP_PK7, PMUX_FUNC_UARTD);
pinmux_set_io(PMUX_PINGRP_PJ7, PMUX_PIN_OUTPUT);
pinmux_set_io(PMUX_PINGRP_PB0, PMUX_PIN_INPUT);
pinmux_set_io(PMUX_PINGRP_PB1, PMUX_PIN_INPUT);
pinmux_set_io(PMUX_PINGRP_PK7, PMUX_PIN_OUTPUT);
pinmux_tristate_disable(PMUX_PINGRP_PJ7);
pinmux_tristate_disable(PMUX_PINGRP_PB0);
pinmux_tristate_disable(PMUX_PINGRP_PB1);
pinmux_tristate_disable(PMUX_PINGRP_PK7);
break;
}
break;
case PERIPH_ID_UART1:
switch (config) {
case FUNCMUX_UART1_KBC:
pinmux_set_func(PMUX_PINGRP_KB_ROW9_PS1,
PMUX_FUNC_UARTA);
pinmux_set_func(PMUX_PINGRP_KB_ROW10_PS2,
PMUX_FUNC_UARTA);
pinmux_set_io(PMUX_PINGRP_KB_ROW9_PS1, PMUX_PIN_OUTPUT);
pinmux_set_io(PMUX_PINGRP_KB_ROW10_PS2, PMUX_PIN_INPUT);
pinmux_tristate_disable(PMUX_PINGRP_KB_ROW9_PS1);
pinmux_tristate_disable(PMUX_PINGRP_KB_ROW10_PS2);
break;
}
break;
/* Add other periph IDs here as needed */
default:
debug("%s: invalid periph_id %d", __func__, id);
return -1;
}
if (bad_config) {
debug("%s: invalid config %d for periph_id %d", __func__,
config, id);
return -1;
}
return 0;
}
|
