blob: 84e1da42e340402bf7ab5e6b099b6a1ecf490560 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
|
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
*/
/* Tegra114 clock control functions */
#ifndef _TEGRA114_CLOCK_H_
#define _TEGRA114_CLOCK_H_
#include <asm/arch-tegra/clock.h>
/* CLK_RST_CONTROLLER_OSC_CTRL_0 */
#define OSC_FREQ_SHIFT 28
#define OSC_FREQ_MASK (0xF << OSC_FREQ_SHIFT)
/* CLK_RST_CONTROLLER_PLLC_MISC_0 */
#define PLLC_IDDQ (1 << 26)
#endif /* _TEGRA114_CLOCK_H_ */
|
