blob: 81d94701ad69d18f8f5dc1c9570dccda4dd8a7db (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
|
/*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef PHY_H
#define PHY_H
//
// Define
//
#define Enable_SearchPHYID //[ON] (Search vlid PHY ID)
#define Enable_CheckZeroPHYID //[ON] (Check PHY ID with value 0)
#ifdef Enable_CheckZeroPHYID
#define PHY_IS_VALID( dat ) ( ( (dat & 0xffff) != 0xffff ) && ( ( dat & 0xffff ) != 0x0 ) )
#else
#define PHY_IS_VALID( dat ) ( ( dat & 0xffff) != 0xffff )
#endif
// Define PHY basic register
#define PHY_REG_BMCR 0x00 // Basic Mode Control Register
#define PHY_REG_BMSR 0x01 // Basic Mode Status Register
#define PHY_REG_ID_1 0x02
#define PHY_REG_ID_2 0x03
#define PHY_ANER 0x06 // Auto-negotiation Expansion Register
#define PHY_GBCR 0x09 // 1000Base-T Control Register
#define PHY_SR 0x11 // PHY Specific Status Register
#define PHY_INER 0x12 // Interrupt Enable Register
#define TIME_OUT_PHY_RW 10000
#define TIME_OUT_PHY_Rst 10000
#define PHYID3_Mask 0xfc00 //0xffc0
/* --- Note for SettingPHY chip ---
void phy_xxxx (int loop_phy) {
if ( BurstEnable ) {
// IEEE test
}
else if (loop_phy) {
// Internal loop back
}
else {
// external loop back
}
}
----------------------------------- */
#endif // PHY_H
|
