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* implement Fastboot via USB OTG on bcm28155_ap boardsJiandong Zheng2015-07-221-0/+20
| | | | | Signed-off-by: Jiandong Zheng <jdzheng@broadcom.com> Signed-off-by: Steve Rae <srae@broadcom.com>
* g_dnl: add missing declarationSteve Rae2015-07-221-0/+1
| | | | | | Signed-off-by: Steve Rae <srae@broadcom.com> Tested-by: Lukasz Majewski <l.majewski@samsung.com> Test HW: Exynos 4210 (trats), Exynos 5422 (Odroid XU3)
* usb: board_usb_init and board_usb_cleanup calls in the fastboot commandPaul Kocialkowski2015-07-221-1/+1
| | | | | | | | | | | | | | | Each USB download function command calls board_usb_init before registering the USB gadget and board_usb_cleanup after de-registering it. On devices currently using fasboot, musb-new is usually initialized earlier, but some other boards might need the board_usb_init call to properly initialize musb-new. This requires adding an argument (the USB controller index) to the fastboot command, as it is currently done with other USB download gadget functions. Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Tested-by: Lukasz Majewski <l.majewski@samsung.com> Test HW: Odroid_XU3 (Exynos5422), trats (Exynos4210)
* usb: Fastboot function config for better consistency with other functionsPaul Kocialkowski2015-07-225-0/+5
| | | | | | | | | | | | USB download gadget functions such as thor and dfu have a separate config option for the USB gadget part of the code, independent from the command part. This switches the fastboot USB gadget to the same scheme, for better consistency. Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Tested-by: Lukasz Majewski <l.majewski@samsung.com> Test HW: Odroid_XU3 (Exynos5422), trats (Exynos4210)
* usb: USB download gadget and functions config options coherent namingPaul Kocialkowski2015-07-2218-47/+47
| | | | | | | | | | | | This introduces a coherent scheme for naming USB download gadget and functions config options. The download USB gadget config option is moved to CONFIG_USB_GADGET_DOWNLOAD for better consistency with other gadgets and each function's config option is moved to a CONFIG_USB_FUNCTION_ prefix. Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Tested-by: Lukasz Majewski <l.majewski@samsung.com> Test HW: Odroid_XU3 (Exynos5422), trats (Exynos4210)
* include: usb: Map USB controller base addresses for LS2085ANikhil Badola2015-07-221-0/+3
| | | | | | Map USB XHCI controller base addresses for LS2085A SOC Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
* include: usb: Move USB controller base address mappingNikhil Badola2015-07-221-0/+7
| | | | | | | | | Move USB controller Base address mapping from ls102xa immap to fsl xhci header. This is required to remove any warnings when controller base addresses are mapped for multiple platforms in their respective files. Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
* drivers: usb: fsl: Implement Erratum A-009116 for XHCI controllerNikhil Badola2015-07-221-6/+16
| | | | | | | This adjusts (micro)frame length to appropriate value thus avoiding USB devices to time out over a longer run Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
* ls1021aqds: Enable USB IP supportRamneek Mehresh2015-07-221-5/+17
| | | | | | | Enable USB IP support for both EHCI and XHCI for ls1021aqds platform Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
* ls1021atwr: Enable USB IP supportRamneek Mehresh2015-07-221-0/+38
| | | | | | | Enable USB IP support for both EHCI and XHCI for ls1021atwr platform Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
* usb: fsl: Add XHCI driver supportRamneek Mehresh2015-07-221-0/+54
| | | | | | Add xhci driver support for all FSL socs Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
* usb: xhci: keystone: Remove common dwc3 drv functions callsRamneek Mehresh2015-07-221-0/+1
| | | | | | | Remove all redundant dwc3 driver function calls that are defined by dwc3 driver Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
* usb: xhci: omap: Remove common dwc3 drv functions callsRamneek Mehresh2015-07-223-0/+3
| | | | | | | Remove all redundant dwc3 driver function calls that are defined by dwc3 driver Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
* usb: xhci: exynos: Remove common dwc3 drv functions callsRamneek Mehresh2015-07-221-0/+1
| | | | | | | Remove all redundant dwc3 driver function calls that are defined by dwc3 driver Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
* usb: dwc3: Add DWC3 controller driver supportRamneek Mehresh2015-07-221-0/+6
| | | | | | Add support for DWC3 XHCI controller driver Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
* Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini2015-07-2013-75/+299
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| * armv8/ls2085ardb: Enable DSPI flash support for LS2085ARDBHaikun Wang2015-07-201-0/+8
| | | | | | | | | | | | | | Enable DSPI flash related configurations for LS2085ARDB. Signed-off-by: Haikun Wang <haikun.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * armv8/ls2085aqds: Enable DSPI flash support for LS2085AQDSHaikun Wang2015-07-201-0/+9
| | | | | | | | | | | | | | Enable DSPI flash related configurations. Signed-off-by: Haikun Wang <haikun.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * arm/ls102xa: Add PSCI support for ls102xaWang Dongsheng2015-07-202-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | Base on PSCI services, implement CPU_ON/CPU_OFF for ls102xa platform. Tested on LS1021AQDS, LS1021ATWR. Test CPU hotplug times: 60K Test kernel boot times: 1.2K Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com> Acked-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * board/ls2085a: Increase kernel_size value in env variablePrabhakar Kushwaha2015-07-203-3/+3
| | | | | | | | | | | | | | | | | | Linux itb image size has been increased from 30MB. So updating kernel_size to 40MB in env variable. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * board/ls2085rdb: Export functions for standalone AQ FW load appsPrabhakar Kushwaha2015-07-203-1/+26
| | | | | | | | | | | | | | | | | | Export functions required by Aquntia PHY firmware load application. functions are memset, strcpy, mdelay, mdio_get_current_dev, phy_find_by_mask, mdio_phydev_for_ethname and miiphy_set_current_dev Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * armv8/fsl-lsch3: partition stream IDsStuart Yoder2015-07-202-4/+1
| | | | | | | | | | | | | | | | | | | | | | | | Stream IDs on ls2085a devices are not hardwired and are programmed by sw. There are a limited number of stream IDs available, and the partitioning of them is scenario dependent. This header defines the partitioning between legacy, PCI, and DPAA2 devices. Signed-off-by: Stuart Yoder <stuart.yoder@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * drivers: fsl-mc: Update flibs to mc-0.6.0.1Prabhakar Kushwaha2015-07-205-52/+191
| | | | | | | | | | | | | | | | | | | | Update flibs changes to mc-0.6.0.1 for dpmang, dprc, dpni and dpio objects Also rename qbman_portal_ce/ci_paddr to qbman_portal_ce/ci_offset in dpio_attr. These are now offsets from the SoC QBMan portals base. Signed-off-by: J. German Rivera <German.Rivera@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * drivers/fsl-mc: Autoload AOIP image from NOR flashJ. German Rivera2015-07-203-0/+6
| | | | | | | | | | | | | | | | | | Load AIOP image from NOR flash into DDR so that the MC firmware the MC fw can start it at boot time Signed-off-by: J. German Rivera <German.Rivera@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * armv8/ls2085a: enable debug serverStuart Yoder2015-07-201-0/+1
| | | | | | | | | | | | Signed-off-by: Stuart Yoder <stuart.yoder at freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * armv8/fsl-lsch3: Support 256M mem split for MC & dbg-srvrPrabhakar Kushwaha2015-07-201-3/+9
| | | | | | | | | | | | | | | | | | | | | | | | The agreed split of the top of memory is 256M for debug server and 256M for MC. This patch implements the split. In addition, the MC mem must be 512MB aligned, so the amount of memory to hide must be 512MB to achieve that alignment. Signed-off-by: Stuart Yoder <stuart.yoder@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * armv8/ls2085ardb: Fix SPD address error on early boardsYork Sun2015-07-201-2/+2
| | | | | | | | | | | | | | | | | | Board rev C and earlier has duplicated SPD address on 2nd DDR controller slots. It is fixed on rev D and later. SPD addresses need to be updated accordingly. Signed-off-by: York Sun <yorksun at freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
| * driver/ddr/fsl: Add a hook to update SPD addressYork Sun2015-07-201-0/+3
| | | | | | | | | | | | | | | | In case SPD address changes between board revisions, updating SPD address can be called from board file. Signed-off-by: York Sun <yorksun at freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
| * armv8/ls2085a: Avoid hard-coding for board name printPrabhakar Kushwaha2015-07-202-5/+0
| | | | | | | | | | | | | | | | | | | | | | LS2085A supports 6 personalities i.e. LS2045AE, LS2045A, LS2080AE, LS2080A, LS2085AE and LS2085A personlities. Instead of hard-coding, board name should change as per selected personality. Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * armv8/ls2085a: Increase the supported kernel sizeBhupesh Sharma2015-07-203-5/+8
| | | | | | | | | | | | | | | | | | | | | | Increases the kernel size supported for LS2085A platforms:- - Update environment variables - Add ramdisk_size in bootargs env variable - Define CONFIG_SYS_BOOTM_LEN to 64MB Signed-off-by: Bhupesh Sharma <bhupesh.sharma at freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * armv8/ls2085rdb: Update PCA9547PW slave addressPrabhakar Kushwaha2015-07-201-2/+2
| | | | | | | | | | | | | | | | Primary Mux on I2C1 controller has slave address as 0x75. So update its address. Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * armv8/ls2085a: Update LS2085a PCIe compatiblePrabhakar Kushwaha2015-07-201-1/+2
| | | | | | | | | | | | | | | | | | Compatible field "fsl,20851a-pcie" is not correct. So update it to "fsl,ls2085a-pcie" Signed-off-by: Minghuan Lian <Minghuan.Lian at freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * armv8/ls2085a: Enable "date" command for QDS and RDBPriyanka Jain2015-07-202-0/+2
| | | | | | | | | | | | | | | | Enable "date" command for QDS and RDB boards Signed-off-by: Priyanka Jain <Priyanka.Jain at freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * armv8/ls2085ardb: add hwconfig setting for eSDHCYangbo Lu2015-07-201-0/+2
| | | | | | | | | | | | | | | | | | Add hwconfig setting for eSDHC since it shares some pins with other IP block. Signed-off-by: Yangbo Lu <yangbo.lu at freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * armv8/ls2085ardb: Add eth & phy firmware loading supportPrabhakar Kushwaha2015-07-201-0/+23
| | | | | | | | | | | | | | | | | | | | Add support for board eth initialization and support for loading phy firmware. PHY firmware needs to be loaded from board_eth_init() because all the MACs are not initialized by ldpaa_eth driver. Signed-off-by: pankaj chauhan <pankaj.chauhan at freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | libfdt: fix description of fdt_get_string()Masahiro Yamada2015-07-201-1/+1
| | | | | | | | | | | | | | | | | | Looks like this comment was copied from that of fdt_get_string_index(). Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Fixes: 5094eb408a5d ("fdt: Add functions to retrieve strings") Acked-by: Simon Glass <sjg@chromium.org>
* | fdt: prevent clearing memory node if there are no banksAndre Przywara2015-07-201-0/+26
|/ | | | | | | | | | | | | Avoid clearing the reg property in the memory DT node if no memory banks have been specified for a board (CONFIG_NR_DRAM_BANKS == 0). This allows boards to let U-Boot skip the DT memory tinkering in case other firmware has already setup the node properly before. This should be safe as all callers of fdt_fixup_memory_banks that use a computed <banks> value put at least 1 in there. Add some documentation comments to the header file. Signed-off-by: Andre Przywara <osp@andrep.de> Acked-by: Simon Glass <sjg@chromium.org>
* Merge git://git.denx.de/u-boot-x86Tom Rini2015-07-157-27/+39
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| * pci: Configure expansion ROM during auto config processBin Meng2015-07-141-9/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently PCI expansion ROM address is assigned by a call to pciauto_setup_rom() outside of the pci auto config process. This does not work when expansion ROM is on a device behind PCI bridge where bridge's memory limit register was already programmed to a value that does not cover the newly assigned expansion ROM address. To fix this, we should configure the ROM address during the auto config process. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org>
| * dm: x86: baytrail: Correct PCI region 3 when driver model is usedSimon Glass2015-07-141-0/+1
| | | | | | | | | | | | | | | | Commit afbbd413a fixed this for non-driver-model. Make sure that the driver model code handles this also. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * dm: x86: minnowmax: Move PCI to use driver modelSimon Glass2015-07-141-0/+1
| | | | | | | | | | | | | | | | | | Adjust minnowmax to use driver model for PCI. This requires adding a device tree node to specify the ranges, removing the board-specific PCI code and ensuring that the host bridge is configured. Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Simon Glass <sjg@chromium.org>
| * dm: spi: Enable environment for minnowmaxSimon Glass2015-07-141-3/+2
| | | | | | | | | | | | | | | | Enable a SPI environment and store it in a suitable place. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
| * x86: Configure VESA parameters before loading Linux kernelBin Meng2015-07-141-2/+2
| | | | | | | | | | | | | | | | | | Store VESA parameters to Linux setup header so that vesafb driver in the kernel could work. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Jian Luo <jian.luo4@boschrexroth.de>
| * x86: crownbay: Enable graphics supportBin Meng2015-07-141-7/+7
| | | | | | | | | | | | | | | | | | | | | | Enable graphics support on Intel Crown Bay board With the help of vgabios for Intel TunnelCreek IGD. Tested with an external LVDS panel connected to X4 connector and SDVO adapter connected to X9 connector on the board. Signed-off-by: Jian Luo <jian.luo4@boschrexroth.de> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: Move VGA option rom macros to KconfigBin Meng2015-07-142-6/+0
| | | | | | | | | | | | | | | | | | | | Move X86_OPTION_ROM_FILE & X86_OPTION_ROM_ADDR to arch/x86/Kconfig and rename them to VGA_BIOS_FILE & VGA_BIOS_ADDR which depend on HAVE_VGA_BIOS. The new names are consistent with other x86 binary blob options like HAVE_FSP/FSP_FILE/FSP_ADDR. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * dm: pci: Use the correct hose when configuring devicesSimon Glass2015-07-141-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | Only the PCI controller has access to the PCI region information. Make sure to use the controller (rather than any attached bridges) when configuring devices. This corrects a failure to scan and configure devices when driver model is enabled for PCI. Also add a comment to explain the problem. Signed-off-by: Simon Glass <sjg@chromium.org>
| * dm: cpu: Add a new get_count method to cpu uclassBin Meng2015-07-141-0/+16
| | | | | | | | | | | | | | | | Introduce a new method 'get_count' in the UCLASS_CPU ops to get the number of CPUs in the system. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini2015-07-141-3/+18
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| * stv0991: enable cadence qspi controller & spi flashVikas Manocha2015-07-031-0/+15
| | | | | | | | | | | | | | | | This patch does all the board configurations required to use the qspi controller & attached spi flash memory. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> Reviewed-by: Jagannadh Teki <jteki@openedev.com>
| * stv0991: remove define CONFIG_OF_SEPARATE from board fileVikas Manocha2015-07-031-1/+0
| | | | | | | | | | | | | | | | CONFIG_OF_SEPARATE is default define with CONFIG_OF_CONTROL, removing this define from the board file to avoid multiple definition warning. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> Reviewed-by: Jagannadh Teki <jteki@openedev.com>
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