delta/u-boot.git - gitlab.denx.de: u-boot/u-boot.git

	Commit message (Collapse)	Author	Age	Files	Lines
*	fsl-layerscape: Consolidate registers space defination for CCI-400 bus	Ashish Kumar	2017-09-11	1	-0/+51
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	CoreLink Cache Coherent Interconnect (CCI) provides full cache coherency between two clusters of multi-core CPUs and I/O coherency for devices and I/O masters. This patch add new config option SYS_FSL_HAS_CCI400 and moves existing register space definaton of CCI-400 bus to fsl_immap to be shared. CONFIG_SYS_CCI400_ADDR is replaced with SYS_CCI400_OFFSET in Kconfig. Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> [YS: revised commit message, squashed patches for armv8 and armv7] Reviewed-by: York Sun <york.sun@nxp.com>
*	driver/ddr/fsl: Add more debug registers	York Sun	2016-09-14	1	-2/+1
\| \| \| \| \| \| \|	32 more debug registers are added for newer DDR controllers. Signed-off-by: York Sun <york.sun@nxp.com> Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
*	driver/ddr/fsl: Remove deskew_cntrl register	York Sun	2015-05-20	1	-3/+1
\| \| \| \| \| \| \|	This register is reserved and shouldn't have been exposed. Accessing it may have unexpected result on different SoCs. Signed-off-by: York Sun <yorksun@freescale.com>
*	driver/ddr/fsl: Add DDR4 support to Freescale DDR driver	York Sun	2014-04-22	1	-4/+31
\| \| \| \| \| \| \|	Mostly reusing DDR3 driver, this patch adds DDR4 SPD handling, register calculation and programming. Signed-off-by: York Sun <yorksun@freescale.com>
*	Driver/DDR: combine ccsr_ddr for 83xx, 85xx and 86xx	York Sun	2013-11-25	1	-0/+112
	Fix ccsr_ddr structure to avoid using typedef. Combine DDR2 and DDR3 structure for 83xx, 85xx and 86xx. Signed-off-by: York Sun <yorksun@freescale.com>